* [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support
@ 2021-10-26 4:12 Radha Mohan Chintakuntla
2021-10-26 4:12 ` [dpdk-dev] [PATCH 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
` (4 more replies)
0 siblings, 5 replies; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-10-26 4:12 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
Add base support as ROC(Rest of Chip) API which will be used by PMD
dmadev driver.
This patch adds routines to init, fini, configure the DPI DMA device
found in Marvell's CN9k or CN10k SoC familes.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
drivers/common/cnxk/hw/dpi.h | 136 ++++++++++++++++++++
drivers/common/cnxk/meson.build | 1 +
drivers/common/cnxk/roc_api.h | 4 +
drivers/common/cnxk/roc_dpi.c | 193 +++++++++++++++++++++++++++++
drivers/common/cnxk/roc_dpi.h | 44 +++++++
drivers/common/cnxk/roc_dpi_priv.h | 40 ++++++
drivers/common/cnxk/roc_platform.h | 1 +
drivers/common/cnxk/roc_priv.h | 3 +
drivers/common/cnxk/version.map | 5 +
9 files changed, 427 insertions(+)
create mode 100644 drivers/common/cnxk/hw/dpi.h
create mode 100644 drivers/common/cnxk/roc_dpi.c
create mode 100644 drivers/common/cnxk/roc_dpi.h
create mode 100644 drivers/common/cnxk/roc_dpi_priv.h
diff --git a/drivers/common/cnxk/hw/dpi.h b/drivers/common/cnxk/hw/dpi.h
new file mode 100644
index 0000000000..aa1e66aa11
--- /dev/null
+++ b/drivers/common/cnxk/hw/dpi.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+/**
+ * DPI device HW definitions.
+ */
+#ifndef __DEV_DPI_HW_H__
+#define __DEV_DPI_HW_H__
+
+#include <stdint.h>
+
+/** @cond __INTERNAL_DOCUMENTATION__ */
+
+/* DPI VF register offsets from VF_BAR0 */
+#define DPI_VDMA_EN (0x0)
+#define DPI_VDMA_REQQ_CTL (0x8)
+#define DPI_VDMA_DBELL (0x10)
+#define DPI_VDMA_SADDR (0x18)
+#define DPI_VDMA_COUNTS (0x20)
+#define DPI_VDMA_NADDR (0x28)
+#define DPI_VDMA_IWBUSY (0x30)
+#define DPI_VDMA_CNT (0x38)
+#define DPI_VF_INT (0x100)
+#define DPI_VF_INT_W1S (0x108)
+#define DPI_VF_INT_ENA_W1C (0x110)
+#define DPI_VF_INT_ENA_W1S (0x118)
+
+/**
+ * Enumeration dpi_hdr_xtype_e
+ *
+ * DPI Transfer Type Enumeration
+ * Enumerates the pointer type in DPI_DMA_INSTR_HDR_S[XTYPE].
+ */
+#define DPI_XTYPE_OUTBOUND (0)
+#define DPI_XTYPE_INBOUND (1)
+#define DPI_XTYPE_INTERNAL_ONLY (2)
+#define DPI_XTYPE_EXTERNAL_ONLY (3)
+#define DPI_HDR_XTYPE_MASK 0x3
+#define DPI_HDR_PT_MASK 0x3
+#define DPI_HDR_TT_MASK 0x3
+#define DPI_HDR_GRP_MASK 0x3FF
+#define DPI_HDR_FUNC_MASK 0xFFFF
+
+/* Big endian data bit position in DMA local pointer */
+#define DPI_LPTR_BED_BIT_POS (60)
+
+#define DPI_MIN_CMD_SIZE 8
+#define DPI_MAX_CMD_SIZE 64
+
+/**
+ * Structure dpi_instr_hdr_s for CN9K
+ *
+ * DPI DMA Instruction Header Format
+ */
+union dpi_instr_hdr_s {
+ uint64_t u[4];
+ struct dpi_dma_instr_hdr_s_s {
+ uint64_t tag : 32;
+ uint64_t tt : 2;
+ uint64_t grp : 10;
+ uint64_t reserved_44_47 : 4;
+ uint64_t nfst : 4;
+ uint64_t reserved_52_53 : 2;
+ uint64_t nlst : 4;
+ uint64_t reserved_58_63 : 6;
+ /* Word 0 - End */
+ uint64_t aura : 20;
+ uint64_t func : 16;
+ uint64_t pt : 2;
+ uint64_t reserved_102 : 1;
+ uint64_t pvfe : 1;
+ uint64_t fl : 1;
+ uint64_t ii : 1;
+ uint64_t fi : 1;
+ uint64_t ca : 1;
+ uint64_t csel : 1;
+ uint64_t reserved_109_111 : 3;
+ uint64_t xtype : 2;
+ uint64_t reserved_114_119 : 6;
+ uint64_t fport : 2;
+ uint64_t reserved_122_123 : 2;
+ uint64_t lport : 2;
+ uint64_t reserved_126_127 : 2;
+ /* Word 1 - End */
+ uint64_t ptr : 64;
+ /* Word 2 - End */
+ uint64_t reserved_192_255 : 64;
+ /* Word 3 - End */
+ } s;
+};
+
+/**
+ * Structure dpi_cn10k_instr_hdr_s for CN10K
+ *
+ * DPI DMA Instruction Header Format
+ */
+union dpi_cn10k_instr_hdr_s {
+ uint64_t u[4];
+ struct dpi_cn10k_dma_instr_hdr_s_s {
+ uint64_t nfst : 4;
+ uint64_t reserved_4_5 : 2;
+ uint64_t nlst : 4;
+ uint64_t reserved_10_11 : 2;
+ uint64_t pvfe : 1;
+ uint64_t reserved_13 : 1;
+ uint64_t func : 16;
+ uint64_t aura : 20;
+ uint64_t xtype : 2;
+ uint64_t reserved_52_53 : 2;
+ uint64_t pt : 2;
+ uint64_t fport : 2;
+ uint64_t reserved_58_59 : 2;
+ uint64_t lport : 2;
+ uint64_t reserved_62_63 : 2;
+ /* Word 0 - End */
+ uint64_t ptr : 64;
+ /* Word 1 - End */
+ uint64_t tag : 32;
+ uint64_t tt : 2;
+ uint64_t grp : 10;
+ uint64_t reserved_172_173 : 2;
+ uint64_t fl : 1;
+ uint64_t ii : 1;
+ uint64_t fi : 1;
+ uint64_t ca : 1;
+ uint64_t csel : 1;
+ uint64_t reserved_179_191 : 3;
+ /* Word 2 - End */
+ uint64_t reserved_192_255 : 64;
+ /* Word 3 - End */
+ } s;
+};
+
+/** @endcond */
+
+#endif /*__DEV_DPI_HW_H__*/
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index d9871a6b45..d0aeb6b68c 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -19,6 +19,7 @@ sources = files(
'roc_cpt.c',
'roc_cpt_debug.c',
'roc_dev.c',
+ 'roc_dpi.c',
'roc_hash.c',
'roc_idev.c',
'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index b8f3667c6c..359d31327a 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -33,6 +33,7 @@
/* HW structure definition */
#include "hw/cpt.h"
+#include "hw/dpi.h"
#include "hw/nix.h"
#include "hw/npa.h"
#include "hw/npc.h"
@@ -86,6 +87,9 @@
#include "roc_ie_ot.h"
#include "roc_se.h"
+/* DPI */
+#include "roc_dpi.h"
+
/* HASH computation */
#include "roc_hash.h"
diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c
new file mode 100644
index 0000000000..a9613d82f1
--- /dev/null
+++ b/drivers/common/cnxk/roc_dpi.c
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+#include <fcntl.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
+
+static inline int
+send_msg_to_pf(struct plt_pci_addr *pci_addr, const char *value, int size)
+{
+ char buf[255] = {0};
+ int res, fd;
+
+ res = snprintf(
+ buf, sizeof(buf), "/sys/bus/pci/devices/" PCI_PRI_FMT "/%s",
+ pci_addr->domain, pci_addr->bus, DPI_PF_DBDF_DEVICE & 0x7,
+ DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
+
+ if ((res < 0) || ((size_t)res > sizeof(buf)))
+ return -ERANGE;
+
+ fd = open(buf, O_WRONLY);
+ if (fd < 0)
+ return -EACCES;
+
+ res = write(fd, value, size);
+ close(fd);
+ if (res < 0)
+ return -EACCES;
+
+ return 0;
+}
+
+int
+roc_dpi_queue_start(struct roc_dpi *dpi)
+{
+ plt_write64(0x1, dpi->rbase + DPI_VDMA_EN);
+ return 0;
+}
+
+int
+roc_dpi_queue_stop(struct roc_dpi *dpi)
+{
+ plt_write64(0x0, dpi->rbase + DPI_VDMA_EN);
+ return 0;
+}
+
+int
+roc_dpi_queue_configure(struct roc_dpi *roc_dpi)
+{
+ struct plt_pci_device *pci_dev;
+ const struct plt_memzone *dpi_mz;
+ dpi_mbox_msg_t mbox_msg;
+ struct npa_pool_s pool;
+ struct npa_aura_s aura;
+ int rc, count, buflen;
+ uint64_t aura_handle;
+ plt_iova_t iova;
+ char name[32];
+
+ if (!roc_dpi) {
+ plt_err("roc_dpi is NULL");
+ return -EINVAL;
+ }
+
+ pci_dev = roc_dpi->pci_dev;
+ memset(&pool, 0, sizeof(struct npa_pool_s));
+ pool.nat_align = 1;
+
+ memset(&aura, 0, sizeof(aura));
+ rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE,
+ DPI_CMD_QUEUE_BUFS, &aura, &pool);
+ if (rc) {
+ plt_err("Failed to create NPA pool, err %d\n", rc);
+ return rc;
+ }
+
+ snprintf(name, sizeof(name), "dpimem%d", roc_dpi->vfid);
+ buflen = DPI_CMD_QUEUE_SIZE * DPI_CMD_QUEUE_BUFS;
+ dpi_mz = plt_memzone_reserve_aligned(name, buflen, 0,
+ DPI_CMD_QUEUE_SIZE);
+ if (dpi_mz == NULL) {
+ plt_err("dpi memzone reserve failed");
+ rc = -ENOMEM;
+ goto err1;
+ }
+
+ roc_dpi->mz = dpi_mz;
+ iova = dpi_mz->iova;
+ for (count = 0; count < DPI_CMD_QUEUE_BUFS; count++) {
+ roc_npa_aura_op_free(aura_handle, 0, iova);
+ iova += DPI_CMD_QUEUE_SIZE;
+ }
+
+ roc_dpi->chunk_base = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
+ if (!roc_dpi->chunk_base) {
+ plt_err("Failed to alloc buffer from NPA aura");
+ rc = -ENOMEM;
+ goto err2;
+ }
+
+ roc_dpi->chunk_next = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
+ if (!roc_dpi->chunk_next) {
+ plt_err("Failed to alloc buffer from NPA aura");
+ rc = -ENOMEM;
+ goto err2;
+ }
+
+ roc_dpi->aura_handle = aura_handle;
+ /* subtract 2 as they have already been alloc'ed above */
+ roc_dpi->pool_size_m1 = (DPI_CMD_QUEUE_SIZE >> 3) - 2;
+
+ plt_write64(0x0, roc_dpi->rbase + DPI_VDMA_REQQ_CTL);
+ plt_write64(((uint64_t)(roc_dpi->chunk_base) >> 7) << 7,
+ roc_dpi->rbase + DPI_VDMA_SADDR);
+ mbox_msg.u[0] = 0;
+ mbox_msg.u[1] = 0;
+ /* DPI PF driver expects vfid starts from index 0 */
+ mbox_msg.s.vfid = roc_dpi->vfid;
+ mbox_msg.s.cmd = DPI_QUEUE_OPEN;
+ mbox_msg.s.csize = DPI_CMD_QUEUE_SIZE;
+ mbox_msg.s.aura = roc_npa_aura_handle_to_aura(aura_handle);
+ mbox_msg.s.sso_pf_func = idev_sso_pffunc_get();
+ mbox_msg.s.npa_pf_func = idev_npa_pffunc_get();
+
+ rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
+ sizeof(dpi_mbox_msg_t));
+ if (rc < 0) {
+ plt_err("Failed to send mbox message %d to DPI PF, err %d",
+ mbox_msg.s.cmd, rc);
+ goto err2;
+ }
+
+ return rc;
+
+err2:
+ roc_npa_pool_destroy(aura_handle);
+err1:
+ plt_memzone_free(dpi_mz);
+ return rc;
+}
+
+int
+roc_dpi_dev_init(struct roc_dpi *roc_dpi)
+{
+ struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
+ uint16_t vfid;
+
+ roc_dpi->rbase = pci_dev->mem_resource[0].addr;
+ vfid = ((pci_dev->addr.devid & 0x1F) << 3) |
+ (pci_dev->addr.function & 0x7);
+ vfid -= 1;
+ roc_dpi->vfid = vfid;
+ plt_spinlock_init(&roc_dpi->chunk_lock);
+
+ return 0;
+}
+
+int
+roc_dpi_dev_fini(struct roc_dpi *roc_dpi)
+{
+ struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
+ dpi_mbox_msg_t mbox_msg;
+ uint64_t reg;
+ int rc;
+
+ /* Wait for SADDR to become idle */
+ reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
+ while (!(reg & BIT_ULL(63)))
+ reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
+
+ mbox_msg.u[0] = 0;
+ mbox_msg.u[1] = 0;
+ mbox_msg.s.vfid = roc_dpi->vfid;
+ mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
+
+ rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
+ sizeof(dpi_mbox_msg_t));
+ if (rc < 0)
+ plt_err("Failed to send mbox message %d to DPI PF, err %d",
+ mbox_msg.s.cmd, rc);
+
+ roc_npa_pool_destroy(roc_dpi->aura_handle);
+ plt_memzone_free(roc_dpi->mz);
+
+ return rc;
+}
diff --git a/drivers/common/cnxk/roc_dpi.h b/drivers/common/cnxk/roc_dpi.h
new file mode 100644
index 0000000000..c2e6d997ea
--- /dev/null
+++ b/drivers/common/cnxk/roc_dpi.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_DPI_H_
+#define _ROC_DPI_H_
+
+struct roc_dpi_args {
+ uint8_t num_ssegs;
+ uint8_t num_dsegs;
+ uint8_t comp_type;
+ uint8_t direction;
+ uint8_t sdevice;
+ uint8_t ddevice;
+ uint8_t swap;
+ uint8_t use_lock : 1;
+ uint8_t tt : 7;
+ uint16_t func;
+ uint16_t grp;
+ uint32_t tag;
+ uint64_t comp_ptr;
+};
+
+struct roc_dpi {
+ struct plt_pci_device *pci_dev;
+ const struct plt_memzone *mz;
+ uint8_t *rbase;
+ uint16_t vfid;
+ uint16_t pool_size_m1;
+ uint16_t chunk_head;
+ uint64_t *chunk_base;
+ uint64_t *chunk_next;
+ uint64_t aura_handle;
+ plt_spinlock_t chunk_lock;
+} __plt_cache_aligned;
+
+int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi);
+int __roc_api roc_dpi_dev_fini(struct roc_dpi *roc_dpi);
+
+int __roc_api roc_dpi_queue_configure(struct roc_dpi *dpi);
+int __roc_api roc_dpi_queue_start(struct roc_dpi *dpi);
+int __roc_api roc_dpi_queue_stop(struct roc_dpi *dpi);
+
+#endif
diff --git a/drivers/common/cnxk/roc_dpi_priv.h b/drivers/common/cnxk/roc_dpi_priv.h
new file mode 100644
index 0000000000..92953fbcfc
--- /dev/null
+++ b/drivers/common/cnxk/roc_dpi_priv.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_DPI_PRIV_H_
+#define _ROC_DPI_PRIV_H_
+
+#define DPI_MAX_VFS 8
+
+/* DPI PF DBDF information macros */
+#define DPI_PF_DBDF_DEVICE 0
+#define DPI_PF_DBDF_FUNCTION 0
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+
+#define DPI_CMD_QUEUE_SIZE 4096
+#define DPI_CMD_QUEUE_BUFS 1024
+
+typedef union dpi_mbox_msg_t {
+ uint64_t u[2];
+ struct dpi_mbox_message_s {
+ /* VF ID to configure */
+ uint64_t vfid : 4;
+ /* Command code */
+ uint64_t cmd : 4;
+ /* Command buffer size in 8-byte words */
+ uint64_t csize : 14;
+ /* aura of the command buffer */
+ uint64_t aura : 20;
+ /* SSO PF function */
+ uint64_t sso_pf_func : 16;
+ /* NPA PF function */
+ uint64_t npa_pf_func : 16;
+ } s;
+} dpi_mbox_msg_t;
+
+#endif
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 5da23fe5f8..61d4781209 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -69,6 +69,7 @@
#define __roc_api __rte_internal
#define plt_iova_t rte_iova_t
+#define plt_pci_addr rte_pci_addr
#define plt_pci_device rte_pci_device
#define plt_pci_read_config rte_pci_read_config
#define plt_pci_find_ext_capability rte_pci_find_ext_capability
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index f72bbd568f..782b90cf8d 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -41,4 +41,7 @@
/* NIX Inline dev */
#include "roc_nix_inl_priv.h"
+/* DPI */
+#include "roc_dpi_priv.h"
+
#endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 8d4d42f476..3edc42cfd6 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -68,6 +68,11 @@ INTERNAL {
roc_cpt_lmtline_init;
roc_cpt_parse_hdr_dump;
roc_cpt_rxc_time_cfg;
+ roc_dpi_dev_init;
+ roc_dpi_dev_fini;
+ roc_dpi_queue_configure;
+ roc_dpi_queue_start;
+ roc_dpi_queue_stop;
roc_error_msg_get;
roc_hash_sha1_gen;
roc_hash_sha256_gen;
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH 2/4] dma/cnxk: create and initialize dmadev on pci probe
2021-10-26 4:12 [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support Radha Mohan Chintakuntla
@ 2021-10-26 4:12 ` Radha Mohan Chintakuntla
2021-10-26 8:36 ` Jerin Jacob
2021-10-26 4:12 ` [dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
` (3 subsequent siblings)
4 siblings, 1 reply; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-10-26 4:12 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
This patch creates and initializes a dmadev device on pci probe.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
MAINTAINERS | 7 +-
doc/guides/dmadevs/cnxk.rst | 53 +++++++++++++++
doc/guides/dmadevs/index.rst | 1 +
drivers/dma/cnxk/cnxk_dmadev.c | 119 +++++++++++++++++++++++++++++++++
drivers/dma/cnxk/cnxk_dmadev.h | 11 +++
drivers/dma/cnxk/meson.build | 7 ++
drivers/dma/meson.build | 1 +
7 files changed, 198 insertions(+), 1 deletion(-)
create mode 100644 doc/guides/dmadevs/cnxk.rst
create mode 100644 drivers/dma/cnxk/cnxk_dmadev.c
create mode 100644 drivers/dma/cnxk/cnxk_dmadev.h
create mode 100644 drivers/dma/cnxk/meson.build
diff --git a/MAINTAINERS b/MAINTAINERS
index be2c9b6815..cdc2d98a6b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1186,7 +1186,6 @@ F: drivers/compress/zlib/
F: doc/guides/compressdevs/zlib.rst
F: doc/guides/compressdevs/features/zlib.ini
-
DMAdev Drivers
--------------
@@ -1202,6 +1201,12 @@ M: Conor Walsh <conor.walsh@intel.com>
F: drivers/dma/ioat/
F: doc/guides/dmadevs/ioat.rst
+Marvell CNXK DPI DMA
+M: Radha Mohan Chintakuntla <radhac@marvell.com>
+M: Veerasenareddy Burru <vburru@marvell.com>
+F: drivers/dma/cnxk/
+F: doc/guides/dmadevs/cnxk.rst
+
RegEx Drivers
-------------
diff --git a/doc/guides/dmadevs/cnxk.rst b/doc/guides/dmadevs/cnxk.rst
new file mode 100644
index 0000000000..8ae7c1f8cd
--- /dev/null
+++ b/doc/guides/dmadevs/cnxk.rst
@@ -0,0 +1,53 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2021 Marvell International Ltd.
+
+.. include:: <isonum.txt>
+
+CNXK DMA Device Driver
+======================
+
+The ``cnxk`` dmadev driver provides a poll-mode driver (PMD) for Marvell DPI DMA
+Hardware Accelerator block found in OCTEONTX2 and OCTEONTX3 family of SoCs. Each
+DMA queue is exposed as a VF function when SRIOV is enabled.
+
+The block supports following modes of DMA transfers
+
+#. Internal - DMA within SoC DRAM to DRAM
+
+#. Inbound - Host DRAM to SoC DRAM when SoC is in PCIe Endpoint
+
+#. Outbound - SoC DRAM to Host DRAM when SoC is in PCIe Endpoint
+
+Device Setup
+-------------
+The ``dpdk-devbind.py`` script, included with DPDK, can be used to show the
+presence of supported hardware. Running ``dpdk-devbind.py --status-dev dma``
+will show all the CNXK DMA devices.
+
+Devices using VFIO drivers
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The HW devices to be used will need to be bound to a user-space IO driver for use.
+The ``dpdk-devbind.py`` script can be used to view the state of the devices
+and to bind them to a suitable DPDK-supported driver, such as ``vfio-pci``.
+For example::
+
+ $ dpdk-devbind.py -b vfio-pci 0000:05:00.1
+
+Device Probing and Initialization
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To use the devices from an application, the dmadev API can be used.
+CNXK DMA device configuration requirements:
+
+* Only one ``vchan`` is supported per device.
+* CNXK DMA devices do not support silent mode.
+
+Once configured, the device can then be made ready for use by calling the
+ ``rte_dma_start()`` API.
+
+Performing Data Copies
+~~~~~~~~~~~~~~~~~~~~~~~
+
+Refer to the :ref:`Enqueue / Dequeue APIs <dmadev_enqueue_dequeue>` section of the dmadev library
+documentation for details on operation enqueue and submission API usage.
diff --git a/doc/guides/dmadevs/index.rst b/doc/guides/dmadevs/index.rst
index 20476039a5..227fa00c68 100644
--- a/doc/guides/dmadevs/index.rst
+++ b/doc/guides/dmadevs/index.rst
@@ -11,5 +11,6 @@ an application through DMA API.
:maxdepth: 2
:numbered:
+ cnxk
idxd
ioat
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
new file mode 100644
index 0000000000..620766743d
--- /dev/null
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2021 Marvell International Ltd.
+ */
+
+#include <string.h>
+#include <unistd.h>
+
+#include <rte_bus.h>
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_eal.h>
+#include <rte_lcore.h>
+#include <rte_mempool.h>
+#include <rte_pci.h>
+#include <rte_dmadev.h>
+#include <rte_dmadev_pmd.h>
+
+#include <roc_api.h>
+#include <cnxk_dmadev.h>
+
+static int
+cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
+ struct rte_pci_device *pci_dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = NULL;
+ char name[RTE_DEV_NAME_MAX_LEN];
+ struct rte_dma_dev *dmadev;
+ struct roc_dpi *rdpi = NULL;
+ int rc;
+
+ if (!pci_dev->mem_resource[0].addr)
+ return -ENODEV;
+
+ rc = roc_plt_init();
+ if (rc) {
+ plt_err("Failed to initialize platform model, rc=%d", rc);
+ return rc;
+ }
+ memset(name, 0, sizeof(name));
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+ dmadev = rte_dma_pmd_allocate(name, pci_dev->device.numa_node,
+ sizeof(*dpivf));
+ if (dmadev == NULL) {
+ plt_err("dma device allocation failed for %s", name);
+ return -ENOMEM;
+ }
+
+ dpivf = dmadev->data->dev_private;
+
+ dmadev->device = &pci_dev->device;
+ dmadev->fp_obj->dev_private = dpivf;
+
+ rdpi = &dpivf->rdpi;
+
+ rdpi->pci_dev = pci_dev;
+ rc = roc_dpi_dev_init(rdpi);
+ if (rc < 0)
+ goto err_out_free;
+
+ return 0;
+
+err_out_free:
+ if (dmadev)
+ rte_dma_pmd_release(name);
+
+ return rc;
+}
+
+static int
+cnxk_dmadev_remove(struct rte_pci_device *pci_dev)
+{
+ char name[RTE_DEV_NAME_MAX_LEN];
+ struct rte_dma_dev *dmadev;
+ struct cnxk_dpi_vf_s *dpivf;
+ int dev_id;
+
+ memset(name, 0, sizeof(name));
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+ dev_id = rte_dma_get_dev_id_by_name(name);
+ if (dev_id < 0) {
+ plt_err("Invalid device ID");
+ return -EINVAL;
+ }
+
+ dmadev = &rte_dma_devices[dev_id];
+ if (!dmadev) {
+ plt_err("dmadev with name %s not found\n", name);
+ return -ENODEV;
+ }
+
+ dpivf = dmadev->fp_obj->dev_private;
+ roc_dpi_queue_stop(&dpivf->rdpi);
+ roc_dpi_dev_fini(&dpivf->rdpi);
+
+ return rte_dma_pmd_release(name);
+}
+
+static const struct rte_pci_id cnxk_dma_pci_map[] = {
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVID_CNXK_DPI_VF)
+ },
+ {
+ .vendor_id = 0,
+ },
+};
+
+static struct rte_pci_driver cnxk_dmadev = {
+ .id_table = cnxk_dma_pci_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+ .probe = cnxk_dmadev_probe,
+ .remove = cnxk_dmadev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(cnxk_dmadev_pci_driver, cnxk_dmadev);
+RTE_PMD_REGISTER_PCI_TABLE(cnxk_dmadev_pci_driver, cnxk_dma_pci_map);
+RTE_PMD_REGISTER_KMOD_DEP(cnxk_dmadev_pci_driver, "vfio-pci");
diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
new file mode 100644
index 0000000000..9e0bb7b2ce
--- /dev/null
+++ b/drivers/dma/cnxk/cnxk_dmadev.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+#ifndef _CNXK_DMADEV_H_
+#define _CNXK_DMADEV_H_
+
+struct cnxk_dpi_vf_s {
+ struct roc_dpi rdpi;
+};
+
+#endif
diff --git a/drivers/dma/cnxk/meson.build b/drivers/dma/cnxk/meson.build
new file mode 100644
index 0000000000..9489d6e6dc
--- /dev/null
+++ b/drivers/dma/cnxk/meson.build
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2021 Marvell International Ltd.
+#
+
+deps += ['bus_pci', 'common_cnxk', 'dmadev']
+sources = files('cnxk_dmadev.c')
+headers = files('cnxk_dmadev.h')
diff --git a/drivers/dma/meson.build b/drivers/dma/meson.build
index a69418ce9b..c562c8b429 100644
--- a/drivers/dma/meson.build
+++ b/drivers/dma/meson.build
@@ -2,6 +2,7 @@
# Copyright 2021 HiSilicon Limited
drivers = [
+ 'cnxk',
'idxd',
'ioat',
'skeleton',
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations
2021-10-26 4:12 [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support Radha Mohan Chintakuntla
2021-10-26 4:12 ` [dpdk-dev] [PATCH 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
@ 2021-10-26 4:12 ` Radha Mohan Chintakuntla
2021-10-26 8:41 ` Jerin Jacob
2021-10-26 4:13 ` [dpdk-dev] [PATCH 4/4] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
` (2 subsequent siblings)
4 siblings, 1 reply; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-10-26 4:12 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
Add functions for the dmadev vchan setup and DMA operations.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
drivers/dma/cnxk/cnxk_dmadev.c | 322 +++++++++++++++++++++++++++++++++
drivers/dma/cnxk/cnxk_dmadev.h | 53 ++++++
drivers/dma/cnxk/version.map | 3 +
3 files changed, 378 insertions(+)
create mode 100644 drivers/dma/cnxk/version.map
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
index 620766743d..8434579aa2 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.c
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -18,6 +18,322 @@
#include <roc_api.h>
#include <cnxk_dmadev.h>
+static int
+cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
+ struct rte_dma_info *dev_info, uint32_t size)
+{
+ RTE_SET_USED(dev);
+ RTE_SET_USED(size);
+
+ dev_info->max_vchans = 1;
+ dev_info->nb_vchans = 1;
+ dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
+ RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
+ RTE_DMA_CAPA_OPS_COPY;
+ dev_info->max_desc = DPI_MAX_DESC;
+ dev_info->min_desc = 1;
+ dev_info->max_sges = DPI_MAX_POINTER;
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_configure(struct rte_dma_dev *dev,
+ const struct rte_dma_conf *conf, uint32_t conf_sz)
+{
+ struct cnxk_dpi_vf_s *dpivf = NULL;
+ int rc = 0;
+
+ RTE_SET_USED(conf);
+ RTE_SET_USED(conf);
+ RTE_SET_USED(conf_sz);
+ RTE_SET_USED(conf_sz);
+ dpivf = dev->fp_obj->dev_private;
+ rc = roc_dpi_queue_configure(&dpivf->rdpi);
+ if (rc < 0)
+ plt_err("DMA queue configure failed err = %d", rc);
+
+ return rc;
+}
+
+static int
+cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
+ const struct rte_dma_vchan_conf *conf,
+ uint32_t conf_sz)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+ struct cnxk_dpi_compl_s *comp_data;
+ int i;
+
+ RTE_SET_USED(vchan);
+ RTE_SET_USED(conf_sz);
+
+ switch (conf->direction) {
+ case RTE_DMA_DIR_DEV_TO_MEM:
+ dpivf->conf.direction = DPI_XTYPE_INBOUND;
+ dpivf->conf.src_port = conf->src_port.pcie.coreid;
+ dpivf->conf.dst_port = 0;
+ break;
+ case RTE_DMA_DIR_MEM_TO_DEV:
+ dpivf->conf.direction = DPI_XTYPE_OUTBOUND;
+ dpivf->conf.src_port = 0;
+ dpivf->conf.dst_port = conf->dst_port.pcie.coreid;
+ break;
+ case RTE_DMA_DIR_MEM_TO_MEM:
+ dpivf->conf.direction = DPI_XTYPE_INTERNAL_ONLY;
+ dpivf->conf.src_port = 0;
+ dpivf->conf.dst_port = 0;
+ break;
+ case RTE_DMA_DIR_DEV_TO_DEV:
+ dpivf->conf.direction = DPI_XTYPE_EXTERNAL_ONLY;
+ dpivf->conf.src_port = conf->src_port.pcie.coreid;
+ dpivf->conf.dst_port = conf->src_port.pcie.coreid;
+ };
+
+ for (i = 0; i < conf->nb_desc; i++) {
+ comp_data = rte_zmalloc(NULL, sizeof(*comp_data), 0);
+ dpivf->conf.c_desc.compl_ptr[i] = comp_data;
+ };
+ dpivf->conf.c_desc.max_cnt = DPI_MAX_DESC;
+ dpivf->conf.c_desc.head = 0;
+ dpivf->conf.c_desc.tail = 0;
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_start(struct rte_dma_dev *dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+
+ roc_dpi_queue_start(&dpivf->rdpi);
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_stop(struct rte_dma_dev *dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+
+ roc_dpi_queue_stop(&dpivf->rdpi);
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_close(struct rte_dma_dev *dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+
+ roc_dpi_queue_stop(&dpivf->rdpi);
+ roc_dpi_dev_fini(&dpivf->rdpi);
+
+ return 0;
+}
+
+static inline int
+__dpi_queue_write(struct roc_dpi *dpi, uint64_t *cmds, int cmd_count)
+{
+ uint64_t *ptr = dpi->chunk_base;
+
+ if ((cmd_count < DPI_MIN_CMD_SIZE) || (cmd_count > DPI_MAX_CMD_SIZE) ||
+ cmds == NULL)
+ return -EINVAL;
+
+ /*
+ * Normally there is plenty of room in the current buffer for the
+ * command
+ */
+ if (dpi->chunk_head + cmd_count < dpi->pool_size_m1) {
+ ptr += dpi->chunk_head;
+ dpi->chunk_head += cmd_count;
+ while (cmd_count--)
+ *ptr++ = *cmds++;
+ } else {
+ int count;
+ uint64_t *new_buff = dpi->chunk_next;
+
+ dpi->chunk_next =
+ (void *)roc_npa_aura_op_alloc(dpi->aura_handle, 0);
+ if (!dpi->chunk_next) {
+ plt_err("Failed to alloc next buffer from NPA");
+ return -ENOMEM;
+ }
+
+ /*
+ * Figure out how many cmd words will fit in this buffer.
+ * One location will be needed for the next buffer pointer.
+ */
+ count = dpi->pool_size_m1 - dpi->chunk_head;
+ ptr += dpi->chunk_head;
+ cmd_count -= count;
+ while (count--)
+ *ptr++ = *cmds++;
+
+ /*
+ * chunk next ptr is 2 DWORDS
+ * second DWORD is reserved.
+ */
+ *ptr++ = (uint64_t)new_buff;
+ *ptr = 0;
+
+ /*
+ * The current buffer is full and has a link to the next
+ * buffers. Time to write the rest of the commands into the new
+ * buffer.
+ */
+ dpi->chunk_base = new_buff;
+ dpi->chunk_head = cmd_count;
+ ptr = new_buff;
+ while (cmd_count--)
+ *ptr++ = *cmds++;
+
+ /* queue index may be greater than pool size */
+ if (dpi->chunk_head >= dpi->pool_size_m1) {
+ new_buff = dpi->chunk_next;
+ dpi->chunk_next =
+ (void *)roc_npa_aura_op_alloc(dpi->aura_handle,
+ 0);
+ if (!dpi->chunk_next) {
+ plt_err("Failed to alloc next buffer from NPA");
+ return -ENOMEM;
+ }
+ /* Write next buffer address */
+ *ptr = (uint64_t)new_buff;
+ dpi->chunk_base = new_buff;
+ dpi->chunk_head = 0;
+ }
+ }
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
+ rte_iova_t dst, uint32_t length, uint64_t flags)
+{
+ uint64_t cmd[DPI_MAX_CMD_SIZE] = {0};
+ union dpi_instr_hdr_s *header = (union dpi_instr_hdr_s *)&cmd[0];
+ rte_iova_t fptr, lptr;
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ struct cnxk_dpi_compl_s *comp_ptr;
+ int num_words = 0;
+ int rc;
+
+ RTE_SET_USED(vchan);
+
+ header->s.xtype = dpivf->conf.direction;
+ header->s.pt = DPI_HDR_PT_ZBW_CA;
+ comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
+ comp_ptr->cdata = DPI_REQ_CDATA;
+ header->s.ptr = (uint64_t)comp_ptr;
+ STRM_INC(dpivf->conf.c_desc);
+
+ /* pvfe should be set for inbound and outbound only */
+ if (header->s.xtype <= 1)
+ header->s.pvfe = 1;
+ num_words += 4;
+
+ header->s.nfst = 1;
+ header->s.nlst = 1;
+ /*
+ * For inbound case, src pointers are last pointers.
+ * For all other cases, src pointers are first pointers.
+ */
+ if (header->s.xtype == DPI_XTYPE_INBOUND) {
+ fptr = dst;
+ lptr = src;
+ header->s.fport = dpivf->conf.dst_port & 0x3;
+ header->s.lport = dpivf->conf.src_port & 0x3;
+ } else {
+ fptr = src;
+ lptr = dst;
+ header->s.fport = dpivf->conf.src_port & 0x3;
+ header->s.lport = dpivf->conf.dst_port & 0x3;
+ }
+
+ cmd[num_words++] = length;
+ cmd[num_words++] = fptr;
+ cmd[num_words++] = length;
+ cmd[num_words++] = lptr;
+
+ rc = __dpi_queue_write(&dpivf->rdpi, cmd, num_words);
+ if (!rc) {
+ if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
+ rte_wmb();
+ plt_write64(num_words,
+ dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+ }
+ dpivf->num_words = num_words;
+ }
+
+ return rc;
+}
+
+static uint16_t
+cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
+ uint16_t *last_idx, bool *has_error)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ int cnt;
+
+ RTE_SET_USED(vchan);
+ RTE_SET_USED(last_idx);
+ RTE_SET_USED(has_error);
+ for (cnt = 0; cnt < nb_cpls; cnt++) {
+ struct cnxk_dpi_compl_s *comp_ptr =
+ dpivf->conf.c_desc.compl_ptr[cnt];
+
+ if (comp_ptr->cdata)
+ break;
+ }
+
+ dpivf->conf.c_desc.tail = cnt;
+
+ return cnt;
+}
+
+static uint16_t
+cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan,
+ const uint16_t nb_cpls, uint16_t *last_idx,
+ enum rte_dma_status_code *status)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ int cnt;
+
+ RTE_SET_USED(vchan);
+ RTE_SET_USED(last_idx);
+ for (cnt = 0; cnt < nb_cpls; cnt++) {
+ struct cnxk_dpi_compl_s *comp_ptr =
+ dpivf->conf.c_desc.compl_ptr[cnt];
+ status[cnt] = comp_ptr->cdata;
+ }
+
+ dpivf->conf.c_desc.tail = 0;
+ return cnt;
+}
+
+static int
+cnxk_dmadev_submit(void *dev_private, uint16_t vchan __rte_unused)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+
+ rte_wmb();
+ plt_write64(dpivf->num_words, dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+
+ return 0;
+}
+
+static const struct rte_dma_dev_ops cnxk_dmadev_ops = {
+ .dev_info_get = cnxk_dmadev_info_get,
+ .dev_configure = cnxk_dmadev_configure,
+ .dev_start = cnxk_dmadev_start,
+ .dev_stop = cnxk_dmadev_stop,
+ .vchan_setup = cnxk_dmadev_vchan_setup,
+ .dev_close = cnxk_dmadev_close,
+};
+
static int
cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
struct rte_pci_device *pci_dev)
@@ -50,6 +366,12 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
dmadev->device = &pci_dev->device;
dmadev->fp_obj->dev_private = dpivf;
+ dmadev->dev_ops = &cnxk_dmadev_ops;
+
+ dmadev->fp_obj->copy = cnxk_dmadev_copy;
+ dmadev->fp_obj->submit = cnxk_dmadev_submit;
+ dmadev->fp_obj->completed = cnxk_dmadev_completed;
+ dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
rdpi = &dpivf->rdpi;
diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
index 9e0bb7b2ce..ce301a5945 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.h
+++ b/drivers/dma/cnxk/cnxk_dmadev.h
@@ -4,8 +4,61 @@
#ifndef _CNXK_DMADEV_H_
#define _CNXK_DMADEV_H_
+#define DPI_MAX_POINTER 15
+#define DPI_QUEUE_STOP 0x0
+#define DPI_QUEUE_START 0x1
+#define STRM_INC(s) ((s).tail = ((s).tail + 1) % (s).max_cnt)
+#define DPI_MAX_DESC DPI_MAX_POINTER
+
+/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */
+#define DPI_XTYPE_OUTBOUND (0)
+#define DPI_XTYPE_INBOUND (1)
+#define DPI_XTYPE_INTERNAL_ONLY (2)
+#define DPI_XTYPE_EXTERNAL_ONLY (3)
+#define DPI_XTYPE_MASK 0x3
+#define DPI_HDR_PT_ZBW_CA 0x0
+#define DPI_HDR_PT_ZBW_NC 0x1
+#define DPI_HDR_PT_WQP 0x2
+#define DPI_HDR_PT_WQP_NOSTATUS 0x0
+#define DPI_HDR_PT_WQP_STATUSCA 0x1
+#define DPI_HDR_PT_WQP_STATUSNC 0x3
+#define DPI_HDR_PT_CNT 0x3
+#define DPI_HDR_PT_MASK 0x3
+#define DPI_W0_TT_MASK 0x3
+#define DPI_W0_GRP_MASK 0x3FF
+
+/* Set Completion data to 0xFF when request submitted,
+ * upon successful request completion engine reset to completion status
+ */
+#define DPI_REQ_CDATA 0xFF
+
+#define DPI_MIN_CMD_SIZE 8
+#define DPI_MAX_CMD_SIZE 64
+
+struct cnxk_dpi_compl_s {
+ uint64_t cdata;
+ void *cb_data;
+};
+
+struct cnxk_dpi_cdesc_data_s {
+ struct cnxk_dpi_compl_s *compl_ptr[DPI_MAX_DESC];
+ uint16_t max_cnt;
+ uint16_t head;
+ uint16_t tail;
+};
+
+struct cnxk_dpi_queue_conf {
+ uint8_t direction;
+ uint8_t src_port;
+ uint8_t dst_port;
+ uint64_t comp_ptr;
+ struct cnxk_dpi_cdesc_data_s c_desc;
+};
+
struct cnxk_dpi_vf_s {
struct roc_dpi rdpi;
+ struct cnxk_dpi_queue_conf conf;
+ uint32_t num_words;
};
#endif
diff --git a/drivers/dma/cnxk/version.map b/drivers/dma/cnxk/version.map
new file mode 100644
index 0000000000..4a76d1d52d
--- /dev/null
+++ b/drivers/dma/cnxk/version.map
@@ -0,0 +1,3 @@
+DPDK_21 {
+ local: *;
+};
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH 4/4] dma/cnxk: add copy_sg function
2021-10-26 4:12 [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support Radha Mohan Chintakuntla
2021-10-26 4:12 ` [dpdk-dev] [PATCH 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
2021-10-26 4:12 ` [dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
@ 2021-10-26 4:13 ` Radha Mohan Chintakuntla
2021-10-26 8:42 ` Jerin Jacob
2021-10-26 8:33 ` [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support Jerin Jacob
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 " Radha Mohan Chintakuntla
4 siblings, 1 reply; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-10-26 4:13 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
Add the copy_sg function that will do the multiple DMA transfers of
different sizes and different source/destination as well.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
drivers/dma/cnxk/cnxk_dmadev.c | 80 +++++++++++++++++++++++++++++++++-
1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
index 8434579aa2..f15ea16c5f 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.c
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -29,7 +29,7 @@ cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
dev_info->nb_vchans = 1;
dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
- RTE_DMA_CAPA_OPS_COPY;
+ RTE_DMA_CAPA_OPS_COPY | RTE_DMA_CAPA_OPS_COPY_SG;
dev_info->max_desc = DPI_MAX_DESC;
dev_info->min_desc = 1;
dev_info->max_sges = DPI_MAX_POINTER;
@@ -294,6 +294,83 @@ cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
return cnt;
}
+static int
+cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan,
+ const struct rte_dma_sge *src,
+ const struct rte_dma_sge *dst,
+ uint16_t nb_src, uint16_t nb_dst, uint64_t flags)
+{
+ uint64_t cmd[DPI_MAX_CMD_SIZE] = {0};
+ union dpi_instr_hdr_s *header = (union dpi_instr_hdr_s *)&cmd[0];
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ const struct rte_dma_sge *fptr, *lptr;
+ struct cnxk_dpi_compl_s *comp_ptr;
+ int num_words = 0;
+ int i, rc;
+
+ RTE_SET_USED(vchan);
+
+ header->s.xtype = dpivf->conf.direction;
+ header->s.pt = DPI_HDR_PT_ZBW_CA;
+ header->s.grp = 0;
+ header->s.tag = 0;
+ header->s.tt = 0;
+ header->s.func = 0;
+ comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
+ comp_ptr->cdata = DPI_REQ_CDATA;
+ header->s.ptr = (uint64_t)comp_ptr;
+ STRM_INC(dpivf->conf.c_desc);
+
+ /* pvfs should be set for inbound and outbound only */
+ if (header->s.xtype <= 1)
+ header->s.pvfe = 1;
+ num_words += 4;
+
+ /*
+ * For inbound case, src pointers are last pointers.
+ * For all other cases, src pointers are first pointers.
+ */
+ if (header->s.xtype == DPI_XTYPE_INBOUND) {
+ header->s.nfst = nb_dst & 0xf;
+ header->s.nlst = nb_src & 0xf;
+ fptr = &dst[0];
+ lptr = &src[0];
+ header->s.fport = dpivf->conf.dst_port & 0x3;
+ header->s.lport = dpivf->conf.src_port & 0x3;
+ } else {
+ header->s.nfst = nb_src & 0xf;
+ header->s.nlst = nb_dst & 0xf;
+ fptr = &src[0];
+ lptr = &dst[0];
+ header->s.fport = dpivf->conf.src_port & 0x3;
+ header->s.lport = dpivf->conf.dst_port & 0x3;
+ }
+
+ for (i = 0; i < header->s.nfst; i++) {
+ cmd[num_words++] = (uint64_t)fptr->length;
+ cmd[num_words++] = fptr->addr;
+ fptr++;
+ }
+
+ for (i = 0; i < header->s.nlst; i++) {
+ cmd[num_words++] = (uint64_t)lptr->length;
+ cmd[num_words++] = lptr->addr;
+ lptr++;
+ }
+
+ rc = __dpi_queue_write(&dpivf->rdpi, cmd, num_words);
+ if (!rc) {
+ if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
+ rte_wmb();
+ plt_write64(num_words,
+ dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+ }
+ dpivf->num_words = num_words;
+ }
+
+ return rc;
+}
+
static uint16_t
cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan,
const uint16_t nb_cpls, uint16_t *last_idx,
@@ -369,6 +446,7 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
dmadev->dev_ops = &cnxk_dmadev_ops;
dmadev->fp_obj->copy = cnxk_dmadev_copy;
+ dmadev->fp_obj->copy_sg = cnxk_dmadev_copy_sg;
dmadev->fp_obj->submit = cnxk_dmadev_submit;
dmadev->fp_obj->completed = cnxk_dmadev_completed;
dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support
2021-10-26 4:12 [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support Radha Mohan Chintakuntla
` (2 preceding siblings ...)
2021-10-26 4:13 ` [dpdk-dev] [PATCH 4/4] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
@ 2021-10-26 8:33 ` Jerin Jacob
2021-10-26 15:57 ` Radha Mohan
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 " Radha Mohan Chintakuntla
4 siblings, 1 reply; 32+ messages in thread
From: Jerin Jacob @ 2021-10-26 8:33 UTC (permalink / raw)
To: Radha Mohan Chintakuntla
Cc: Thomas Monjalon, fengchengwen, Nithin Dabilpuram, Kiran Kumar K,
Sunil Kumar Kori, Satha Koteswara Rao Kottidi, Jerin Jacob,
Satananda Burla, dpdk-dev
On Tue, Oct 26, 2021 at 9:43 AM Radha Mohan Chintakuntla
<radhac@marvell.com> wrote:
>
> Add base support as ROC(Rest of Chip) API which will be used by PMD
> dmadev driver.
>
> This patch adds routines to init, fini, configure the DPI DMA device
> found in Marvell's CN9k or CN10k SoC familes.
families
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
> drivers/common/cnxk/hw/dpi.h | 136 ++++++++++++++++++++
> drivers/common/cnxk/meson.build | 1 +
> drivers/common/cnxk/roc_api.h | 4 +
> drivers/common/cnxk/roc_dpi.c | 193 +++++++++++++++++++++++++++++
> drivers/common/cnxk/roc_dpi.h | 44 +++++++
> drivers/common/cnxk/roc_dpi_priv.h | 40 ++++++
> drivers/common/cnxk/roc_platform.h | 1 +
> drivers/common/cnxk/roc_priv.h | 3 +
> drivers/common/cnxk/version.map | 5 +
> 9 files changed, 427 insertions(+)
> create mode 100644 drivers/common/cnxk/hw/dpi.h
> create mode 100644 drivers/common/cnxk/roc_dpi.c
> create mode 100644 drivers/common/cnxk/roc_dpi.h
> create mode 100644 drivers/common/cnxk/roc_dpi_priv.h
>
> diff --git a/drivers/common/cnxk/hw/dpi.h b/drivers/common/cnxk/hw/dpi.h
> new file mode 100644
> index 0000000000..aa1e66aa11
> --- /dev/null
> +++ b/drivers/common/cnxk/hw/dpi.h
> @@ -0,0 +1,136 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +/**
> + * DPI device HW definitions.
> + */
> +#ifndef __DEV_DPI_HW_H__
> +#define __DEV_DPI_HW_H__
> +
> +#include <stdint.h>
> +
> +/** @cond __INTERNAL_DOCUMENTATION__ */
This is not required.
> +
> +/* DPI VF register offsets from VF_BAR0 */
> +#define DPI_VDMA_EN (0x0)
> +#define DPI_VDMA_REQQ_CTL (0x8)
> +#define DPI_VDMA_DBELL (0x10)
> +#define DPI_VDMA_SADDR (0x18)
> +#define DPI_VDMA_COUNTS (0x20)
> +#define DPI_VDMA_NADDR (0x28)
> +#define DPI_VDMA_IWBUSY (0x30)
> +#define DPI_VDMA_CNT (0x38)
> +#define DPI_VF_INT (0x100)
> +#define DPI_VF_INT_W1S (0x108)
> +#define DPI_VF_INT_ENA_W1C (0x110)
> +#define DPI_VF_INT_ENA_W1S (0x118)
> +
> +/**
> + * Enumeration dpi_hdr_xtype_e
> + *
> + * DPI Transfer Type Enumeration
> + * Enumerates the pointer type in DPI_DMA_INSTR_HDR_S[XTYPE].
> + */
> +#define DPI_XTYPE_OUTBOUND (0)
> +#define DPI_XTYPE_INBOUND (1)
> +#define DPI_XTYPE_INTERNAL_ONLY (2)
> +#define DPI_XTYPE_EXTERNAL_ONLY (3)
> +#define DPI_HDR_XTYPE_MASK 0x3
> +#define DPI_HDR_PT_MASK 0x3
> +#define DPI_HDR_TT_MASK 0x3
> +#define DPI_HDR_GRP_MASK 0x3FF
> +#define DPI_HDR_FUNC_MASK 0xFFFF
> +
> +/* Big endian data bit position in DMA local pointer */
> +#define DPI_LPTR_BED_BIT_POS (60)
> +
> +#define DPI_MIN_CMD_SIZE 8
> +#define DPI_MAX_CMD_SIZE 64
> +
> +/**
> + * Structure dpi_instr_hdr_s for CN9K
> + *
> + * DPI DMA Instruction Header Format
> + */
> +union dpi_instr_hdr_s {
> + uint64_t u[4];
> + struct dpi_dma_instr_hdr_s_s {
> + uint64_t tag : 32;
> + uint64_t tt : 2;
> + uint64_t grp : 10;
> + uint64_t reserved_44_47 : 4;
> + uint64_t nfst : 4;
> + uint64_t reserved_52_53 : 2;
> + uint64_t nlst : 4;
> + uint64_t reserved_58_63 : 6;
> + /* Word 0 - End */
> + uint64_t aura : 20;
> + uint64_t func : 16;
> + uint64_t pt : 2;
> + uint64_t reserved_102 : 1;
> + uint64_t pvfe : 1;
> + uint64_t fl : 1;
> + uint64_t ii : 1;
> + uint64_t fi : 1;
> + uint64_t ca : 1;
> + uint64_t csel : 1;
> + uint64_t reserved_109_111 : 3;
> + uint64_t xtype : 2;
> + uint64_t reserved_114_119 : 6;
> + uint64_t fport : 2;
> + uint64_t reserved_122_123 : 2;
> + uint64_t lport : 2;
> + uint64_t reserved_126_127 : 2;
> + /* Word 1 - End */
> + uint64_t ptr : 64;
> + /* Word 2 - End */
> + uint64_t reserved_192_255 : 64;
> + /* Word 3 - End */
> + } s;
> +};
> +
> +/**
> + * Structure dpi_cn10k_instr_hdr_s for CN10K
> + *
> + * DPI DMA Instruction Header Format
> + */
> +union dpi_cn10k_instr_hdr_s {
> + uint64_t u[4];
> + struct dpi_cn10k_dma_instr_hdr_s_s {
> + uint64_t nfst : 4;
> + uint64_t reserved_4_5 : 2;
> + uint64_t nlst : 4;
> + uint64_t reserved_10_11 : 2;
> + uint64_t pvfe : 1;
> + uint64_t reserved_13 : 1;
> + uint64_t func : 16;
> + uint64_t aura : 20;
> + uint64_t xtype : 2;
> + uint64_t reserved_52_53 : 2;
> + uint64_t pt : 2;
> + uint64_t fport : 2;
> + uint64_t reserved_58_59 : 2;
> + uint64_t lport : 2;
> + uint64_t reserved_62_63 : 2;
> + /* Word 0 - End */
> + uint64_t ptr : 64;
> + /* Word 1 - End */
> + uint64_t tag : 32;
> + uint64_t tt : 2;
> + uint64_t grp : 10;
> + uint64_t reserved_172_173 : 2;
> + uint64_t fl : 1;
> + uint64_t ii : 1;
> + uint64_t fi : 1;
> + uint64_t ca : 1;
> + uint64_t csel : 1;
> + uint64_t reserved_179_191 : 3;
> + /* Word 2 - End */
> + uint64_t reserved_192_255 : 64;
> + /* Word 3 - End */
> + } s;
> +};
> +
> +/** @endcond */
This is not required.
> +
> +#endif /*__DEV_DPI_HW_H__*/
> diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
> index d9871a6b45..d0aeb6b68c 100644
> --- a/drivers/common/cnxk/meson.build
> +++ b/drivers/common/cnxk/meson.build
> @@ -19,6 +19,7 @@ sources = files(
> 'roc_cpt.c',
> 'roc_cpt_debug.c',
> 'roc_dev.c',
> + 'roc_dpi.c',
> 'roc_hash.c',
> 'roc_idev.c',
> 'roc_irq.c',
> diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
> index b8f3667c6c..359d31327a 100644
> --- a/drivers/common/cnxk/roc_api.h
> +++ b/drivers/common/cnxk/roc_api.h
> @@ -33,6 +33,7 @@
>
> /* HW structure definition */
> #include "hw/cpt.h"
> +#include "hw/dpi.h"
> #include "hw/nix.h"
> #include "hw/npa.h"
> #include "hw/npc.h"
> @@ -86,6 +87,9 @@
> #include "roc_ie_ot.h"
> #include "roc_se.h"
>
> +/* DPI */
> +#include "roc_dpi.h"
> +
> /* HASH computation */
> #include "roc_hash.h"
>
> diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c
> new file mode 100644
> index 0000000000..a9613d82f1
> --- /dev/null
> +++ b/drivers/common/cnxk/roc_dpi.c
> @@ -0,0 +1,193 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +
> +#include "roc_api.h"
> +#include "roc_priv.h"
move internal headers file after the public ones with a new line.
> +#include <fcntl.h>
> +#include <sys/stat.h>
> +#include <sys/types.h>
> +#include <unistd.h>
> +
> +#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
> +
> +static inline int
> +send_msg_to_pf(struct plt_pci_addr *pci_addr, const char *value, int size)
> +{
> + char buf[255] = {0};
> + int res, fd;
> +
> + res = snprintf(
> + buf, sizeof(buf), "/sys/bus/pci/devices/" PCI_PRI_FMT "/%s",
> + pci_addr->domain, pci_addr->bus, DPI_PF_DBDF_DEVICE & 0x7,
> + DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
> +
> + if ((res < 0) || ((size_t)res > sizeof(buf)))
> + return -ERANGE;
> +
> + fd = open(buf, O_WRONLY);
> + if (fd < 0)
> + return -EACCES;
> +
> + res = write(fd, value, size);
> + close(fd);
> + if (res < 0)
> + return -EACCES;
> +
> + return 0;
> +}
> +
> +int
> +roc_dpi_queue_start(struct roc_dpi *dpi)
> +{
> + plt_write64(0x1, dpi->rbase + DPI_VDMA_EN);
> + return 0;
> +}
> +
> +int
> +roc_dpi_queue_stop(struct roc_dpi *dpi)
> +{
> + plt_write64(0x0, dpi->rbase + DPI_VDMA_EN);
> + return 0;
> +}
> +
> +int
> +roc_dpi_queue_configure(struct roc_dpi *roc_dpi)
> +{
> + struct plt_pci_device *pci_dev;
> + const struct plt_memzone *dpi_mz;
> + dpi_mbox_msg_t mbox_msg;
> + struct npa_pool_s pool;
> + struct npa_aura_s aura;
> + int rc, count, buflen;
> + uint64_t aura_handle;
> + plt_iova_t iova;
> + char name[32];
> +
> + if (!roc_dpi) {
> + plt_err("roc_dpi is NULL");
> + return -EINVAL;
> + }
> +
> + pci_dev = roc_dpi->pci_dev;
> + memset(&pool, 0, sizeof(struct npa_pool_s));
> + pool.nat_align = 1;
> +
> + memset(&aura, 0, sizeof(aura));
> + rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE,
> + DPI_CMD_QUEUE_BUFS, &aura, &pool);
> + if (rc) {
> + plt_err("Failed to create NPA pool, err %d\n", rc);
> + return rc;
> + }
> +
> + snprintf(name, sizeof(name), "dpimem%d", roc_dpi->vfid);
> + buflen = DPI_CMD_QUEUE_SIZE * DPI_CMD_QUEUE_BUFS;
> + dpi_mz = plt_memzone_reserve_aligned(name, buflen, 0,
> + DPI_CMD_QUEUE_SIZE);
> + if (dpi_mz == NULL) {
> + plt_err("dpi memzone reserve failed");
> + rc = -ENOMEM;
> + goto err1;
> + }
> +
> + roc_dpi->mz = dpi_mz;
> + iova = dpi_mz->iova;
> + for (count = 0; count < DPI_CMD_QUEUE_BUFS; count++) {
> + roc_npa_aura_op_free(aura_handle, 0, iova);
> + iova += DPI_CMD_QUEUE_SIZE;
> + }
> +
> + roc_dpi->chunk_base = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
> + if (!roc_dpi->chunk_base) {
> + plt_err("Failed to alloc buffer from NPA aura");
> + rc = -ENOMEM;
> + goto err2;
> + }
> +
> + roc_dpi->chunk_next = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
> + if (!roc_dpi->chunk_next) {
> + plt_err("Failed to alloc buffer from NPA aura");
> + rc = -ENOMEM;
> + goto err2;
> + }
> +
> + roc_dpi->aura_handle = aura_handle;
> + /* subtract 2 as they have already been alloc'ed above */
> + roc_dpi->pool_size_m1 = (DPI_CMD_QUEUE_SIZE >> 3) - 2;
> +
> + plt_write64(0x0, roc_dpi->rbase + DPI_VDMA_REQQ_CTL);
> + plt_write64(((uint64_t)(roc_dpi->chunk_base) >> 7) << 7,
> + roc_dpi->rbase + DPI_VDMA_SADDR);
> + mbox_msg.u[0] = 0;
> + mbox_msg.u[1] = 0;
> + /* DPI PF driver expects vfid starts from index 0 */
> + mbox_msg.s.vfid = roc_dpi->vfid;
> + mbox_msg.s.cmd = DPI_QUEUE_OPEN;
> + mbox_msg.s.csize = DPI_CMD_QUEUE_SIZE;
> + mbox_msg.s.aura = roc_npa_aura_handle_to_aura(aura_handle);
> + mbox_msg.s.sso_pf_func = idev_sso_pffunc_get();
> + mbox_msg.s.npa_pf_func = idev_npa_pffunc_get();
> +
> + rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
> + sizeof(dpi_mbox_msg_t));
> + if (rc < 0) {
> + plt_err("Failed to send mbox message %d to DPI PF, err %d",
> + mbox_msg.s.cmd, rc);
> + goto err2;
> + }
> +
> + return rc;
> +
> +err2:
> + roc_npa_pool_destroy(aura_handle);
> +err1:
> + plt_memzone_free(dpi_mz);
> + return rc;
> +}
> +
> +int
> +roc_dpi_dev_init(struct roc_dpi *roc_dpi)
> +{
> + struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
> + uint16_t vfid;
> +
> + roc_dpi->rbase = pci_dev->mem_resource[0].addr;
> + vfid = ((pci_dev->addr.devid & 0x1F) << 3) |
> + (pci_dev->addr.function & 0x7);
> + vfid -= 1;
> + roc_dpi->vfid = vfid;
> + plt_spinlock_init(&roc_dpi->chunk_lock);
> +
> + return 0;
> +}
> +
> +int
> +roc_dpi_dev_fini(struct roc_dpi *roc_dpi)
> +{
> + struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
> + dpi_mbox_msg_t mbox_msg;
> + uint64_t reg;
> + int rc;
> +
> + /* Wait for SADDR to become idle */
> + reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
> + while (!(reg & BIT_ULL(63)))
> + reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
> +
> + mbox_msg.u[0] = 0;
> + mbox_msg.u[1] = 0;
> + mbox_msg.s.vfid = roc_dpi->vfid;
> + mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
> +
> + rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
> + sizeof(dpi_mbox_msg_t));
> + if (rc < 0)
> + plt_err("Failed to send mbox message %d to DPI PF, err %d",
> + mbox_msg.s.cmd, rc);
> +
> + roc_npa_pool_destroy(roc_dpi->aura_handle);
> + plt_memzone_free(roc_dpi->mz);
> +
> + return rc;
> +}
> diff --git a/drivers/common/cnxk/roc_dpi.h b/drivers/common/cnxk/roc_dpi.h
> new file mode 100644
> index 0000000000..c2e6d997ea
> --- /dev/null
> +++ b/drivers/common/cnxk/roc_dpi.h
> @@ -0,0 +1,44 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +
> +#ifndef _ROC_DPI_H_
> +#define _ROC_DPI_H_
> +
> +struct roc_dpi_args {
> + uint8_t num_ssegs;
> + uint8_t num_dsegs;
> + uint8_t comp_type;
> + uint8_t direction;
> + uint8_t sdevice;
> + uint8_t ddevice;
> + uint8_t swap;
> + uint8_t use_lock : 1;
> + uint8_t tt : 7;
> + uint16_t func;
> + uint16_t grp;
> + uint32_t tag;
> + uint64_t comp_ptr;
> +};
> +
> +struct roc_dpi {
> + struct plt_pci_device *pci_dev;
> + const struct plt_memzone *mz;
> + uint8_t *rbase;
> + uint16_t vfid;
> + uint16_t pool_size_m1;
> + uint16_t chunk_head;
> + uint64_t *chunk_base;
> + uint64_t *chunk_next;
> + uint64_t aura_handle;
> + plt_spinlock_t chunk_lock;
segregate input parameters for roc_dpi_dev_init() and RoC managed
variables with comments.
> +} __plt_cache_aligned;
> +
> +int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi);
> +int __roc_api roc_dpi_dev_fini(struct roc_dpi *roc_dpi);
> +
> +int __roc_api roc_dpi_queue_configure(struct roc_dpi *dpi);
> +int __roc_api roc_dpi_queue_start(struct roc_dpi *dpi);
> +int __roc_api roc_dpi_queue_stop(struct roc_dpi *dpi);
For future proof and make API looks clean, add quued id.
If there will not be any queue in the future change to
roc_dpi_configure()... etc.
Please change start/stop change to enable/disable.
> +
> +#endif
> diff --git a/drivers/common/cnxk/roc_dpi_priv.h b/drivers/common/cnxk/roc_dpi_priv.h
> new file mode 100644
> index 0000000000..92953fbcfc
> --- /dev/null
> +++ b/drivers/common/cnxk/roc_dpi_priv.h
> @@ -0,0 +1,40 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +
> +#ifndef _ROC_DPI_PRIV_H_
> +#define _ROC_DPI_PRIV_H_
> +
> +#define DPI_MAX_VFS 8
> +
> +/* DPI PF DBDF information macros */
> +#define DPI_PF_DBDF_DEVICE 0
> +#define DPI_PF_DBDF_FUNCTION 0
> +
> +#define DPI_QUEUE_OPEN 0x1
> +#define DPI_QUEUE_CLOSE 0x2
> +#define DPI_REG_DUMP 0x3
> +#define DPI_GET_REG_CFG 0x4
> +
> +#define DPI_CMD_QUEUE_SIZE 4096
> +#define DPI_CMD_QUEUE_BUFS 1024
> +
> +typedef union dpi_mbox_msg_t {
> + uint64_t u[2];
> + struct dpi_mbox_message_s {
> + /* VF ID to configure */
> + uint64_t vfid : 4;
> + /* Command code */
> + uint64_t cmd : 4;
> + /* Command buffer size in 8-byte words */
> + uint64_t csize : 14;
> + /* aura of the command buffer */
> + uint64_t aura : 20;
> + /* SSO PF function */
> + uint64_t sso_pf_func : 16;
> + /* NPA PF function */
> + uint64_t npa_pf_func : 16;
> + } s;
> +} dpi_mbox_msg_t;
> +
> +#endif
> diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
> index 5da23fe5f8..61d4781209 100644
> --- a/drivers/common/cnxk/roc_platform.h
> +++ b/drivers/common/cnxk/roc_platform.h
> @@ -69,6 +69,7 @@
> #define __roc_api __rte_internal
> #define plt_iova_t rte_iova_t
>
> +#define plt_pci_addr rte_pci_addr
> #define plt_pci_device rte_pci_device
> #define plt_pci_read_config rte_pci_read_config
> #define plt_pci_find_ext_capability rte_pci_find_ext_capability
> diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
> index f72bbd568f..782b90cf8d 100644
> --- a/drivers/common/cnxk/roc_priv.h
> +++ b/drivers/common/cnxk/roc_priv.h
> @@ -41,4 +41,7 @@
> /* NIX Inline dev */
> #include "roc_nix_inl_priv.h"
>
> +/* DPI */
> +#include "roc_dpi_priv.h"
> +
> #endif /* _ROC_PRIV_H_ */
> diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
> index 8d4d42f476..3edc42cfd6 100644
> --- a/drivers/common/cnxk/version.map
> +++ b/drivers/common/cnxk/version.map
> @@ -68,6 +68,11 @@ INTERNAL {
> roc_cpt_lmtline_init;
> roc_cpt_parse_hdr_dump;
> roc_cpt_rxc_time_cfg;
> + roc_dpi_dev_init;
> + roc_dpi_dev_fini;
> + roc_dpi_queue_configure;
> + roc_dpi_queue_start;
> + roc_dpi_queue_stop;
> roc_error_msg_get;
> roc_hash_sha1_gen;
> roc_hash_sha256_gen;
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH 2/4] dma/cnxk: create and initialize dmadev on pci probe
2021-10-26 4:12 ` [dpdk-dev] [PATCH 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
@ 2021-10-26 8:36 ` Jerin Jacob
2021-10-26 21:05 ` Radha Mohan
0 siblings, 1 reply; 32+ messages in thread
From: Jerin Jacob @ 2021-10-26 8:36 UTC (permalink / raw)
To: Radha Mohan Chintakuntla
Cc: Thomas Monjalon, fengchengwen, Nithin Dabilpuram, Kiran Kumar K,
Sunil Kumar Kori, Satha Koteswara Rao Kottidi, Jerin Jacob,
Satananda Burla, dpdk-dev
On Tue, Oct 26, 2021 at 9:43 AM Radha Mohan Chintakuntla
<radhac@marvell.com> wrote:
>
> This patch creates and initializes a dmadev device on pci probe.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
> MAINTAINERS | 7 +-
> doc/guides/dmadevs/cnxk.rst | 53 +++++++++++++++
> doc/guides/dmadevs/index.rst | 1 +
> drivers/dma/cnxk/cnxk_dmadev.c | 119 +++++++++++++++++++++++++++++++++
> drivers/dma/cnxk/cnxk_dmadev.h | 11 +++
> drivers/dma/cnxk/meson.build | 7 ++
> drivers/dma/meson.build | 1 +
> 7 files changed, 198 insertions(+), 1 deletion(-)
> create mode 100644 doc/guides/dmadevs/cnxk.rst
> create mode 100644 drivers/dma/cnxk/cnxk_dmadev.c
> create mode 100644 drivers/dma/cnxk/cnxk_dmadev.h
> create mode 100644 drivers/dma/cnxk/meson.build
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index be2c9b6815..cdc2d98a6b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1186,7 +1186,6 @@ F: drivers/compress/zlib/
> F: doc/guides/compressdevs/zlib.rst
> F: doc/guides/compressdevs/features/zlib.ini
>
> -
Unwanted line deletion.
> DMAdev Drivers
> --------------
>
> @@ -1202,6 +1201,12 @@ M: Conor Walsh <conor.walsh@intel.com>
> F: drivers/dma/ioat/
> F: doc/guides/dmadevs/ioat.rst
>
> +Marvell CNXK DPI DMA
> +M: Radha Mohan Chintakuntla <radhac@marvell.com>
> +M: Veerasenareddy Burru <vburru@marvell.com>
> +F: drivers/dma/cnxk/
> +F: doc/guides/dmadevs/cnxk.rst
> +
>
> RegEx Drivers
> -------------
> diff --git a/doc/guides/dmadevs/cnxk.rst b/doc/guides/dmadevs/cnxk.rst
> new file mode 100644
> index 0000000000..8ae7c1f8cd
> --- /dev/null
> +++ b/doc/guides/dmadevs/cnxk.rst
> @@ -0,0 +1,53 @@
> +.. SPDX-License-Identifier: BSD-3-Clause
> + Copyright(c) 2021 Marvell International Ltd.
> +
> +.. include:: <isonum.txt>
> +
Please link top-level doc/guides/platform/cnxk.rst documentation file
to this file.
> +CNXK DMA Device Driver
> +======================
> +
> +The ``cnxk`` dmadev driver provides a poll-mode driver (PMD) for Marvell DPI DMA
> +Hardware Accelerator block found in OCTEONTX2 and OCTEONTX3 family of SoCs. Each
> +DMA queue is exposed as a VF function when SRIOV is enabled.
> +
> +The block supports following modes of DMA transfers
> +
> +#. Internal - DMA within SoC DRAM to DRAM
> +
> +#. Inbound - Host DRAM to SoC DRAM when SoC is in PCIe Endpoint
> +
> +#. Outbound - SoC DRAM to Host DRAM when SoC is in PCIe Endpoint
> +
> +Device Setup
> +-------------
> +The ``dpdk-devbind.py`` script, included with DPDK, can be used to show the
> +presence of supported hardware. Running ``dpdk-devbind.py --status-dev dma``
> +will show all the CNXK DMA devices.
> +
> +Devices using VFIO drivers
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +The HW devices to be used will need to be bound to a user-space IO driver for use.
> +The ``dpdk-devbind.py`` script can be used to view the state of the devices
> +and to bind them to a suitable DPDK-supported driver, such as ``vfio-pci``.
> +For example::
> +
> + $ dpdk-devbind.py -b vfio-pci 0000:05:00.1
> +
> +Device Probing and Initialization
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +To use the devices from an application, the dmadev API can be used.
> +CNXK DMA device configuration requirements:
> +
> +* Only one ``vchan`` is supported per device.
> +* CNXK DMA devices do not support silent mode.
> +
> +Once configured, the device can then be made ready for use by calling the
> + ``rte_dma_start()`` API.
> +
> +Performing Data Copies
> +~~~~~~~~~~~~~~~~~~~~~~~
> +
> +Refer to the :ref:`Enqueue / Dequeue APIs <dmadev_enqueue_dequeue>` section of the dmadev library
> +documentation for details on operation enqueue and submission API usage.
> diff --git a/doc/guides/dmadevs/index.rst b/doc/guides/dmadevs/index.rst
> index 20476039a5..227fa00c68 100644
> --- a/doc/guides/dmadevs/index.rst
> +++ b/doc/guides/dmadevs/index.rst
> @@ -11,5 +11,6 @@ an application through DMA API.
> :maxdepth: 2
> :numbered:
>
> + cnxk
> idxd
> ioat
> diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
> new file mode 100644
> index 0000000000..620766743d
> --- /dev/null
> +++ b/drivers/dma/cnxk/cnxk_dmadev.c
> @@ -0,0 +1,119 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright (C) 2021 Marvell International Ltd.
> + */
> +
> +#include <string.h>
> +#include <unistd.h>
> +
> +#include <rte_bus.h>
> +#include <rte_bus_pci.h>
> +#include <rte_common.h>
> +#include <rte_eal.h>
> +#include <rte_lcore.h>
> +#include <rte_mempool.h>
> +#include <rte_pci.h>
> +#include <rte_dmadev.h>
> +#include <rte_dmadev_pmd.h>
> +
> +#include <roc_api.h>
> +#include <cnxk_dmadev.h>
> +
> +static int
> +cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
> + struct rte_pci_device *pci_dev)
> +{
> + struct cnxk_dpi_vf_s *dpivf = NULL;
> + char name[RTE_DEV_NAME_MAX_LEN];
> + struct rte_dma_dev *dmadev;
> + struct roc_dpi *rdpi = NULL;
> + int rc;
> +
> + if (!pci_dev->mem_resource[0].addr)
> + return -ENODEV;
> +
> + rc = roc_plt_init();
> + if (rc) {
> + plt_err("Failed to initialize platform model, rc=%d", rc);
> + return rc;
> + }
> + memset(name, 0, sizeof(name));
> + rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
> +
> + dmadev = rte_dma_pmd_allocate(name, pci_dev->device.numa_node,
> + sizeof(*dpivf));
> + if (dmadev == NULL) {
> + plt_err("dma device allocation failed for %s", name);
> + return -ENOMEM;
> + }
> +
> + dpivf = dmadev->data->dev_private;
> +
> + dmadev->device = &pci_dev->device;
> + dmadev->fp_obj->dev_private = dpivf;
> +
> + rdpi = &dpivf->rdpi;
> +
> + rdpi->pci_dev = pci_dev;
> + rc = roc_dpi_dev_init(rdpi);
> + if (rc < 0)
> + goto err_out_free;
> +
> + return 0;
> +
> +err_out_free:
> + if (dmadev)
> + rte_dma_pmd_release(name);
> +
> + return rc;
> +}
> +
> +static int
> +cnxk_dmadev_remove(struct rte_pci_device *pci_dev)
> +{
> + char name[RTE_DEV_NAME_MAX_LEN];
> + struct rte_dma_dev *dmadev;
> + struct cnxk_dpi_vf_s *dpivf;
> + int dev_id;
> +
> + memset(name, 0, sizeof(name));
> + rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
> +
> + dev_id = rte_dma_get_dev_id_by_name(name);
> + if (dev_id < 0) {
> + plt_err("Invalid device ID");
> + return -EINVAL;
> + }
> +
> + dmadev = &rte_dma_devices[dev_id];
> + if (!dmadev) {
> + plt_err("dmadev with name %s not found\n", name);
> + return -ENODEV;
> + }
> +
> + dpivf = dmadev->fp_obj->dev_private;
> + roc_dpi_queue_stop(&dpivf->rdpi);
> + roc_dpi_dev_fini(&dpivf->rdpi);
> +
> + return rte_dma_pmd_release(name);
> +}
> +
> +static const struct rte_pci_id cnxk_dma_pci_map[] = {
> + {
> + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
> + PCI_DEVID_CNXK_DPI_VF)
> + },
> + {
> + .vendor_id = 0,
> + },
> +};
> +
> +static struct rte_pci_driver cnxk_dmadev = {
> + .id_table = cnxk_dma_pci_map,
> + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
> + .probe = cnxk_dmadev_probe,
> + .remove = cnxk_dmadev_remove,
> +};
> +
> +RTE_PMD_REGISTER_PCI(cnxk_dmadev_pci_driver, cnxk_dmadev);
> +RTE_PMD_REGISTER_PCI_TABLE(cnxk_dmadev_pci_driver, cnxk_dma_pci_map);
> +RTE_PMD_REGISTER_KMOD_DEP(cnxk_dmadev_pci_driver, "vfio-pci");
> diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
> new file mode 100644
> index 0000000000..9e0bb7b2ce
> --- /dev/null
> +++ b/drivers/dma/cnxk/cnxk_dmadev.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell International Ltd.
> + */
> +#ifndef _CNXK_DMADEV_H_
> +#define _CNXK_DMADEV_H_
> +
> +struct cnxk_dpi_vf_s {
> + struct roc_dpi rdpi;
> +};
> +
> +#endif
> diff --git a/drivers/dma/cnxk/meson.build b/drivers/dma/cnxk/meson.build
> new file mode 100644
> index 0000000000..9489d6e6dc
> --- /dev/null
> +++ b/drivers/dma/cnxk/meson.build
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(C) 2021 Marvell International Ltd.
> +#
> +
> +deps += ['bus_pci', 'common_cnxk', 'dmadev']
> +sources = files('cnxk_dmadev.c')
> +headers = files('cnxk_dmadev.h')
> diff --git a/drivers/dma/meson.build b/drivers/dma/meson.build
> index a69418ce9b..c562c8b429 100644
> --- a/drivers/dma/meson.build
> +++ b/drivers/dma/meson.build
> @@ -2,6 +2,7 @@
> # Copyright 2021 HiSilicon Limited
>
> drivers = [
> + 'cnxk',
> 'idxd',
> 'ioat',
> 'skeleton',
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations
2021-10-26 4:12 ` [dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
@ 2021-10-26 8:41 ` Jerin Jacob
2021-10-28 18:18 ` Radha Mohan
0 siblings, 1 reply; 32+ messages in thread
From: Jerin Jacob @ 2021-10-26 8:41 UTC (permalink / raw)
To: Radha Mohan Chintakuntla
Cc: Thomas Monjalon, fengchengwen, Nithin Dabilpuram, Kiran Kumar K,
Sunil Kumar Kori, Satha Koteswara Rao Kottidi, Jerin Jacob,
Satananda Burla, dpdk-dev
On Tue, Oct 26, 2021 at 9:43 AM Radha Mohan Chintakuntla
<radhac@marvell.com> wrote:
>
> Add functions for the dmadev vchan setup and DMA operations.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
> drivers/dma/cnxk/cnxk_dmadev.c | 322 +++++++++++++++++++++++++++++++++
> drivers/dma/cnxk/cnxk_dmadev.h | 53 ++++++
> drivers/dma/cnxk/version.map | 3 +
> 3 files changed, 378 insertions(+)
> create mode 100644 drivers/dma/cnxk/version.map
>
> diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
> index 620766743d..8434579aa2 100644
> --- a/drivers/dma/cnxk/cnxk_dmadev.c
> +++ b/drivers/dma/cnxk/cnxk_dmadev.c
> @@ -18,6 +18,322 @@
> #include <roc_api.h>
> #include <cnxk_dmadev.h>
>
> +static int
> +cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
> + struct rte_dma_info *dev_info, uint32_t size)
> +{
> + RTE_SET_USED(dev);
> + RTE_SET_USED(size);
> +
> + dev_info->max_vchans = 1;
> + dev_info->nb_vchans = 1;
> + dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
> + RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
> + RTE_DMA_CAPA_OPS_COPY;
> + dev_info->max_desc = DPI_MAX_DESC;
> + dev_info->min_desc = 1;
> + dev_info->max_sges = DPI_MAX_POINTER;
> +
> + return 0;
> +}
> +
> +static int
> +cnxk_dmadev_configure(struct rte_dma_dev *dev,
> + const struct rte_dma_conf *conf, uint32_t conf_sz)
> +{
> + struct cnxk_dpi_vf_s *dpivf = NULL;
> + int rc = 0;
> +
> + RTE_SET_USED(conf);
> + RTE_SET_USED(conf);
> + RTE_SET_USED(conf_sz);
> + RTE_SET_USED(conf_sz);
> + dpivf = dev->fp_obj->dev_private;
> + rc = roc_dpi_queue_configure(&dpivf->rdpi);
> + if (rc < 0)
> + plt_err("DMA queue configure failed err = %d", rc);
> +
> + return rc;
> +}
> +
> +static int
> +cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
> + const struct rte_dma_vchan_conf *conf,
> + uint32_t conf_sz)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> + struct cnxk_dpi_compl_s *comp_data;
> + int i;
> +
> + RTE_SET_USED(vchan);
> + RTE_SET_USED(conf_sz);
> +
> + switch (conf->direction) {
> + case RTE_DMA_DIR_DEV_TO_MEM:
> + dpivf->conf.direction = DPI_XTYPE_INBOUND;
> + dpivf->conf.src_port = conf->src_port.pcie.coreid;
> + dpivf->conf.dst_port = 0;
> + break;
> + case RTE_DMA_DIR_MEM_TO_DEV:
> + dpivf->conf.direction = DPI_XTYPE_OUTBOUND;
> + dpivf->conf.src_port = 0;
> + dpivf->conf.dst_port = conf->dst_port.pcie.coreid;
> + break;
> + case RTE_DMA_DIR_MEM_TO_MEM:
> + dpivf->conf.direction = DPI_XTYPE_INTERNAL_ONLY;
> + dpivf->conf.src_port = 0;
> + dpivf->conf.dst_port = 0;
> + break;
> + case RTE_DMA_DIR_DEV_TO_DEV:
> + dpivf->conf.direction = DPI_XTYPE_EXTERNAL_ONLY;
> + dpivf->conf.src_port = conf->src_port.pcie.coreid;
> + dpivf->conf.dst_port = conf->src_port.pcie.coreid;
> + };
> +
> + for (i = 0; i < conf->nb_desc; i++) {
> + comp_data = rte_zmalloc(NULL, sizeof(*comp_data), 0);
> + dpivf->conf.c_desc.compl_ptr[i] = comp_data;
> + };
> + dpivf->conf.c_desc.max_cnt = DPI_MAX_DESC;
> + dpivf->conf.c_desc.head = 0;
> + dpivf->conf.c_desc.tail = 0;
> +
> + return 0;
> +}
> +
> +static int
> +cnxk_dmadev_start(struct rte_dma_dev *dev)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> +
> + roc_dpi_queue_start(&dpivf->rdpi);
> +
> + return 0;
> +}
> +
> +static int
> +cnxk_dmadev_stop(struct rte_dma_dev *dev)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> +
> + roc_dpi_queue_stop(&dpivf->rdpi);
> +
> + return 0;
> +}
> +
> +static int
> +cnxk_dmadev_close(struct rte_dma_dev *dev)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> +
> + roc_dpi_queue_stop(&dpivf->rdpi);
> + roc_dpi_dev_fini(&dpivf->rdpi);
> +
> + return 0;
> +}
> +
> +static inline int
> +__dpi_queue_write(struct roc_dpi *dpi, uint64_t *cmds, int cmd_count)
> +{
> + uint64_t *ptr = dpi->chunk_base;
> +
> + if ((cmd_count < DPI_MIN_CMD_SIZE) || (cmd_count > DPI_MAX_CMD_SIZE) ||
> + cmds == NULL)
> + return -EINVAL;
> +
> + /*
> + * Normally there is plenty of room in the current buffer for the
> + * command
> + */
> + if (dpi->chunk_head + cmd_count < dpi->pool_size_m1) {
> + ptr += dpi->chunk_head;
> + dpi->chunk_head += cmd_count;
> + while (cmd_count--)
> + *ptr++ = *cmds++;
> + } else {
> + int count;
> + uint64_t *new_buff = dpi->chunk_next;
> +
> + dpi->chunk_next =
> + (void *)roc_npa_aura_op_alloc(dpi->aura_handle, 0);
> + if (!dpi->chunk_next) {
> + plt_err("Failed to alloc next buffer from NPA");
> + return -ENOMEM;
> + }
> +
> + /*
> + * Figure out how many cmd words will fit in this buffer.
> + * One location will be needed for the next buffer pointer.
> + */
> + count = dpi->pool_size_m1 - dpi->chunk_head;
> + ptr += dpi->chunk_head;
> + cmd_count -= count;
> + while (count--)
> + *ptr++ = *cmds++;
> +
> + /*
> + * chunk next ptr is 2 DWORDS
> + * second DWORD is reserved.
> + */
> + *ptr++ = (uint64_t)new_buff;
> + *ptr = 0;
> +
> + /*
> + * The current buffer is full and has a link to the next
> + * buffers. Time to write the rest of the commands into the new
> + * buffer.
> + */
> + dpi->chunk_base = new_buff;
> + dpi->chunk_head = cmd_count;
> + ptr = new_buff;
> + while (cmd_count--)
> + *ptr++ = *cmds++;
> +
> + /* queue index may be greater than pool size */
> + if (dpi->chunk_head >= dpi->pool_size_m1) {
> + new_buff = dpi->chunk_next;
> + dpi->chunk_next =
> + (void *)roc_npa_aura_op_alloc(dpi->aura_handle,
> + 0);
> + if (!dpi->chunk_next) {
> + plt_err("Failed to alloc next buffer from NPA");
> + return -ENOMEM;
> + }
> + /* Write next buffer address */
> + *ptr = (uint64_t)new_buff;
> + dpi->chunk_base = new_buff;
> + dpi->chunk_head = 0;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int
> +cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
> + rte_iova_t dst, uint32_t length, uint64_t flags)
> +{
> + uint64_t cmd[DPI_MAX_CMD_SIZE] = {0};
> + union dpi_instr_hdr_s *header = (union dpi_instr_hdr_s *)&cmd[0];
> + rte_iova_t fptr, lptr;
> + struct cnxk_dpi_vf_s *dpivf = dev_private;
> + struct cnxk_dpi_compl_s *comp_ptr;
> + int num_words = 0;
> + int rc;
> +
> + RTE_SET_USED(vchan);
> +
> + header->s.xtype = dpivf->conf.direction;
> + header->s.pt = DPI_HDR_PT_ZBW_CA;
> + comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
> + comp_ptr->cdata = DPI_REQ_CDATA;
> + header->s.ptr = (uint64_t)comp_ptr;
> + STRM_INC(dpivf->conf.c_desc);
> +
> + /* pvfe should be set for inbound and outbound only */
> + if (header->s.xtype <= 1)
> + header->s.pvfe = 1;
> + num_words += 4;
> +
> + header->s.nfst = 1;
> + header->s.nlst = 1;
Including filling zeros in cmd and the rest of the filling can be
moved to slow path..
Please change the logic to populate the static items based on
configure/channel setup
in slowpath and update only per transfer-specific items to have better
performance.
> + /*
> + * For inbound case, src pointers are last pointers.
> + * For all other cases, src pointers are first pointers.
> + */
> + if (header->s.xtype == DPI_XTYPE_INBOUND) {
> + fptr = dst;
> + lptr = src;
> + header->s.fport = dpivf->conf.dst_port & 0x3;
> + header->s.lport = dpivf->conf.src_port & 0x3;
> + } else {
> + fptr = src;
> + lptr = dst;
> + header->s.fport = dpivf->conf.src_port & 0x3;
> + header->s.lport = dpivf->conf.dst_port & 0x3;
> + }
> +
> + cmd[num_words++] = length;
> + cmd[num_words++] = fptr;
> + cmd[num_words++] = length;
> + cmd[num_words++] = lptr;
> +
> + rc = __dpi_queue_write(&dpivf->rdpi, cmd, num_words);
> + if (!rc) {
> + if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
> + rte_wmb();
> + plt_write64(num_words,
> + dpivf->rdpi.rbase + DPI_VDMA_DBELL);
> + }
> + dpivf->num_words = num_words;
> + }
> +
> + return rc;
> +}
> +
> +static uint16_t
> +cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
> + uint16_t *last_idx, bool *has_error)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev_private;
> + int cnt;
> +
> + RTE_SET_USED(vchan);
> + RTE_SET_USED(last_idx);
> + RTE_SET_USED(has_error);
> + for (cnt = 0; cnt < nb_cpls; cnt++) {
> + struct cnxk_dpi_compl_s *comp_ptr =
> + dpivf->conf.c_desc.compl_ptr[cnt];
> +
> + if (comp_ptr->cdata)
> + break;
> + }
> +
> + dpivf->conf.c_desc.tail = cnt;
> +
> + return cnt;
> +}
> +
> +static uint16_t
> +cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan,
> + const uint16_t nb_cpls, uint16_t *last_idx,
> + enum rte_dma_status_code *status)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev_private;
> + int cnt;
> +
> + RTE_SET_USED(vchan);
> + RTE_SET_USED(last_idx);
> + for (cnt = 0; cnt < nb_cpls; cnt++) {
> + struct cnxk_dpi_compl_s *comp_ptr =
> + dpivf->conf.c_desc.compl_ptr[cnt];
> + status[cnt] = comp_ptr->cdata;
> + }
> +
> + dpivf->conf.c_desc.tail = 0;
> + return cnt;
> +}
> +
> +static int
> +cnxk_dmadev_submit(void *dev_private, uint16_t vchan __rte_unused)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev_private;
> +
> + rte_wmb();
> + plt_write64(dpivf->num_words, dpivf->rdpi.rbase + DPI_VDMA_DBELL);
> +
> + return 0;
> +}
> +
> +static const struct rte_dma_dev_ops cnxk_dmadev_ops = {
> + .dev_info_get = cnxk_dmadev_info_get,
> + .dev_configure = cnxk_dmadev_configure,
> + .dev_start = cnxk_dmadev_start,
> + .dev_stop = cnxk_dmadev_stop,
> + .vchan_setup = cnxk_dmadev_vchan_setup,
> + .dev_close = cnxk_dmadev_close,
> +};
> +
> static int
> cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
> struct rte_pci_device *pci_dev)
> @@ -50,6 +366,12 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
>
> dmadev->device = &pci_dev->device;
> dmadev->fp_obj->dev_private = dpivf;
> + dmadev->dev_ops = &cnxk_dmadev_ops;
> +
> + dmadev->fp_obj->copy = cnxk_dmadev_copy;
> + dmadev->fp_obj->submit = cnxk_dmadev_submit;
> + dmadev->fp_obj->completed = cnxk_dmadev_completed;
> + dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
>
> rdpi = &dpivf->rdpi;
>
> diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
> index 9e0bb7b2ce..ce301a5945 100644
> --- a/drivers/dma/cnxk/cnxk_dmadev.h
> +++ b/drivers/dma/cnxk/cnxk_dmadev.h
> @@ -4,8 +4,61 @@
> #ifndef _CNXK_DMADEV_H_
> #define _CNXK_DMADEV_H_
>
> +#define DPI_MAX_POINTER 15
> +#define DPI_QUEUE_STOP 0x0
> +#define DPI_QUEUE_START 0x1
> +#define STRM_INC(s) ((s).tail = ((s).tail + 1) % (s).max_cnt)
> +#define DPI_MAX_DESC DPI_MAX_POINTER
> +
> +/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */
> +#define DPI_XTYPE_OUTBOUND (0)
> +#define DPI_XTYPE_INBOUND (1)
> +#define DPI_XTYPE_INTERNAL_ONLY (2)
> +#define DPI_XTYPE_EXTERNAL_ONLY (3)
> +#define DPI_XTYPE_MASK 0x3
> +#define DPI_HDR_PT_ZBW_CA 0x0
> +#define DPI_HDR_PT_ZBW_NC 0x1
> +#define DPI_HDR_PT_WQP 0x2
> +#define DPI_HDR_PT_WQP_NOSTATUS 0x0
> +#define DPI_HDR_PT_WQP_STATUSCA 0x1
> +#define DPI_HDR_PT_WQP_STATUSNC 0x3
> +#define DPI_HDR_PT_CNT 0x3
> +#define DPI_HDR_PT_MASK 0x3
> +#define DPI_W0_TT_MASK 0x3
> +#define DPI_W0_GRP_MASK 0x3FF
> +
> +/* Set Completion data to 0xFF when request submitted,
> + * upon successful request completion engine reset to completion status
> + */
> +#define DPI_REQ_CDATA 0xFF
> +
> +#define DPI_MIN_CMD_SIZE 8
> +#define DPI_MAX_CMD_SIZE 64
> +
> +struct cnxk_dpi_compl_s {
> + uint64_t cdata;
> + void *cb_data;
> +};
> +
> +struct cnxk_dpi_cdesc_data_s {
> + struct cnxk_dpi_compl_s *compl_ptr[DPI_MAX_DESC];
> + uint16_t max_cnt;
> + uint16_t head;
> + uint16_t tail;
> +};
> +
> +struct cnxk_dpi_queue_conf {
> + uint8_t direction;
> + uint8_t src_port;
> + uint8_t dst_port;
> + uint64_t comp_ptr;
> + struct cnxk_dpi_cdesc_data_s c_desc;
> +};
> +
> struct cnxk_dpi_vf_s {
> struct roc_dpi rdpi;
> + struct cnxk_dpi_queue_conf conf;
> + uint32_t num_words;
> };
>
> #endif
> diff --git a/drivers/dma/cnxk/version.map b/drivers/dma/cnxk/version.map
> new file mode 100644
> index 0000000000..4a76d1d52d
> --- /dev/null
> +++ b/drivers/dma/cnxk/version.map
> @@ -0,0 +1,3 @@
> +DPDK_21 {
> + local: *;
> +};
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH 4/4] dma/cnxk: add copy_sg function
2021-10-26 4:13 ` [dpdk-dev] [PATCH 4/4] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
@ 2021-10-26 8:42 ` Jerin Jacob
0 siblings, 0 replies; 32+ messages in thread
From: Jerin Jacob @ 2021-10-26 8:42 UTC (permalink / raw)
To: Radha Mohan Chintakuntla
Cc: Thomas Monjalon, fengchengwen, Nithin Dabilpuram, Kiran Kumar K,
Sunil Kumar Kori, Satha Koteswara Rao Kottidi, Jerin Jacob,
Satananda Burla, dpdk-dev
On Tue, Oct 26, 2021 at 9:43 AM Radha Mohan Chintakuntla
<radhac@marvell.com> wrote:
>
> Add the copy_sg function that will do the multiple DMA transfers of
> different sizes and different source/destination as well.
> +static int
> +cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan,
> + const struct rte_dma_sge *src,
> + const struct rte_dma_sge *dst,
> + uint16_t nb_src, uint16_t nb_dst, uint64_t flags)
> +{
> + uint64_t cmd[DPI_MAX_CMD_SIZE] = {0};
> + union dpi_instr_hdr_s *header = (union dpi_instr_hdr_s *)&cmd[0];
> + struct cnxk_dpi_vf_s *dpivf = dev_private;
> + const struct rte_dma_sge *fptr, *lptr;
> + struct cnxk_dpi_compl_s *comp_ptr;
> + int num_words = 0;
> + int i, rc;
> +
> + RTE_SET_USED(vchan);
> +
> + header->s.xtype = dpivf->conf.direction;
> + header->s.pt = DPI_HDR_PT_ZBW_CA;
> + header->s.grp = 0;
> + header->s.tag = 0;
> + header->s.tt = 0;
> + header->s.func = 0;
> + comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
> + comp_ptr->cdata = DPI_REQ_CDATA;
> + header->s.ptr = (uint64_t)comp_ptr;
> + STRM_INC(dpivf->conf.c_desc);
> +
> + /* pvfs should be set for inbound and outbound only */
> + if (header->s.xtype <= 1)
> + header->s.pvfe = 1;
> + num_words += 4;
# Please change the logic to populate the static items based on
configure/channel setup
in slowpath and update only per transfer-specific items to have better
performance.
# Also make sure test application and example application passes this
patch series.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support
2021-10-26 8:33 ` [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support Jerin Jacob
@ 2021-10-26 15:57 ` Radha Mohan
0 siblings, 0 replies; 32+ messages in thread
From: Radha Mohan @ 2021-10-26 15:57 UTC (permalink / raw)
To: Jerin Jacob
Cc: Radha Mohan Chintakuntla, Thomas Monjalon, fengchengwen,
Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Koteswara Rao Kottidi, Jerin Jacob, Satananda Burla,
dpdk-dev
On Tue, Oct 26, 2021 at 1:34 AM Jerin Jacob <jerinjacobk@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 9:43 AM Radha Mohan Chintakuntla
> <radhac@marvell.com> wrote:
> >
> > Add base support as ROC(Rest of Chip) API which will be used by PMD
> > dmadev driver.
> >
> > This patch adds routines to init, fini, configure the DPI DMA device
> > found in Marvell's CN9k or CN10k SoC familes.
>
> families
ack.
>
> >
> > Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> > ---
> > drivers/common/cnxk/hw/dpi.h | 136 ++++++++++++++++++++
> > drivers/common/cnxk/meson.build | 1 +
> > drivers/common/cnxk/roc_api.h | 4 +
> > drivers/common/cnxk/roc_dpi.c | 193 +++++++++++++++++++++++++++++
> > drivers/common/cnxk/roc_dpi.h | 44 +++++++
> > drivers/common/cnxk/roc_dpi_priv.h | 40 ++++++
> > drivers/common/cnxk/roc_platform.h | 1 +
> > drivers/common/cnxk/roc_priv.h | 3 +
> > drivers/common/cnxk/version.map | 5 +
> > 9 files changed, 427 insertions(+)
> > create mode 100644 drivers/common/cnxk/hw/dpi.h
> > create mode 100644 drivers/common/cnxk/roc_dpi.c
> > create mode 100644 drivers/common/cnxk/roc_dpi.h
> > create mode 100644 drivers/common/cnxk/roc_dpi_priv.h
> >
> > diff --git a/drivers/common/cnxk/hw/dpi.h b/drivers/common/cnxk/hw/dpi.h
> > new file mode 100644
> > index 0000000000..aa1e66aa11
> > --- /dev/null
> > +++ b/drivers/common/cnxk/hw/dpi.h
> > @@ -0,0 +1,136 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(C) 2021 Marvell.
> > + */
> > +/**
> > + * DPI device HW definitions.
> > + */
> > +#ifndef __DEV_DPI_HW_H__
> > +#define __DEV_DPI_HW_H__
> > +
> > +#include <stdint.h>
> > +
> > +/** @cond __INTERNAL_DOCUMENTATION__ */
>
> This is not required.
>
> > +
> > +/* DPI VF register offsets from VF_BAR0 */
> > +#define DPI_VDMA_EN (0x0)
> > +#define DPI_VDMA_REQQ_CTL (0x8)
> > +#define DPI_VDMA_DBELL (0x10)
> > +#define DPI_VDMA_SADDR (0x18)
> > +#define DPI_VDMA_COUNTS (0x20)
> > +#define DPI_VDMA_NADDR (0x28)
> > +#define DPI_VDMA_IWBUSY (0x30)
> > +#define DPI_VDMA_CNT (0x38)
> > +#define DPI_VF_INT (0x100)
> > +#define DPI_VF_INT_W1S (0x108)
> > +#define DPI_VF_INT_ENA_W1C (0x110)
> > +#define DPI_VF_INT_ENA_W1S (0x118)
> > +
> > +/**
> > + * Enumeration dpi_hdr_xtype_e
> > + *
> > + * DPI Transfer Type Enumeration
> > + * Enumerates the pointer type in DPI_DMA_INSTR_HDR_S[XTYPE].
> > + */
> > +#define DPI_XTYPE_OUTBOUND (0)
> > +#define DPI_XTYPE_INBOUND (1)
> > +#define DPI_XTYPE_INTERNAL_ONLY (2)
> > +#define DPI_XTYPE_EXTERNAL_ONLY (3)
> > +#define DPI_HDR_XTYPE_MASK 0x3
> > +#define DPI_HDR_PT_MASK 0x3
> > +#define DPI_HDR_TT_MASK 0x3
> > +#define DPI_HDR_GRP_MASK 0x3FF
> > +#define DPI_HDR_FUNC_MASK 0xFFFF
> > +
> > +/* Big endian data bit position in DMA local pointer */
> > +#define DPI_LPTR_BED_BIT_POS (60)
> > +
> > +#define DPI_MIN_CMD_SIZE 8
> > +#define DPI_MAX_CMD_SIZE 64
> > +
> > +/**
> > + * Structure dpi_instr_hdr_s for CN9K
> > + *
> > + * DPI DMA Instruction Header Format
> > + */
> > +union dpi_instr_hdr_s {
> > + uint64_t u[4];
> > + struct dpi_dma_instr_hdr_s_s {
> > + uint64_t tag : 32;
> > + uint64_t tt : 2;
> > + uint64_t grp : 10;
> > + uint64_t reserved_44_47 : 4;
> > + uint64_t nfst : 4;
> > + uint64_t reserved_52_53 : 2;
> > + uint64_t nlst : 4;
> > + uint64_t reserved_58_63 : 6;
> > + /* Word 0 - End */
> > + uint64_t aura : 20;
> > + uint64_t func : 16;
> > + uint64_t pt : 2;
> > + uint64_t reserved_102 : 1;
> > + uint64_t pvfe : 1;
> > + uint64_t fl : 1;
> > + uint64_t ii : 1;
> > + uint64_t fi : 1;
> > + uint64_t ca : 1;
> > + uint64_t csel : 1;
> > + uint64_t reserved_109_111 : 3;
> > + uint64_t xtype : 2;
> > + uint64_t reserved_114_119 : 6;
> > + uint64_t fport : 2;
> > + uint64_t reserved_122_123 : 2;
> > + uint64_t lport : 2;
> > + uint64_t reserved_126_127 : 2;
> > + /* Word 1 - End */
> > + uint64_t ptr : 64;
> > + /* Word 2 - End */
> > + uint64_t reserved_192_255 : 64;
> > + /* Word 3 - End */
> > + } s;
> > +};
> > +
> > +/**
> > + * Structure dpi_cn10k_instr_hdr_s for CN10K
> > + *
> > + * DPI DMA Instruction Header Format
> > + */
> > +union dpi_cn10k_instr_hdr_s {
> > + uint64_t u[4];
> > + struct dpi_cn10k_dma_instr_hdr_s_s {
> > + uint64_t nfst : 4;
> > + uint64_t reserved_4_5 : 2;
> > + uint64_t nlst : 4;
> > + uint64_t reserved_10_11 : 2;
> > + uint64_t pvfe : 1;
> > + uint64_t reserved_13 : 1;
> > + uint64_t func : 16;
> > + uint64_t aura : 20;
> > + uint64_t xtype : 2;
> > + uint64_t reserved_52_53 : 2;
> > + uint64_t pt : 2;
> > + uint64_t fport : 2;
> > + uint64_t reserved_58_59 : 2;
> > + uint64_t lport : 2;
> > + uint64_t reserved_62_63 : 2;
> > + /* Word 0 - End */
> > + uint64_t ptr : 64;
> > + /* Word 1 - End */
> > + uint64_t tag : 32;
> > + uint64_t tt : 2;
> > + uint64_t grp : 10;
> > + uint64_t reserved_172_173 : 2;
> > + uint64_t fl : 1;
> > + uint64_t ii : 1;
> > + uint64_t fi : 1;
> > + uint64_t ca : 1;
> > + uint64_t csel : 1;
> > + uint64_t reserved_179_191 : 3;
> > + /* Word 2 - End */
> > + uint64_t reserved_192_255 : 64;
> > + /* Word 3 - End */
> > + } s;
> > +};
> > +
> > +/** @endcond */
>
> This is not required.
ack
>
> > +
> > +#endif /*__DEV_DPI_HW_H__*/
> > diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
> > index d9871a6b45..d0aeb6b68c 100644
> > --- a/drivers/common/cnxk/meson.build
> > +++ b/drivers/common/cnxk/meson.build
> > @@ -19,6 +19,7 @@ sources = files(
> > 'roc_cpt.c',
> > 'roc_cpt_debug.c',
> > 'roc_dev.c',
> > + 'roc_dpi.c',
> > 'roc_hash.c',
> > 'roc_idev.c',
> > 'roc_irq.c',
> > diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
> > index b8f3667c6c..359d31327a 100644
> > --- a/drivers/common/cnxk/roc_api.h
> > +++ b/drivers/common/cnxk/roc_api.h
> > @@ -33,6 +33,7 @@
> >
> > /* HW structure definition */
> > #include "hw/cpt.h"
> > +#include "hw/dpi.h"
> > #include "hw/nix.h"
> > #include "hw/npa.h"
> > #include "hw/npc.h"
> > @@ -86,6 +87,9 @@
> > #include "roc_ie_ot.h"
> > #include "roc_se.h"
> >
> > +/* DPI */
> > +#include "roc_dpi.h"
> > +
> > /* HASH computation */
> > #include "roc_hash.h"
> >
> > diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c
> > new file mode 100644
> > index 0000000000..a9613d82f1
> > --- /dev/null
> > +++ b/drivers/common/cnxk/roc_dpi.c
> > @@ -0,0 +1,193 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(C) 2021 Marvell.
> > + */
> > +
> > +#include "roc_api.h"
> > +#include "roc_priv.h"
>
> move internal headers file after the public ones with a new line.
ack
>
> > +#include <fcntl.h>
> > +#include <sys/stat.h>
> > +#include <sys/types.h>
> > +#include <unistd.h>
> > +
> > +#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
> > +
> > +static inline int
> > +send_msg_to_pf(struct plt_pci_addr *pci_addr, const char *value, int size)
> > +{
> > + char buf[255] = {0};
> > + int res, fd;
> > +
> > + res = snprintf(
> > + buf, sizeof(buf), "/sys/bus/pci/devices/" PCI_PRI_FMT "/%s",
> > + pci_addr->domain, pci_addr->bus, DPI_PF_DBDF_DEVICE & 0x7,
> > + DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
> > +
> > + if ((res < 0) || ((size_t)res > sizeof(buf)))
> > + return -ERANGE;
> > +
> > + fd = open(buf, O_WRONLY);
> > + if (fd < 0)
> > + return -EACCES;
> > +
> > + res = write(fd, value, size);
> > + close(fd);
> > + if (res < 0)
> > + return -EACCES;
> > +
> > + return 0;
> > +}
> > +
> > +int
> > +roc_dpi_queue_start(struct roc_dpi *dpi)
> > +{
> > + plt_write64(0x1, dpi->rbase + DPI_VDMA_EN);
> > + return 0;
> > +}
> > +
> > +int
> > +roc_dpi_queue_stop(struct roc_dpi *dpi)
> > +{
> > + plt_write64(0x0, dpi->rbase + DPI_VDMA_EN);
> > + return 0;
> > +}
> > +
> > +int
> > +roc_dpi_queue_configure(struct roc_dpi *roc_dpi)
> > +{
> > + struct plt_pci_device *pci_dev;
> > + const struct plt_memzone *dpi_mz;
> > + dpi_mbox_msg_t mbox_msg;
> > + struct npa_pool_s pool;
> > + struct npa_aura_s aura;
> > + int rc, count, buflen;
> > + uint64_t aura_handle;
> > + plt_iova_t iova;
> > + char name[32];
> > +
> > + if (!roc_dpi) {
> > + plt_err("roc_dpi is NULL");
> > + return -EINVAL;
> > + }
> > +
> > + pci_dev = roc_dpi->pci_dev;
> > + memset(&pool, 0, sizeof(struct npa_pool_s));
> > + pool.nat_align = 1;
> > +
> > + memset(&aura, 0, sizeof(aura));
> > + rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE,
> > + DPI_CMD_QUEUE_BUFS, &aura, &pool);
> > + if (rc) {
> > + plt_err("Failed to create NPA pool, err %d\n", rc);
> > + return rc;
> > + }
> > +
> > + snprintf(name, sizeof(name), "dpimem%d", roc_dpi->vfid);
> > + buflen = DPI_CMD_QUEUE_SIZE * DPI_CMD_QUEUE_BUFS;
> > + dpi_mz = plt_memzone_reserve_aligned(name, buflen, 0,
> > + DPI_CMD_QUEUE_SIZE);
> > + if (dpi_mz == NULL) {
> > + plt_err("dpi memzone reserve failed");
> > + rc = -ENOMEM;
> > + goto err1;
> > + }
> > +
> > + roc_dpi->mz = dpi_mz;
> > + iova = dpi_mz->iova;
> > + for (count = 0; count < DPI_CMD_QUEUE_BUFS; count++) {
> > + roc_npa_aura_op_free(aura_handle, 0, iova);
> > + iova += DPI_CMD_QUEUE_SIZE;
> > + }
> > +
> > + roc_dpi->chunk_base = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
> > + if (!roc_dpi->chunk_base) {
> > + plt_err("Failed to alloc buffer from NPA aura");
> > + rc = -ENOMEM;
> > + goto err2;
> > + }
> > +
> > + roc_dpi->chunk_next = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
> > + if (!roc_dpi->chunk_next) {
> > + plt_err("Failed to alloc buffer from NPA aura");
> > + rc = -ENOMEM;
> > + goto err2;
> > + }
> > +
> > + roc_dpi->aura_handle = aura_handle;
> > + /* subtract 2 as they have already been alloc'ed above */
> > + roc_dpi->pool_size_m1 = (DPI_CMD_QUEUE_SIZE >> 3) - 2;
> > +
> > + plt_write64(0x0, roc_dpi->rbase + DPI_VDMA_REQQ_CTL);
> > + plt_write64(((uint64_t)(roc_dpi->chunk_base) >> 7) << 7,
> > + roc_dpi->rbase + DPI_VDMA_SADDR);
> > + mbox_msg.u[0] = 0;
> > + mbox_msg.u[1] = 0;
> > + /* DPI PF driver expects vfid starts from index 0 */
> > + mbox_msg.s.vfid = roc_dpi->vfid;
> > + mbox_msg.s.cmd = DPI_QUEUE_OPEN;
> > + mbox_msg.s.csize = DPI_CMD_QUEUE_SIZE;
> > + mbox_msg.s.aura = roc_npa_aura_handle_to_aura(aura_handle);
> > + mbox_msg.s.sso_pf_func = idev_sso_pffunc_get();
> > + mbox_msg.s.npa_pf_func = idev_npa_pffunc_get();
> > +
> > + rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
> > + sizeof(dpi_mbox_msg_t));
> > + if (rc < 0) {
> > + plt_err("Failed to send mbox message %d to DPI PF, err %d",
> > + mbox_msg.s.cmd, rc);
> > + goto err2;
> > + }
> > +
> > + return rc;
> > +
> > +err2:
> > + roc_npa_pool_destroy(aura_handle);
> > +err1:
> > + plt_memzone_free(dpi_mz);
> > + return rc;
> > +}
> > +
> > +int
> > +roc_dpi_dev_init(struct roc_dpi *roc_dpi)
> > +{
> > + struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
> > + uint16_t vfid;
> > +
> > + roc_dpi->rbase = pci_dev->mem_resource[0].addr;
> > + vfid = ((pci_dev->addr.devid & 0x1F) << 3) |
> > + (pci_dev->addr.function & 0x7);
> > + vfid -= 1;
> > + roc_dpi->vfid = vfid;
> > + plt_spinlock_init(&roc_dpi->chunk_lock);
> > +
> > + return 0;
> > +}
> > +
> > +int
> > +roc_dpi_dev_fini(struct roc_dpi *roc_dpi)
> > +{
> > + struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
> > + dpi_mbox_msg_t mbox_msg;
> > + uint64_t reg;
> > + int rc;
> > +
> > + /* Wait for SADDR to become idle */
> > + reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
> > + while (!(reg & BIT_ULL(63)))
> > + reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
> > +
> > + mbox_msg.u[0] = 0;
> > + mbox_msg.u[1] = 0;
> > + mbox_msg.s.vfid = roc_dpi->vfid;
> > + mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
> > +
> > + rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
> > + sizeof(dpi_mbox_msg_t));
> > + if (rc < 0)
> > + plt_err("Failed to send mbox message %d to DPI PF, err %d",
> > + mbox_msg.s.cmd, rc);
> > +
> > + roc_npa_pool_destroy(roc_dpi->aura_handle);
> > + plt_memzone_free(roc_dpi->mz);
> > +
> > + return rc;
> > +}
> > diff --git a/drivers/common/cnxk/roc_dpi.h b/drivers/common/cnxk/roc_dpi.h
> > new file mode 100644
> > index 0000000000..c2e6d997ea
> > --- /dev/null
> > +++ b/drivers/common/cnxk/roc_dpi.h
> > @@ -0,0 +1,44 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(C) 2021 Marvell.
> > + */
> > +
> > +#ifndef _ROC_DPI_H_
> > +#define _ROC_DPI_H_
> > +
> > +struct roc_dpi_args {
> > + uint8_t num_ssegs;
> > + uint8_t num_dsegs;
> > + uint8_t comp_type;
> > + uint8_t direction;
> > + uint8_t sdevice;
> > + uint8_t ddevice;
> > + uint8_t swap;
> > + uint8_t use_lock : 1;
> > + uint8_t tt : 7;
> > + uint16_t func;
> > + uint16_t grp;
> > + uint32_t tag;
> > + uint64_t comp_ptr;
> > +};
> > +
> > +struct roc_dpi {
> > + struct plt_pci_device *pci_dev;
> > + const struct plt_memzone *mz;
> > + uint8_t *rbase;
> > + uint16_t vfid;
> > + uint16_t pool_size_m1;
> > + uint16_t chunk_head;
> > + uint64_t *chunk_base;
> > + uint64_t *chunk_next;
> > + uint64_t aura_handle;
> > + plt_spinlock_t chunk_lock;
>
> segregate input parameters for roc_dpi_dev_init() and RoC managed
> variables with comments.
>
> > +} __plt_cache_aligned;
> > +
> > +int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi);
> > +int __roc_api roc_dpi_dev_fini(struct roc_dpi *roc_dpi);
> > +
> > +int __roc_api roc_dpi_queue_configure(struct roc_dpi *dpi);
> > +int __roc_api roc_dpi_queue_start(struct roc_dpi *dpi);
> > +int __roc_api roc_dpi_queue_stop(struct roc_dpi *dpi);
>
> For future proof and make API looks clean, add quued id.
> If there will not be any queue in the future change to
> roc_dpi_configure()... etc.
> Please change start/stop change to enable/disable.
ack. will get rid of "queue" in the name.
>
>
> > +
> > +#endif
> > diff --git a/drivers/common/cnxk/roc_dpi_priv.h b/drivers/common/cnxk/roc_dpi_priv.h
> > new file mode 100644
> > index 0000000000..92953fbcfc
> > --- /dev/null
> > +++ b/drivers/common/cnxk/roc_dpi_priv.h
> > @@ -0,0 +1,40 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(C) 2021 Marvell.
> > + */
> > +
> > +#ifndef _ROC_DPI_PRIV_H_
> > +#define _ROC_DPI_PRIV_H_
> > +
> > +#define DPI_MAX_VFS 8
> > +
> > +/* DPI PF DBDF information macros */
> > +#define DPI_PF_DBDF_DEVICE 0
> > +#define DPI_PF_DBDF_FUNCTION 0
> > +
> > +#define DPI_QUEUE_OPEN 0x1
> > +#define DPI_QUEUE_CLOSE 0x2
> > +#define DPI_REG_DUMP 0x3
> > +#define DPI_GET_REG_CFG 0x4
> > +
> > +#define DPI_CMD_QUEUE_SIZE 4096
> > +#define DPI_CMD_QUEUE_BUFS 1024
> > +
> > +typedef union dpi_mbox_msg_t {
> > + uint64_t u[2];
> > + struct dpi_mbox_message_s {
> > + /* VF ID to configure */
> > + uint64_t vfid : 4;
> > + /* Command code */
> > + uint64_t cmd : 4;
> > + /* Command buffer size in 8-byte words */
> > + uint64_t csize : 14;
> > + /* aura of the command buffer */
> > + uint64_t aura : 20;
> > + /* SSO PF function */
> > + uint64_t sso_pf_func : 16;
> > + /* NPA PF function */
> > + uint64_t npa_pf_func : 16;
> > + } s;
> > +} dpi_mbox_msg_t;
> > +
> > +#endif
> > diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
> > index 5da23fe5f8..61d4781209 100644
> > --- a/drivers/common/cnxk/roc_platform.h
> > +++ b/drivers/common/cnxk/roc_platform.h
> > @@ -69,6 +69,7 @@
> > #define __roc_api __rte_internal
> > #define plt_iova_t rte_iova_t
> >
> > +#define plt_pci_addr rte_pci_addr
> > #define plt_pci_device rte_pci_device
> > #define plt_pci_read_config rte_pci_read_config
> > #define plt_pci_find_ext_capability rte_pci_find_ext_capability
> > diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
> > index f72bbd568f..782b90cf8d 100644
> > --- a/drivers/common/cnxk/roc_priv.h
> > +++ b/drivers/common/cnxk/roc_priv.h
> > @@ -41,4 +41,7 @@
> > /* NIX Inline dev */
> > #include "roc_nix_inl_priv.h"
> >
> > +/* DPI */
> > +#include "roc_dpi_priv.h"
> > +
> > #endif /* _ROC_PRIV_H_ */
> > diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
> > index 8d4d42f476..3edc42cfd6 100644
> > --- a/drivers/common/cnxk/version.map
> > +++ b/drivers/common/cnxk/version.map
> > @@ -68,6 +68,11 @@ INTERNAL {
> > roc_cpt_lmtline_init;
> > roc_cpt_parse_hdr_dump;
> > roc_cpt_rxc_time_cfg;
> > + roc_dpi_dev_init;
> > + roc_dpi_dev_fini;
> > + roc_dpi_queue_configure;
> > + roc_dpi_queue_start;
> > + roc_dpi_queue_stop;
> > roc_error_msg_get;
> > roc_hash_sha1_gen;
> > roc_hash_sha256_gen;
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH 2/4] dma/cnxk: create and initialize dmadev on pci probe
2021-10-26 8:36 ` Jerin Jacob
@ 2021-10-26 21:05 ` Radha Mohan
0 siblings, 0 replies; 32+ messages in thread
From: Radha Mohan @ 2021-10-26 21:05 UTC (permalink / raw)
To: Jerin Jacob
Cc: Radha Mohan Chintakuntla, Thomas Monjalon, fengchengwen,
Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Koteswara Rao Kottidi, Jerin Jacob, Satananda Burla,
dpdk-dev
On Tue, Oct 26, 2021 at 2:32 AM Jerin Jacob <jerinjacobk@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 9:43 AM Radha Mohan Chintakuntla
> <radhac@marvell.com> wrote:
> >
> > This patch creates and initializes a dmadev device on pci probe.
> >
> > Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> > ---
> > MAINTAINERS | 7 +-
> > doc/guides/dmadevs/cnxk.rst | 53 +++++++++++++++
> > doc/guides/dmadevs/index.rst | 1 +
> > drivers/dma/cnxk/cnxk_dmadev.c | 119 +++++++++++++++++++++++++++++++++
> > drivers/dma/cnxk/cnxk_dmadev.h | 11 +++
> > drivers/dma/cnxk/meson.build | 7 ++
> > drivers/dma/meson.build | 1 +
> > 7 files changed, 198 insertions(+), 1 deletion(-)
> > create mode 100644 doc/guides/dmadevs/cnxk.rst
> > create mode 100644 drivers/dma/cnxk/cnxk_dmadev.c
> > create mode 100644 drivers/dma/cnxk/cnxk_dmadev.h
> > create mode 100644 drivers/dma/cnxk/meson.build
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index be2c9b6815..cdc2d98a6b 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1186,7 +1186,6 @@ F: drivers/compress/zlib/
> > F: doc/guides/compressdevs/zlib.rst
> > F: doc/guides/compressdevs/features/zlib.ini
> >
> > -
>
> Unwanted line deletion.
Ah ok. overlooked when resolving conflicts with latest.
>
> > DMAdev Drivers
> > --------------
> >
> > @@ -1202,6 +1201,12 @@ M: Conor Walsh <conor.walsh@intel.com>
> > F: drivers/dma/ioat/
> > F: doc/guides/dmadevs/ioat.rst
> >
> > +Marvell CNXK DPI DMA
> > +M: Radha Mohan Chintakuntla <radhac@marvell.com>
> > +M: Veerasenareddy Burru <vburru@marvell.com>
> > +F: drivers/dma/cnxk/
> > +F: doc/guides/dmadevs/cnxk.rst
> > +
> >
> > RegEx Drivers
> > -------------
> > diff --git a/doc/guides/dmadevs/cnxk.rst b/doc/guides/dmadevs/cnxk.rst
> > new file mode 100644
> > index 0000000000..8ae7c1f8cd
> > --- /dev/null
> > +++ b/doc/guides/dmadevs/cnxk.rst
> > @@ -0,0 +1,53 @@
> > +.. SPDX-License-Identifier: BSD-3-Clause
> > + Copyright(c) 2021 Marvell International Ltd.
> > +
> > +.. include:: <isonum.txt>
> > +
>
>
> Please link top-level doc/guides/platform/cnxk.rst documentation file
> to this file.
>
sure will do in v2.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations
2021-10-26 8:41 ` Jerin Jacob
@ 2021-10-28 18:18 ` Radha Mohan
2021-10-29 14:54 ` Jerin Jacob
0 siblings, 1 reply; 32+ messages in thread
From: Radha Mohan @ 2021-10-28 18:18 UTC (permalink / raw)
To: Jerin Jacob
Cc: Radha Mohan Chintakuntla, Thomas Monjalon, fengchengwen,
Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Koteswara Rao Kottidi, Jerin Jacob, Satananda Burla,
dpdk-dev
On Tue, Oct 26, 2021 at 1:49 AM Jerin Jacob <jerinjacobk@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 9:43 AM Radha Mohan Chintakuntla
> <radhac@marvell.com> wrote:
> >
> > Add functions for the dmadev vchan setup and DMA operations.
> >
> > Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> > ---
> > drivers/dma/cnxk/cnxk_dmadev.c | 322 +++++++++++++++++++++++++++++++++
> > drivers/dma/cnxk/cnxk_dmadev.h | 53 ++++++
> > drivers/dma/cnxk/version.map | 3 +
> > 3 files changed, 378 insertions(+)
> > create mode 100644 drivers/dma/cnxk/version.map
> >
> > diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
> > index 620766743d..8434579aa2 100644
> > --- a/drivers/dma/cnxk/cnxk_dmadev.c
> > +++ b/drivers/dma/cnxk/cnxk_dmadev.c
> > @@ -18,6 +18,322 @@
> > #include <roc_api.h>
> > #include <cnxk_dmadev.h>
> >
> > +static int
> > +cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
> > + struct rte_dma_info *dev_info, uint32_t size)
> > +{
> > + RTE_SET_USED(dev);
> > + RTE_SET_USED(size);
> > +
> > + dev_info->max_vchans = 1;
> > + dev_info->nb_vchans = 1;
> > + dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
> > + RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
> > + RTE_DMA_CAPA_OPS_COPY;
> > + dev_info->max_desc = DPI_MAX_DESC;
> > + dev_info->min_desc = 1;
> > + dev_info->max_sges = DPI_MAX_POINTER;
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +cnxk_dmadev_configure(struct rte_dma_dev *dev,
> > + const struct rte_dma_conf *conf, uint32_t conf_sz)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = NULL;
> > + int rc = 0;
> > +
> > + RTE_SET_USED(conf);
> > + RTE_SET_USED(conf);
> > + RTE_SET_USED(conf_sz);
> > + RTE_SET_USED(conf_sz);
> > + dpivf = dev->fp_obj->dev_private;
> > + rc = roc_dpi_queue_configure(&dpivf->rdpi);
> > + if (rc < 0)
> > + plt_err("DMA queue configure failed err = %d", rc);
> > +
> > + return rc;
> > +}
> > +
> > +static int
> > +cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
> > + const struct rte_dma_vchan_conf *conf,
> > + uint32_t conf_sz)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> > + struct cnxk_dpi_compl_s *comp_data;
> > + int i;
> > +
> > + RTE_SET_USED(vchan);
> > + RTE_SET_USED(conf_sz);
> > +
> > + switch (conf->direction) {
> > + case RTE_DMA_DIR_DEV_TO_MEM:
> > + dpivf->conf.direction = DPI_XTYPE_INBOUND;
> > + dpivf->conf.src_port = conf->src_port.pcie.coreid;
> > + dpivf->conf.dst_port = 0;
> > + break;
> > + case RTE_DMA_DIR_MEM_TO_DEV:
> > + dpivf->conf.direction = DPI_XTYPE_OUTBOUND;
> > + dpivf->conf.src_port = 0;
> > + dpivf->conf.dst_port = conf->dst_port.pcie.coreid;
> > + break;
> > + case RTE_DMA_DIR_MEM_TO_MEM:
> > + dpivf->conf.direction = DPI_XTYPE_INTERNAL_ONLY;
> > + dpivf->conf.src_port = 0;
> > + dpivf->conf.dst_port = 0;
> > + break;
> > + case RTE_DMA_DIR_DEV_TO_DEV:
> > + dpivf->conf.direction = DPI_XTYPE_EXTERNAL_ONLY;
> > + dpivf->conf.src_port = conf->src_port.pcie.coreid;
> > + dpivf->conf.dst_port = conf->src_port.pcie.coreid;
> > + };
> > +
> > + for (i = 0; i < conf->nb_desc; i++) {
> > + comp_data = rte_zmalloc(NULL, sizeof(*comp_data), 0);
> > + dpivf->conf.c_desc.compl_ptr[i] = comp_data;
> > + };
> > + dpivf->conf.c_desc.max_cnt = DPI_MAX_DESC;
> > + dpivf->conf.c_desc.head = 0;
> > + dpivf->conf.c_desc.tail = 0;
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +cnxk_dmadev_start(struct rte_dma_dev *dev)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> > +
> > + roc_dpi_queue_start(&dpivf->rdpi);
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +cnxk_dmadev_stop(struct rte_dma_dev *dev)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> > +
> > + roc_dpi_queue_stop(&dpivf->rdpi);
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +cnxk_dmadev_close(struct rte_dma_dev *dev)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> > +
> > + roc_dpi_queue_stop(&dpivf->rdpi);
> > + roc_dpi_dev_fini(&dpivf->rdpi);
> > +
> > + return 0;
> > +}
> > +
> > +static inline int
> > +__dpi_queue_write(struct roc_dpi *dpi, uint64_t *cmds, int cmd_count)
> > +{
> > + uint64_t *ptr = dpi->chunk_base;
> > +
> > + if ((cmd_count < DPI_MIN_CMD_SIZE) || (cmd_count > DPI_MAX_CMD_SIZE) ||
> > + cmds == NULL)
> > + return -EINVAL;
> > +
> > + /*
> > + * Normally there is plenty of room in the current buffer for the
> > + * command
> > + */
> > + if (dpi->chunk_head + cmd_count < dpi->pool_size_m1) {
> > + ptr += dpi->chunk_head;
> > + dpi->chunk_head += cmd_count;
> > + while (cmd_count--)
> > + *ptr++ = *cmds++;
> > + } else {
> > + int count;
> > + uint64_t *new_buff = dpi->chunk_next;
> > +
> > + dpi->chunk_next =
> > + (void *)roc_npa_aura_op_alloc(dpi->aura_handle, 0);
> > + if (!dpi->chunk_next) {
> > + plt_err("Failed to alloc next buffer from NPA");
> > + return -ENOMEM;
> > + }
> > +
> > + /*
> > + * Figure out how many cmd words will fit in this buffer.
> > + * One location will be needed for the next buffer pointer.
> > + */
> > + count = dpi->pool_size_m1 - dpi->chunk_head;
> > + ptr += dpi->chunk_head;
> > + cmd_count -= count;
> > + while (count--)
> > + *ptr++ = *cmds++;
> > +
> > + /*
> > + * chunk next ptr is 2 DWORDS
> > + * second DWORD is reserved.
> > + */
> > + *ptr++ = (uint64_t)new_buff;
> > + *ptr = 0;
> > +
> > + /*
> > + * The current buffer is full and has a link to the next
> > + * buffers. Time to write the rest of the commands into the new
> > + * buffer.
> > + */
> > + dpi->chunk_base = new_buff;
> > + dpi->chunk_head = cmd_count;
> > + ptr = new_buff;
> > + while (cmd_count--)
> > + *ptr++ = *cmds++;
> > +
> > + /* queue index may be greater than pool size */
> > + if (dpi->chunk_head >= dpi->pool_size_m1) {
> > + new_buff = dpi->chunk_next;
> > + dpi->chunk_next =
> > + (void *)roc_npa_aura_op_alloc(dpi->aura_handle,
> > + 0);
> > + if (!dpi->chunk_next) {
> > + plt_err("Failed to alloc next buffer from NPA");
> > + return -ENOMEM;
> > + }
> > + /* Write next buffer address */
> > + *ptr = (uint64_t)new_buff;
> > + dpi->chunk_base = new_buff;
> > + dpi->chunk_head = 0;
> > + }
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
> > + rte_iova_t dst, uint32_t length, uint64_t flags)
> > +{
> > + uint64_t cmd[DPI_MAX_CMD_SIZE] = {0};
> > + union dpi_instr_hdr_s *header = (union dpi_instr_hdr_s *)&cmd[0];
> > + rte_iova_t fptr, lptr;
> > + struct cnxk_dpi_vf_s *dpivf = dev_private;
> > + struct cnxk_dpi_compl_s *comp_ptr;
> > + int num_words = 0;
> > + int rc;
> > +
> > + RTE_SET_USED(vchan);
> > +
> > + header->s.xtype = dpivf->conf.direction;
> > + header->s.pt = DPI_HDR_PT_ZBW_CA;
> > + comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
> > + comp_ptr->cdata = DPI_REQ_CDATA;
> > + header->s.ptr = (uint64_t)comp_ptr;
> > + STRM_INC(dpivf->conf.c_desc);
> > +
> > + /* pvfe should be set for inbound and outbound only */
> > + if (header->s.xtype <= 1)
> > + header->s.pvfe = 1;
> > + num_words += 4;
> > +
> > + header->s.nfst = 1;
> > + header->s.nlst = 1;
>
> Including filling zeros in cmd and the rest of the filling can be
> moved to slow path..
>
> Please change the logic to populate the static items based on
> configure/channel setup
> in slowpath and update only per transfer-specific items to have better
> performance.
>
These are instruction header values that we are filling. If you look
at it there is really one 64bit field that can be filled beforehand
a.k.a slowpath in vchan_setup().
Rest of the header can only be filled here like nlst, nfst (these are
number of pointers to be DMA'ed) and completion pointer. So just for
that I do not see a value in moving around the code.
<snip>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations
2021-10-28 18:18 ` Radha Mohan
@ 2021-10-29 14:54 ` Jerin Jacob
2021-10-29 18:02 ` Radha Mohan
0 siblings, 1 reply; 32+ messages in thread
From: Jerin Jacob @ 2021-10-29 14:54 UTC (permalink / raw)
To: Radha Mohan
Cc: Radha Mohan Chintakuntla, Thomas Monjalon, fengchengwen,
Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Koteswara Rao Kottidi, Jerin Jacob, Satananda Burla,
dpdk-dev
On Thu, Oct 28, 2021 at 11:48 PM Radha Mohan <mohun106@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 1:49 AM Jerin Jacob <jerinjacobk@gmail.com> wrote:
> >
> > On Tue, Oct 26, 2021 at 9:43 AM Radha Mohan Chintakuntla
> > <radhac@marvell.com> wrote:
> > >
> > > Add functions for the dmadev vchan setup and DMA operations.
> > >
> > > Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> > > +static int
> > > +cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
> > > + rte_iova_t dst, uint32_t length, uint64_t flags)
> > > +{
> > > + uint64_t cmd[DPI_MAX_CMD_SIZE] = {0};
> > > + union dpi_instr_hdr_s *header = (union dpi_instr_hdr_s *)&cmd[0];
> > > + rte_iova_t fptr, lptr;
> > > + struct cnxk_dpi_vf_s *dpivf = dev_private;
> > > + struct cnxk_dpi_compl_s *comp_ptr;
> > > + int num_words = 0;
> > > + int rc;
> > > +
> > > + RTE_SET_USED(vchan);
> > > +
> > > + header->s.xtype = dpivf->conf.direction;
> > > + header->s.pt = DPI_HDR_PT_ZBW_CA;
> > > + comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
> > > + comp_ptr->cdata = DPI_REQ_CDATA;
> > > + header->s.ptr = (uint64_t)comp_ptr;
> > > + STRM_INC(dpivf->conf.c_desc);
> > > +
> > > + /* pvfe should be set for inbound and outbound only */
> > > + if (header->s.xtype <= 1)
> > > + header->s.pvfe = 1;
> > > + num_words += 4;
> > > +
> > > + header->s.nfst = 1;
> > > + header->s.nlst = 1;
> >
> > Including filling zeros in cmd and the rest of the filling can be
> > moved to slow path..
> >
> > Please change the logic to populate the static items based on
> > configure/channel setup
> > in slowpath and update only per transfer-specific items to have better
> > performance.
> >
> These are instruction header values that we are filling. If you look
> at it there is really one 64bit field that can be filled beforehand
> a.k.a slowpath in vchan_setup().
> Rest of the header can only be filled here like nlst, nfst (these are
> number of pointers to be DMA'ed) and completion pointer. So just for
> that I do not see a value in moving around the code.
Two things,
1) By dong like below,
> > > + header->s.nfst = 1;
> > > + header->s.nlst = 1;
it will generate multiple stores. One option is to have a local u64
variable and form the required descriptor and write it one shot.
It is a standard optimation strategy used in fastpath.
2) uint64_t cmd[DPI_MAX_CMD_SIZE] = {0}; This will result in memset of
64B, That reason for creating
template based on vchan make sense.
Looks like moving to a template-based scheme need a lot of rework in
the driver,
I will leave you to decide performance vs other aspects as you are
maintaining the driver.
No strong opinion.
>
> <snip>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations
2021-10-29 14:54 ` Jerin Jacob
@ 2021-10-29 18:02 ` Radha Mohan
0 siblings, 0 replies; 32+ messages in thread
From: Radha Mohan @ 2021-10-29 18:02 UTC (permalink / raw)
To: Jerin Jacob
Cc: Radha Mohan Chintakuntla, Thomas Monjalon, fengchengwen,
Nithin Dabilpuram, Kiran Kumar K, Sunil Kumar Kori,
Satha Koteswara Rao Kottidi, Jerin Jacob, Satananda Burla,
dpdk-dev
On Fri, Oct 29, 2021 at 7:54 AM Jerin Jacob <jerinjacobk@gmail.com> wrote:
>
> On Thu, Oct 28, 2021 at 11:48 PM Radha Mohan <mohun106@gmail.com> wrote:
> >
> > On Tue, Oct 26, 2021 at 1:49 AM Jerin Jacob <jerinjacobk@gmail.com> wrote:
> > >
> > > On Tue, Oct 26, 2021 at 9:43 AM Radha Mohan Chintakuntla
> > > <radhac@marvell.com> wrote:
> > > >
> > > > Add functions for the dmadev vchan setup and DMA operations.
> > > >
> > > > Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
>
> > > > +static int
> > > > +cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
> > > > + rte_iova_t dst, uint32_t length, uint64_t flags)
> > > > +{
> > > > + uint64_t cmd[DPI_MAX_CMD_SIZE] = {0};
> > > > + union dpi_instr_hdr_s *header = (union dpi_instr_hdr_s *)&cmd[0];
> > > > + rte_iova_t fptr, lptr;
> > > > + struct cnxk_dpi_vf_s *dpivf = dev_private;
> > > > + struct cnxk_dpi_compl_s *comp_ptr;
> > > > + int num_words = 0;
> > > > + int rc;
> > > > +
> > > > + RTE_SET_USED(vchan);
> > > > +
> > > > + header->s.xtype = dpivf->conf.direction;
> > > > + header->s.pt = DPI_HDR_PT_ZBW_CA;
> > > > + comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
> > > > + comp_ptr->cdata = DPI_REQ_CDATA;
> > > > + header->s.ptr = (uint64_t)comp_ptr;
> > > > + STRM_INC(dpivf->conf.c_desc);
> > > > +
> > > > + /* pvfe should be set for inbound and outbound only */
> > > > + if (header->s.xtype <= 1)
> > > > + header->s.pvfe = 1;
> > > > + num_words += 4;
> > > > +
> > > > + header->s.nfst = 1;
> > > > + header->s.nlst = 1;
> > >
> > > Including filling zeros in cmd and the rest of the filling can be
> > > moved to slow path..
> > >
> > > Please change the logic to populate the static items based on
> > > configure/channel setup
> > > in slowpath and update only per transfer-specific items to have better
> > > performance.
> > >
> > These are instruction header values that we are filling. If you look
> > at it there is really one 64bit field that can be filled beforehand
> > a.k.a slowpath in vchan_setup().
> > Rest of the header can only be filled here like nlst, nfst (these are
> > number of pointers to be DMA'ed) and completion pointer. So just for
> > that I do not see a value in moving around the code.
>
> Two things,
>
> 1) By dong like below,
> > > > + header->s.nfst = 1;
> > > > + header->s.nlst = 1;
>
> it will generate multiple stores.
No it won't for this case. Here is how the compiler generated the
writes to the 64-bit fields of the header field.
7a4: d2e00821 mov x1, #0x41000000000000 //
#18295873486192640
>One option is to have a local u64
> variable and form the required descriptor and write it one shot.
> It is a standard optimation strategy used in fastpath.
Maybe not here.
>
> 2) uint64_t cmd[DPI_MAX_CMD_SIZE] = {0}; This will result in memset of
> 64B, That reason for creating
> template based on vchan make sense.
>
> Looks like moving to a template-based scheme need a lot of rework in
> the driver,
> I will leave you to decide performance vs other aspects as you are
> maintaining the driver.
> No strong opinion.
>
Ok understand. We'll do a v2 with some improvments.
>
> >
> > <snip>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH v2 1/4] common/cnxk: add DPI DMA support
2021-10-26 4:12 [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support Radha Mohan Chintakuntla
` (3 preceding siblings ...)
2021-10-26 8:33 ` [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support Jerin Jacob
@ 2021-11-02 3:40 ` Radha Mohan Chintakuntla
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
` (4 more replies)
4 siblings, 5 replies; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-11-02 3:40 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
Add base support as ROC(Rest of Chip) API which will be used by PMD
dmadev driver.
This patch adds routines to init, fini, configure the DPI DMA device
found in Marvell's CN9k or CN10k SoC families.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v1:
- Changed to roc_dpi_enable() from roc_dpi_queue_start()
- Changed to roc_dpi_disable() from roc_dp_queue_stop()
- Moved part of DMA header preparation to vchan_setup() which can save
some CPU cycles in fastpath.
drivers/common/cnxk/hw/dpi.h | 141 +++++++++++++++++++++
drivers/common/cnxk/meson.build | 1 +
drivers/common/cnxk/roc_api.h | 4 +
drivers/common/cnxk/roc_dpi.c | 193 +++++++++++++++++++++++++++++
drivers/common/cnxk/roc_dpi.h | 46 +++++++
drivers/common/cnxk/roc_dpi_priv.h | 40 ++++++
drivers/common/cnxk/roc_platform.h | 1 +
drivers/common/cnxk/roc_priv.h | 3 +
drivers/common/cnxk/version.map | 5 +
9 files changed, 434 insertions(+)
create mode 100644 drivers/common/cnxk/hw/dpi.h
create mode 100644 drivers/common/cnxk/roc_dpi.c
create mode 100644 drivers/common/cnxk/roc_dpi.h
create mode 100644 drivers/common/cnxk/roc_dpi_priv.h
diff --git a/drivers/common/cnxk/hw/dpi.h b/drivers/common/cnxk/hw/dpi.h
new file mode 100644
index 0000000000..69fe7b6d33
--- /dev/null
+++ b/drivers/common/cnxk/hw/dpi.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+/**
+ * DPI device HW definitions.
+ */
+#ifndef __DEV_DPI_HW_H__
+#define __DEV_DPI_HW_H__
+
+#include <stdint.h>
+
+/* DPI VF register offsets from VF_BAR0 */
+#define DPI_VDMA_EN (0x0)
+#define DPI_VDMA_REQQ_CTL (0x8)
+#define DPI_VDMA_DBELL (0x10)
+#define DPI_VDMA_SADDR (0x18)
+#define DPI_VDMA_COUNTS (0x20)
+#define DPI_VDMA_NADDR (0x28)
+#define DPI_VDMA_IWBUSY (0x30)
+#define DPI_VDMA_CNT (0x38)
+#define DPI_VF_INT (0x100)
+#define DPI_VF_INT_W1S (0x108)
+#define DPI_VF_INT_ENA_W1C (0x110)
+#define DPI_VF_INT_ENA_W1S (0x118)
+
+/**
+ * Enumeration dpi_hdr_xtype_e
+ *
+ * DPI Transfer Type Enumeration
+ * Enumerates the pointer type in DPI_DMA_INSTR_HDR_S[XTYPE].
+ */
+#define DPI_XTYPE_OUTBOUND (0)
+#define DPI_XTYPE_INBOUND (1)
+#define DPI_XTYPE_INTERNAL_ONLY (2)
+#define DPI_XTYPE_EXTERNAL_ONLY (3)
+#define DPI_HDR_XTYPE_MASK 0x3
+
+#define DPI_HDR_PT_ZBW_CA 0x0
+#define DPI_HDR_PT_ZBW_NC 0x1
+#define DPI_HDR_PT_WQP 0x2
+#define DPI_HDR_PT_WQP_NOSTATUS 0x0
+#define DPI_HDR_PT_WQP_STATUSCA 0x1
+#define DPI_HDR_PT_WQP_STATUSNC 0x3
+#define DPI_HDR_PT_CNT 0x3
+#define DPI_HDR_PT_MASK 0x3
+
+#define DPI_HDR_TT_MASK 0x3
+#define DPI_HDR_GRP_MASK 0x3FF
+#define DPI_HDR_FUNC_MASK 0xFFFF
+
+/* Big endian data bit position in DMA local pointer */
+#define DPI_LPTR_BED_BIT_POS (60)
+
+#define DPI_MIN_CMD_SIZE 8
+#define DPI_MAX_CMD_SIZE 64
+
+/**
+ * Structure dpi_instr_hdr_s for CN9K
+ *
+ * DPI DMA Instruction Header Format
+ */
+union dpi_instr_hdr_s {
+ uint64_t u[4];
+ struct dpi_dma_instr_hdr_s_s {
+ uint64_t tag : 32;
+ uint64_t tt : 2;
+ uint64_t grp : 10;
+ uint64_t reserved_44_47 : 4;
+ uint64_t nfst : 4;
+ uint64_t reserved_52_53 : 2;
+ uint64_t nlst : 4;
+ uint64_t reserved_58_63 : 6;
+ /* Word 0 - End */
+ uint64_t aura : 20;
+ uint64_t func : 16;
+ uint64_t pt : 2;
+ uint64_t reserved_102 : 1;
+ uint64_t pvfe : 1;
+ uint64_t fl : 1;
+ uint64_t ii : 1;
+ uint64_t fi : 1;
+ uint64_t ca : 1;
+ uint64_t csel : 1;
+ uint64_t reserved_109_111 : 3;
+ uint64_t xtype : 2;
+ uint64_t reserved_114_119 : 6;
+ uint64_t fport : 2;
+ uint64_t reserved_122_123 : 2;
+ uint64_t lport : 2;
+ uint64_t reserved_126_127 : 2;
+ /* Word 1 - End */
+ uint64_t ptr : 64;
+ /* Word 2 - End */
+ uint64_t reserved_192_255 : 64;
+ /* Word 3 - End */
+ } s;
+};
+
+/**
+ * Structure dpi_cn10k_instr_hdr_s for CN10K
+ *
+ * DPI DMA Instruction Header Format
+ */
+union dpi_cn10k_instr_hdr_s {
+ uint64_t u[4];
+ struct dpi_cn10k_dma_instr_hdr_s_s {
+ uint64_t nfst : 4;
+ uint64_t reserved_4_5 : 2;
+ uint64_t nlst : 4;
+ uint64_t reserved_10_11 : 2;
+ uint64_t pvfe : 1;
+ uint64_t reserved_13 : 1;
+ uint64_t func : 16;
+ uint64_t aura : 20;
+ uint64_t xtype : 2;
+ uint64_t reserved_52_53 : 2;
+ uint64_t pt : 2;
+ uint64_t fport : 2;
+ uint64_t reserved_58_59 : 2;
+ uint64_t lport : 2;
+ uint64_t reserved_62_63 : 2;
+ /* Word 0 - End */
+ uint64_t ptr : 64;
+ /* Word 1 - End */
+ uint64_t tag : 32;
+ uint64_t tt : 2;
+ uint64_t grp : 10;
+ uint64_t reserved_172_173 : 2;
+ uint64_t fl : 1;
+ uint64_t ii : 1;
+ uint64_t fi : 1;
+ uint64_t ca : 1;
+ uint64_t csel : 1;
+ uint64_t reserved_179_191 : 3;
+ /* Word 2 - End */
+ uint64_t reserved_192_255 : 64;
+ /* Word 3 - End */
+ } s;
+};
+
+#endif /*__DEV_DPI_HW_H__*/
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index d9871a6b45..d0aeb6b68c 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -19,6 +19,7 @@ sources = files(
'roc_cpt.c',
'roc_cpt_debug.c',
'roc_dev.c',
+ 'roc_dpi.c',
'roc_hash.c',
'roc_idev.c',
'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index b8f3667c6c..359d31327a 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -33,6 +33,7 @@
/* HW structure definition */
#include "hw/cpt.h"
+#include "hw/dpi.h"
#include "hw/nix.h"
#include "hw/npa.h"
#include "hw/npc.h"
@@ -86,6 +87,9 @@
#include "roc_ie_ot.h"
#include "roc_se.h"
+/* DPI */
+#include "roc_dpi.h"
+
/* HASH computation */
#include "roc_hash.h"
diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c
new file mode 100644
index 0000000000..97177777c3
--- /dev/null
+++ b/drivers/common/cnxk/roc_dpi.c
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <fcntl.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
+
+static inline int
+send_msg_to_pf(struct plt_pci_addr *pci_addr, const char *value, int size)
+{
+ char buf[255] = {0};
+ int res, fd;
+
+ res = snprintf(
+ buf, sizeof(buf), "/sys/bus/pci/devices/" PCI_PRI_FMT "/%s",
+ pci_addr->domain, pci_addr->bus, DPI_PF_DBDF_DEVICE & 0x7,
+ DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
+
+ if ((res < 0) || ((size_t)res > sizeof(buf)))
+ return -ERANGE;
+
+ fd = open(buf, O_WRONLY);
+ if (fd < 0)
+ return -EACCES;
+
+ res = write(fd, value, size);
+ close(fd);
+ if (res < 0)
+ return -EACCES;
+
+ return 0;
+}
+
+int
+roc_dpi_enable(struct roc_dpi *dpi)
+{
+ plt_write64(0x1, dpi->rbase + DPI_VDMA_EN);
+ return 0;
+}
+
+int
+roc_dpi_disable(struct roc_dpi *dpi)
+{
+ plt_write64(0x0, dpi->rbase + DPI_VDMA_EN);
+ return 0;
+}
+
+int
+roc_dpi_configure(struct roc_dpi *roc_dpi)
+{
+ struct plt_pci_device *pci_dev;
+ const struct plt_memzone *dpi_mz;
+ dpi_mbox_msg_t mbox_msg;
+ struct npa_pool_s pool;
+ struct npa_aura_s aura;
+ int rc, count, buflen;
+ uint64_t aura_handle;
+ plt_iova_t iova;
+ char name[32];
+
+ if (!roc_dpi) {
+ plt_err("roc_dpi is NULL");
+ return -EINVAL;
+ }
+
+ pci_dev = roc_dpi->pci_dev;
+ memset(&pool, 0, sizeof(struct npa_pool_s));
+ pool.nat_align = 1;
+
+ memset(&aura, 0, sizeof(aura));
+ rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE,
+ DPI_CMD_QUEUE_BUFS, &aura, &pool);
+ if (rc) {
+ plt_err("Failed to create NPA pool, err %d\n", rc);
+ return rc;
+ }
+
+ snprintf(name, sizeof(name), "dpimem%d", roc_dpi->vfid);
+ buflen = DPI_CMD_QUEUE_SIZE * DPI_CMD_QUEUE_BUFS;
+ dpi_mz = plt_memzone_reserve_aligned(name, buflen, 0,
+ DPI_CMD_QUEUE_SIZE);
+ if (dpi_mz == NULL) {
+ plt_err("dpi memzone reserve failed");
+ rc = -ENOMEM;
+ goto err1;
+ }
+
+ roc_dpi->mz = dpi_mz;
+ iova = dpi_mz->iova;
+ for (count = 0; count < DPI_CMD_QUEUE_BUFS; count++) {
+ roc_npa_aura_op_free(aura_handle, 0, iova);
+ iova += DPI_CMD_QUEUE_SIZE;
+ }
+
+ roc_dpi->chunk_base = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
+ if (!roc_dpi->chunk_base) {
+ plt_err("Failed to alloc buffer from NPA aura");
+ rc = -ENOMEM;
+ goto err2;
+ }
+
+ roc_dpi->chunk_next = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
+ if (!roc_dpi->chunk_next) {
+ plt_err("Failed to alloc buffer from NPA aura");
+ rc = -ENOMEM;
+ goto err2;
+ }
+
+ roc_dpi->aura_handle = aura_handle;
+ /* subtract 2 as they have already been alloc'ed above */
+ roc_dpi->pool_size_m1 = (DPI_CMD_QUEUE_SIZE >> 3) - 2;
+
+ plt_write64(0x0, roc_dpi->rbase + DPI_VDMA_REQQ_CTL);
+ plt_write64(((uint64_t)(roc_dpi->chunk_base) >> 7) << 7,
+ roc_dpi->rbase + DPI_VDMA_SADDR);
+ mbox_msg.u[0] = 0;
+ mbox_msg.u[1] = 0;
+ /* DPI PF driver expects vfid starts from index 0 */
+ mbox_msg.s.vfid = roc_dpi->vfid;
+ mbox_msg.s.cmd = DPI_QUEUE_OPEN;
+ mbox_msg.s.csize = DPI_CMD_QUEUE_SIZE;
+ mbox_msg.s.aura = roc_npa_aura_handle_to_aura(aura_handle);
+ mbox_msg.s.sso_pf_func = idev_sso_pffunc_get();
+ mbox_msg.s.npa_pf_func = idev_npa_pffunc_get();
+
+ rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
+ sizeof(dpi_mbox_msg_t));
+ if (rc < 0) {
+ plt_err("Failed to send mbox message %d to DPI PF, err %d",
+ mbox_msg.s.cmd, rc);
+ goto err2;
+ }
+
+ return rc;
+
+err2:
+ roc_npa_pool_destroy(aura_handle);
+err1:
+ plt_memzone_free(dpi_mz);
+ return rc;
+}
+
+int
+roc_dpi_dev_init(struct roc_dpi *roc_dpi)
+{
+ struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
+ uint16_t vfid;
+
+ roc_dpi->rbase = pci_dev->mem_resource[0].addr;
+ vfid = ((pci_dev->addr.devid & 0x1F) << 3) |
+ (pci_dev->addr.function & 0x7);
+ vfid -= 1;
+ roc_dpi->vfid = vfid;
+ plt_spinlock_init(&roc_dpi->chunk_lock);
+
+ return 0;
+}
+
+int
+roc_dpi_dev_fini(struct roc_dpi *roc_dpi)
+{
+ struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
+ dpi_mbox_msg_t mbox_msg;
+ uint64_t reg;
+ int rc;
+
+ /* Wait for SADDR to become idle */
+ reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
+ while (!(reg & BIT_ULL(63)))
+ reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
+
+ mbox_msg.u[0] = 0;
+ mbox_msg.u[1] = 0;
+ mbox_msg.s.vfid = roc_dpi->vfid;
+ mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
+
+ rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
+ sizeof(dpi_mbox_msg_t));
+ if (rc < 0)
+ plt_err("Failed to send mbox message %d to DPI PF, err %d",
+ mbox_msg.s.cmd, rc);
+
+ roc_npa_pool_destroy(roc_dpi->aura_handle);
+ plt_memzone_free(roc_dpi->mz);
+
+ return rc;
+}
diff --git a/drivers/common/cnxk/roc_dpi.h b/drivers/common/cnxk/roc_dpi.h
new file mode 100644
index 0000000000..2f061b07c5
--- /dev/null
+++ b/drivers/common/cnxk/roc_dpi.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_DPI_H_
+#define _ROC_DPI_H_
+
+struct roc_dpi_args {
+ uint8_t num_ssegs;
+ uint8_t num_dsegs;
+ uint8_t comp_type;
+ uint8_t direction;
+ uint8_t sdevice;
+ uint8_t ddevice;
+ uint8_t swap;
+ uint8_t use_lock : 1;
+ uint8_t tt : 7;
+ uint16_t func;
+ uint16_t grp;
+ uint32_t tag;
+ uint64_t comp_ptr;
+};
+
+struct roc_dpi {
+ /* Input parameters */
+ struct plt_pci_device *pci_dev;
+ /* End of Input parameters */
+ const struct plt_memzone *mz;
+ uint8_t *rbase;
+ uint16_t vfid;
+ uint16_t pool_size_m1;
+ uint16_t chunk_head;
+ uint64_t *chunk_base;
+ uint64_t *chunk_next;
+ uint64_t aura_handle;
+ plt_spinlock_t chunk_lock;
+} __plt_cache_aligned;
+
+int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi);
+int __roc_api roc_dpi_dev_fini(struct roc_dpi *roc_dpi);
+
+int __roc_api roc_dpi_configure(struct roc_dpi *dpi);
+int __roc_api roc_dpi_enable(struct roc_dpi *dpi);
+int __roc_api roc_dpi_disable(struct roc_dpi *dpi);
+
+#endif
diff --git a/drivers/common/cnxk/roc_dpi_priv.h b/drivers/common/cnxk/roc_dpi_priv.h
new file mode 100644
index 0000000000..92953fbcfc
--- /dev/null
+++ b/drivers/common/cnxk/roc_dpi_priv.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_DPI_PRIV_H_
+#define _ROC_DPI_PRIV_H_
+
+#define DPI_MAX_VFS 8
+
+/* DPI PF DBDF information macros */
+#define DPI_PF_DBDF_DEVICE 0
+#define DPI_PF_DBDF_FUNCTION 0
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+
+#define DPI_CMD_QUEUE_SIZE 4096
+#define DPI_CMD_QUEUE_BUFS 1024
+
+typedef union dpi_mbox_msg_t {
+ uint64_t u[2];
+ struct dpi_mbox_message_s {
+ /* VF ID to configure */
+ uint64_t vfid : 4;
+ /* Command code */
+ uint64_t cmd : 4;
+ /* Command buffer size in 8-byte words */
+ uint64_t csize : 14;
+ /* aura of the command buffer */
+ uint64_t aura : 20;
+ /* SSO PF function */
+ uint64_t sso_pf_func : 16;
+ /* NPA PF function */
+ uint64_t npa_pf_func : 16;
+ } s;
+} dpi_mbox_msg_t;
+
+#endif
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 5da23fe5f8..61d4781209 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -69,6 +69,7 @@
#define __roc_api __rte_internal
#define plt_iova_t rte_iova_t
+#define plt_pci_addr rte_pci_addr
#define plt_pci_device rte_pci_device
#define plt_pci_read_config rte_pci_read_config
#define plt_pci_find_ext_capability rte_pci_find_ext_capability
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index f72bbd568f..782b90cf8d 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -41,4 +41,7 @@
/* NIX Inline dev */
#include "roc_nix_inl_priv.h"
+/* DPI */
+#include "roc_dpi_priv.h"
+
#endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 8d4d42f476..56e8ea5501 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -68,6 +68,11 @@ INTERNAL {
roc_cpt_lmtline_init;
roc_cpt_parse_hdr_dump;
roc_cpt_rxc_time_cfg;
+ roc_dpi_dev_init;
+ roc_dpi_dev_fini;
+ roc_dpi_configure;
+ roc_dpi_enable;
+ roc_dpi_disable;
roc_error_msg_get;
roc_hash_sha1_gen;
roc_hash_sha256_gen;
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH v2 2/4] dma/cnxk: create and initialize dmadev on pci probe
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 " Radha Mohan Chintakuntla
@ 2021-11-02 3:40 ` Radha Mohan Chintakuntla
2021-11-02 4:02 ` Jerin Jacob
2021-11-02 11:49 ` fengchengwen
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 3/4] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
` (3 subsequent siblings)
4 siblings, 2 replies; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-11-02 3:40 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
This patch creates and initializes a dmadev device on pci probe.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
MAINTAINERS | 6 ++
doc/guides/dmadevs/cnxk.rst | 58 +++++++++++++++++++
doc/guides/dmadevs/index.rst | 1 +
drivers/dma/cnxk/cnxk_dmadev.c | 100 +++++++++++++++++++++++++++++++++
drivers/dma/cnxk/cnxk_dmadev.h | 11 ++++
drivers/dma/cnxk/meson.build | 7 +++
drivers/dma/meson.build | 1 +
7 files changed, 184 insertions(+)
create mode 100644 doc/guides/dmadevs/cnxk.rst
create mode 100644 drivers/dma/cnxk/cnxk_dmadev.c
create mode 100644 drivers/dma/cnxk/cnxk_dmadev.h
create mode 100644 drivers/dma/cnxk/meson.build
diff --git a/MAINTAINERS b/MAINTAINERS
index be2c9b6815..60560a6a3b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1202,6 +1202,12 @@ M: Conor Walsh <conor.walsh@intel.com>
F: drivers/dma/ioat/
F: doc/guides/dmadevs/ioat.rst
+Marvell CNXK DPI DMA
+M: Radha Mohan Chintakuntla <radhac@marvell.com>
+M: Veerasenareddy Burru <vburru@marvell.com>
+F: drivers/dma/cnxk/
+F: doc/guides/dmadevs/cnxk.rst
+
RegEx Drivers
-------------
diff --git a/doc/guides/dmadevs/cnxk.rst b/doc/guides/dmadevs/cnxk.rst
new file mode 100644
index 0000000000..b29bd59a01
--- /dev/null
+++ b/doc/guides/dmadevs/cnxk.rst
@@ -0,0 +1,58 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2021 Marvell International Ltd.
+
+.. include:: <isonum.txt>
+
+CNXK DMA Device Driver
+======================
+
+The ``cnxk`` dmadev driver provides a poll-mode driver (PMD) for Marvell DPI DMA
+Hardware Accelerator block found in OCTEONTX2 and OCTEONTX3 family of SoCs. Each
+DMA queue is exposed as a VF function when SRIOV is enabled.
+
+The block supports following modes of DMA transfers
+
+#. Internal - DMA within SoC DRAM to DRAM
+
+#. Inbound - Host DRAM to SoC DRAM when SoC is in PCIe Endpoint
+
+#. Outbound - SoC DRAM to Host DRAM when SoC is in PCIe Endpoint
+
+Prerequisites and Compilation procedure
+---------------------------------------
+
+ See :doc:`../platform/cnxk` for setup information.
+
+Device Setup
+-------------
+The ``dpdk-devbind.py`` script, included with DPDK, can be used to show the
+presence of supported hardware. Running ``dpdk-devbind.py --status-dev dma``
+will show all the CNXK DMA devices.
+
+Devices using VFIO drivers
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The HW devices to be used will need to be bound to a user-space IO driver for use.
+The ``dpdk-devbind.py`` script can be used to view the state of the devices
+and to bind them to a suitable DPDK-supported driver, such as ``vfio-pci``.
+For example::
+
+ $ dpdk-devbind.py -b vfio-pci 0000:05:00.1
+
+Device Probing and Initialization
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To use the devices from an application, the dmadev API can be used.
+CNXK DMA device configuration requirements:
+
+* Only one ``vchan`` is supported per device.
+* CNXK DMA devices do not support silent mode.
+
+Once configured, the device can then be made ready for use by calling the
+ ``rte_dma_start()`` API.
+
+Performing Data Copies
+~~~~~~~~~~~~~~~~~~~~~~~
+
+Refer to the :ref:`Enqueue / Dequeue APIs <dmadev_enqueue_dequeue>` section of the dmadev library
+documentation for details on operation enqueue and submission API usage.
diff --git a/doc/guides/dmadevs/index.rst b/doc/guides/dmadevs/index.rst
index 20476039a5..227fa00c68 100644
--- a/doc/guides/dmadevs/index.rst
+++ b/doc/guides/dmadevs/index.rst
@@ -11,5 +11,6 @@ an application through DMA API.
:maxdepth: 2
:numbered:
+ cnxk
idxd
ioat
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
new file mode 100644
index 0000000000..268482677d
--- /dev/null
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2021 Marvell International Ltd.
+ */
+
+#include <string.h>
+#include <unistd.h>
+
+#include <rte_bus.h>
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_eal.h>
+#include <rte_lcore.h>
+#include <rte_mempool.h>
+#include <rte_pci.h>
+#include <rte_dmadev.h>
+#include <rte_dmadev_pmd.h>
+
+#include <roc_api.h>
+#include <cnxk_dmadev.h>
+
+static int
+cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
+ struct rte_pci_device *pci_dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = NULL;
+ char name[RTE_DEV_NAME_MAX_LEN];
+ struct rte_dma_dev *dmadev;
+ struct roc_dpi *rdpi = NULL;
+ int rc;
+
+ if (!pci_dev->mem_resource[0].addr)
+ return -ENODEV;
+
+ rc = roc_plt_init();
+ if (rc) {
+ plt_err("Failed to initialize platform model, rc=%d", rc);
+ return rc;
+ }
+ memset(name, 0, sizeof(name));
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+ dmadev = rte_dma_pmd_allocate(name, pci_dev->device.numa_node,
+ sizeof(*dpivf));
+ if (dmadev == NULL) {
+ plt_err("dma device allocation failed for %s", name);
+ return -ENOMEM;
+ }
+
+ dpivf = dmadev->data->dev_private;
+
+ dmadev->device = &pci_dev->device;
+ dmadev->fp_obj->dev_private = dpivf;
+
+ rdpi = &dpivf->rdpi;
+
+ rdpi->pci_dev = pci_dev;
+ rc = roc_dpi_dev_init(rdpi);
+ if (rc < 0)
+ goto err_out_free;
+
+ return 0;
+
+err_out_free:
+ if (dmadev)
+ rte_dma_pmd_release(name);
+
+ return rc;
+}
+
+static int
+cnxk_dmadev_remove(struct rte_pci_device *pci_dev)
+{
+ char name[RTE_DEV_NAME_MAX_LEN];
+
+ memset(name, 0, sizeof(name));
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+ return rte_dma_pmd_release(name);
+}
+
+static const struct rte_pci_id cnxk_dma_pci_map[] = {
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVID_CNXK_DPI_VF)
+ },
+ {
+ .vendor_id = 0,
+ },
+};
+
+static struct rte_pci_driver cnxk_dmadev = {
+ .id_table = cnxk_dma_pci_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+ .probe = cnxk_dmadev_probe,
+ .remove = cnxk_dmadev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(cnxk_dmadev_pci_driver, cnxk_dmadev);
+RTE_PMD_REGISTER_PCI_TABLE(cnxk_dmadev_pci_driver, cnxk_dma_pci_map);
+RTE_PMD_REGISTER_KMOD_DEP(cnxk_dmadev_pci_driver, "vfio-pci");
diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
new file mode 100644
index 0000000000..9e0bb7b2ce
--- /dev/null
+++ b/drivers/dma/cnxk/cnxk_dmadev.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+#ifndef _CNXK_DMADEV_H_
+#define _CNXK_DMADEV_H_
+
+struct cnxk_dpi_vf_s {
+ struct roc_dpi rdpi;
+};
+
+#endif
diff --git a/drivers/dma/cnxk/meson.build b/drivers/dma/cnxk/meson.build
new file mode 100644
index 0000000000..9489d6e6dc
--- /dev/null
+++ b/drivers/dma/cnxk/meson.build
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2021 Marvell International Ltd.
+#
+
+deps += ['bus_pci', 'common_cnxk', 'dmadev']
+sources = files('cnxk_dmadev.c')
+headers = files('cnxk_dmadev.h')
diff --git a/drivers/dma/meson.build b/drivers/dma/meson.build
index a69418ce9b..c562c8b429 100644
--- a/drivers/dma/meson.build
+++ b/drivers/dma/meson.build
@@ -2,6 +2,7 @@
# Copyright 2021 HiSilicon Limited
drivers = [
+ 'cnxk',
'idxd',
'ioat',
'skeleton',
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH v2 3/4] dma/cnxk: add dma channel operations
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 " Radha Mohan Chintakuntla
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
@ 2021-11-02 3:40 ` Radha Mohan Chintakuntla
2021-11-02 11:59 ` fengchengwen
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 4/4] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
` (2 subsequent siblings)
4 siblings, 1 reply; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-11-02 3:40 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
Add functions for the dmadev vchan setup and DMA operations.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
drivers/dma/cnxk/cnxk_dmadev.c | 322 +++++++++++++++++++++++++++++++++
drivers/dma/cnxk/cnxk_dmadev.h | 31 ++++
drivers/dma/cnxk/version.map | 3 +
3 files changed, 356 insertions(+)
create mode 100644 drivers/dma/cnxk/version.map
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
index 268482677d..9ecd254b76 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.c
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -18,6 +18,322 @@
#include <roc_api.h>
#include <cnxk_dmadev.h>
+static int
+cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
+ struct rte_dma_info *dev_info, uint32_t size)
+{
+ RTE_SET_USED(dev);
+ RTE_SET_USED(size);
+
+ dev_info->max_vchans = 1;
+ dev_info->nb_vchans = 1;
+ dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
+ RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
+ RTE_DMA_CAPA_OPS_COPY;
+ dev_info->max_desc = DPI_MAX_DESC;
+ dev_info->min_desc = 1;
+ dev_info->max_sges = DPI_MAX_POINTER;
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_configure(struct rte_dma_dev *dev,
+ const struct rte_dma_conf *conf, uint32_t conf_sz)
+{
+ struct cnxk_dpi_vf_s *dpivf = NULL;
+ int rc = 0;
+
+ RTE_SET_USED(conf);
+ RTE_SET_USED(conf);
+ RTE_SET_USED(conf_sz);
+ RTE_SET_USED(conf_sz);
+ dpivf = dev->fp_obj->dev_private;
+ rc = roc_dpi_configure(&dpivf->rdpi);
+ if (rc < 0)
+ plt_err("DMA configure failed err = %d", rc);
+
+ return rc;
+}
+
+static int
+cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
+ const struct rte_dma_vchan_conf *conf,
+ uint32_t conf_sz)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+ struct cnxk_dpi_compl_s *comp_data;
+ union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
+ int i;
+
+ RTE_SET_USED(vchan);
+ RTE_SET_USED(conf_sz);
+
+ header->s.pt = DPI_HDR_PT_ZBW_CA;
+
+ switch (conf->direction) {
+ case RTE_DMA_DIR_DEV_TO_MEM:
+ header->s.xtype = DPI_XTYPE_INBOUND;
+ header->s.lport = conf->src_port.pcie.coreid;
+ header->s.fport = 0;
+ header->s.pvfe = 1;
+ break;
+ case RTE_DMA_DIR_MEM_TO_DEV:
+ header->s.xtype = DPI_XTYPE_OUTBOUND;
+ header->s.lport = 0;
+ header->s.fport = conf->dst_port.pcie.coreid;
+ header->s.pvfe = 1;
+ break;
+ case RTE_DMA_DIR_MEM_TO_MEM:
+ header->s.xtype = DPI_XTYPE_INTERNAL_ONLY;
+ header->s.lport = 0;
+ header->s.fport = 0;
+ header->s.pvfe = 0;
+ break;
+ case RTE_DMA_DIR_DEV_TO_DEV:
+ header->s.xtype = DPI_XTYPE_EXTERNAL_ONLY;
+ header->s.lport = conf->src_port.pcie.coreid;
+ header->s.fport = conf->dst_port.pcie.coreid;
+ };
+
+ for (i = 0; i < conf->nb_desc; i++) {
+ comp_data = rte_zmalloc(NULL, sizeof(*comp_data), 0);
+ dpivf->conf.c_desc.compl_ptr[i] = comp_data;
+ };
+ dpivf->conf.c_desc.max_cnt = DPI_MAX_DESC;
+ dpivf->conf.c_desc.head = 0;
+ dpivf->conf.c_desc.tail = 0;
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_start(struct rte_dma_dev *dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+
+ roc_dpi_enable(&dpivf->rdpi);
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_stop(struct rte_dma_dev *dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+
+ roc_dpi_disable(&dpivf->rdpi);
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_close(struct rte_dma_dev *dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+
+ roc_dpi_disable(&dpivf->rdpi);
+ roc_dpi_dev_fini(&dpivf->rdpi);
+
+ return 0;
+}
+
+static inline int
+__dpi_queue_write(struct roc_dpi *dpi, uint64_t *cmds, int cmd_count)
+{
+ uint64_t *ptr = dpi->chunk_base;
+
+ if ((cmd_count < DPI_MIN_CMD_SIZE) || (cmd_count > DPI_MAX_CMD_SIZE) ||
+ cmds == NULL)
+ return -EINVAL;
+
+ /*
+ * Normally there is plenty of room in the current buffer for the
+ * command
+ */
+ if (dpi->chunk_head + cmd_count < dpi->pool_size_m1) {
+ ptr += dpi->chunk_head;
+ dpi->chunk_head += cmd_count;
+ while (cmd_count--)
+ *ptr++ = *cmds++;
+ } else {
+ int count;
+ uint64_t *new_buff = dpi->chunk_next;
+
+ dpi->chunk_next =
+ (void *)roc_npa_aura_op_alloc(dpi->aura_handle, 0);
+ if (!dpi->chunk_next) {
+ plt_err("Failed to alloc next buffer from NPA");
+ return -ENOMEM;
+ }
+
+ /*
+ * Figure out how many cmd words will fit in this buffer.
+ * One location will be needed for the next buffer pointer.
+ */
+ count = dpi->pool_size_m1 - dpi->chunk_head;
+ ptr += dpi->chunk_head;
+ cmd_count -= count;
+ while (count--)
+ *ptr++ = *cmds++;
+
+ /*
+ * chunk next ptr is 2 DWORDS
+ * second DWORD is reserved.
+ */
+ *ptr++ = (uint64_t)new_buff;
+ *ptr = 0;
+
+ /*
+ * The current buffer is full and has a link to the next
+ * buffers. Time to write the rest of the commands into the new
+ * buffer.
+ */
+ dpi->chunk_base = new_buff;
+ dpi->chunk_head = cmd_count;
+ ptr = new_buff;
+ while (cmd_count--)
+ *ptr++ = *cmds++;
+
+ /* queue index may be greater than pool size */
+ if (dpi->chunk_head >= dpi->pool_size_m1) {
+ new_buff = dpi->chunk_next;
+ dpi->chunk_next =
+ (void *)roc_npa_aura_op_alloc(dpi->aura_handle,
+ 0);
+ if (!dpi->chunk_next) {
+ plt_err("Failed to alloc next buffer from NPA");
+ return -ENOMEM;
+ }
+ /* Write next buffer address */
+ *ptr = (uint64_t)new_buff;
+ dpi->chunk_base = new_buff;
+ dpi->chunk_head = 0;
+ }
+ }
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
+ rte_iova_t dst, uint32_t length, uint64_t flags)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
+ struct cnxk_dpi_compl_s *comp_ptr;
+ rte_iova_t fptr, lptr;
+ int num_words = 0;
+ int rc;
+
+ RTE_SET_USED(vchan);
+
+ comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
+ comp_ptr->cdata = DPI_REQ_CDATA;
+ header->s.ptr = (uint64_t)comp_ptr;
+ STRM_INC(dpivf->conf.c_desc);
+
+ header->s.nfst = 1;
+ header->s.nlst = 1;
+
+ /*
+ * For inbound case, src pointers are last pointers.
+ * For all other cases, src pointers are first pointers.
+ */
+ if (header->s.xtype == DPI_XTYPE_INBOUND) {
+ fptr = dst;
+ lptr = src;
+ } else {
+ fptr = src;
+ lptr = dst;
+ }
+
+ dpivf->cmd[0] = header->u[0];
+ dpivf->cmd[1] = header->u[1];
+ dpivf->cmd[2] = header->u[2];
+ /* word3 is always 0 */
+ num_words += 4;
+ dpivf->cmd[num_words++] = length;
+ dpivf->cmd[num_words++] = fptr;
+ dpivf->cmd[num_words++] = length;
+ dpivf->cmd[num_words++] = lptr;
+
+ rc = __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words);
+ if (!rc) {
+ if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
+ rte_wmb();
+ plt_write64(num_words,
+ dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+ }
+ dpivf->num_words = num_words;
+ }
+
+ return rc;
+}
+
+static uint16_t
+cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
+ uint16_t *last_idx, bool *has_error)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ int cnt;
+
+ RTE_SET_USED(vchan);
+ RTE_SET_USED(last_idx);
+ RTE_SET_USED(has_error);
+ for (cnt = 0; cnt < nb_cpls; cnt++) {
+ struct cnxk_dpi_compl_s *comp_ptr =
+ dpivf->conf.c_desc.compl_ptr[cnt];
+
+ if (comp_ptr->cdata)
+ break;
+ }
+
+ dpivf->conf.c_desc.tail = cnt;
+
+ return cnt;
+}
+
+static uint16_t
+cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan,
+ const uint16_t nb_cpls, uint16_t *last_idx,
+ enum rte_dma_status_code *status)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ int cnt;
+
+ RTE_SET_USED(vchan);
+ RTE_SET_USED(last_idx);
+ for (cnt = 0; cnt < nb_cpls; cnt++) {
+ struct cnxk_dpi_compl_s *comp_ptr =
+ dpivf->conf.c_desc.compl_ptr[cnt];
+ status[cnt] = comp_ptr->cdata;
+ }
+
+ dpivf->conf.c_desc.tail = 0;
+ return cnt;
+}
+
+static int
+cnxk_dmadev_submit(void *dev_private, uint16_t vchan __rte_unused)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+
+ rte_wmb();
+ plt_write64(dpivf->num_words, dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+
+ return 0;
+}
+
+static const struct rte_dma_dev_ops cnxk_dmadev_ops = {
+ .dev_info_get = cnxk_dmadev_info_get,
+ .dev_configure = cnxk_dmadev_configure,
+ .dev_start = cnxk_dmadev_start,
+ .dev_stop = cnxk_dmadev_stop,
+ .vchan_setup = cnxk_dmadev_vchan_setup,
+ .dev_close = cnxk_dmadev_close,
+};
+
static int
cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
struct rte_pci_device *pci_dev)
@@ -50,6 +366,12 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
dmadev->device = &pci_dev->device;
dmadev->fp_obj->dev_private = dpivf;
+ dmadev->dev_ops = &cnxk_dmadev_ops;
+
+ dmadev->fp_obj->copy = cnxk_dmadev_copy;
+ dmadev->fp_obj->submit = cnxk_dmadev_submit;
+ dmadev->fp_obj->completed = cnxk_dmadev_completed;
+ dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
rdpi = &dpivf->rdpi;
diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
index 9e0bb7b2ce..efb09af03e 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.h
+++ b/drivers/dma/cnxk/cnxk_dmadev.h
@@ -4,8 +4,39 @@
#ifndef _CNXK_DMADEV_H_
#define _CNXK_DMADEV_H_
+#define DPI_MAX_POINTER 15
+#define DPI_QUEUE_STOP 0x0
+#define DPI_QUEUE_START 0x1
+#define STRM_INC(s) ((s).tail = ((s).tail + 1) % (s).max_cnt)
+#define DPI_MAX_DESC DPI_MAX_POINTER
+
+/* Set Completion data to 0xFF when request submitted,
+ * upon successful request completion engine reset to completion status
+ */
+#define DPI_REQ_CDATA 0xFF
+
+struct cnxk_dpi_compl_s {
+ uint64_t cdata;
+ void *cb_data;
+};
+
+struct cnxk_dpi_cdesc_data_s {
+ struct cnxk_dpi_compl_s *compl_ptr[DPI_MAX_DESC];
+ uint16_t max_cnt;
+ uint16_t head;
+ uint16_t tail;
+};
+
+struct cnxk_dpi_conf {
+ union dpi_instr_hdr_s hdr;
+ struct cnxk_dpi_cdesc_data_s c_desc;
+};
+
struct cnxk_dpi_vf_s {
struct roc_dpi rdpi;
+ struct cnxk_dpi_conf conf;
+ uint64_t cmd[DPI_MAX_CMD_SIZE];
+ uint32_t num_words;
};
#endif
diff --git a/drivers/dma/cnxk/version.map b/drivers/dma/cnxk/version.map
new file mode 100644
index 0000000000..4a76d1d52d
--- /dev/null
+++ b/drivers/dma/cnxk/version.map
@@ -0,0 +1,3 @@
+DPDK_21 {
+ local: *;
+};
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH v2 4/4] dma/cnxk: add copy_sg function
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 " Radha Mohan Chintakuntla
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 3/4] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
@ 2021-11-02 3:40 ` Radha Mohan Chintakuntla
2021-11-02 12:02 ` fengchengwen
2021-11-02 11:45 ` [dpdk-dev] [PATCH v2 1/4] common/cnxk: add DPI DMA support fengchengwen
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 1/5] " Radha Mohan Chintakuntla
4 siblings, 1 reply; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-11-02 3:40 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
Add the copy_sg function that will do the multiple DMA transfers of
different sizes and different source/destination as well.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
drivers/dma/cnxk/cnxk_dmadev.c | 68 +++++++++++++++++++++++++++++++++-
1 file changed, 67 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
index 9ecd254b76..359e00287f 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.c
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -29,7 +29,7 @@ cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
dev_info->nb_vchans = 1;
dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
- RTE_DMA_CAPA_OPS_COPY;
+ RTE_DMA_CAPA_OPS_COPY | RTE_DMA_CAPA_OPS_COPY_SG;
dev_info->max_desc = DPI_MAX_DESC;
dev_info->min_desc = 1;
dev_info->max_sges = DPI_MAX_POINTER;
@@ -271,6 +271,71 @@ cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
return rc;
}
+static int
+cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan,
+ const struct rte_dma_sge *src,
+ const struct rte_dma_sge *dst,
+ uint16_t nb_src, uint16_t nb_dst, uint64_t flags)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
+ const struct rte_dma_sge *fptr, *lptr;
+ struct cnxk_dpi_compl_s *comp_ptr;
+ int num_words = 0;
+ int i, rc;
+
+ RTE_SET_USED(vchan);
+
+ comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
+ comp_ptr->cdata = DPI_REQ_CDATA;
+ header->s.ptr = (uint64_t)comp_ptr;
+ STRM_INC(dpivf->conf.c_desc);
+
+ /*
+ * For inbound case, src pointers are last pointers.
+ * For all other cases, src pointers are first pointers.
+ */
+ if (header->s.xtype == DPI_XTYPE_INBOUND) {
+ header->s.nfst = nb_dst & 0xf;
+ header->s.nlst = nb_src & 0xf;
+ fptr = &dst[0];
+ lptr = &src[0];
+ } else {
+ header->s.nfst = nb_src & 0xf;
+ header->s.nlst = nb_dst & 0xf;
+ fptr = &src[0];
+ lptr = &dst[0];
+ }
+
+ dpivf->cmd[0] = header->u[0];
+ dpivf->cmd[1] = header->u[1];
+ dpivf->cmd[2] = header->u[2];
+ num_words += 4;
+ for (i = 0; i < header->s.nfst; i++) {
+ dpivf->cmd[num_words++] = (uint64_t)fptr->length;
+ dpivf->cmd[num_words++] = fptr->addr;
+ fptr++;
+ }
+
+ for (i = 0; i < header->s.nlst; i++) {
+ dpivf->cmd[num_words++] = (uint64_t)lptr->length;
+ dpivf->cmd[num_words++] = lptr->addr;
+ lptr++;
+ }
+
+ rc = __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words);
+ if (!rc) {
+ if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
+ rte_wmb();
+ plt_write64(num_words,
+ dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+ }
+ dpivf->num_words = num_words;
+ }
+
+ return rc;
+}
+
static uint16_t
cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
uint16_t *last_idx, bool *has_error)
@@ -369,6 +434,7 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
dmadev->dev_ops = &cnxk_dmadev_ops;
dmadev->fp_obj->copy = cnxk_dmadev_copy;
+ dmadev->fp_obj->copy_sg = cnxk_dmadev_copy_sg;
dmadev->fp_obj->submit = cnxk_dmadev_submit;
dmadev->fp_obj->completed = cnxk_dmadev_completed;
dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH v2 2/4] dma/cnxk: create and initialize dmadev on pci probe
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
@ 2021-11-02 4:02 ` Jerin Jacob
2021-11-02 11:49 ` fengchengwen
1 sibling, 0 replies; 32+ messages in thread
From: Jerin Jacob @ 2021-11-02 4:02 UTC (permalink / raw)
To: Radha Mohan Chintakuntla
Cc: Thomas Monjalon, fengchengwen, Nithin Dabilpuram, Kiran Kumar K,
Sunil Kumar Kori, Satha Koteswara Rao Kottidi, Jerin Jacob,
Satananda Burla, dpdk-dev
On Tue, Nov 2, 2021 at 9:10 AM Radha Mohan Chintakuntla
<radhac@marvell.com> wrote:
>
> This patch creates and initializes a dmadev device on pci probe.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
> MAINTAINERS | 6 ++
> doc/guides/dmadevs/cnxk.rst | 58 +++++++++++++++++++
> doc/guides/dmadevs/index.rst | 1 +
> drivers/dma/cnxk/cnxk_dmadev.c | 100 +++++++++++++++++++++++++++++++++
> drivers/dma/cnxk/cnxk_dmadev.h | 11 ++++
> drivers/dma/cnxk/meson.build | 7 +++
> drivers/dma/meson.build | 1 +
> 7 files changed, 184 insertions(+)
> create mode 100644 doc/guides/dmadevs/cnxk.rst
> create mode 100644 drivers/dma/cnxk/cnxk_dmadev.c
> create mode 100644 drivers/dma/cnxk/cnxk_dmadev.h
> create mode 100644 drivers/dma/cnxk/meson.build
>
Please update doc/guides/platform/cnxk.rst and update following sections
1) "_table_cnxk_rvu_dpdk_mapping"
2) "HW Offload Drivers"
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH v2 1/4] common/cnxk: add DPI DMA support
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 " Radha Mohan Chintakuntla
` (2 preceding siblings ...)
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 4/4] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
@ 2021-11-02 11:45 ` fengchengwen
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 1/5] " Radha Mohan Chintakuntla
4 siblings, 0 replies; 32+ messages in thread
From: fengchengwen @ 2021-11-02 11:45 UTC (permalink / raw)
To: Radha Mohan Chintakuntla, thomas, ndabilpuram, kirankumark,
skori, skoteshwar, jerinj, sburla
Cc: dev
On 2021/11/2 11:40, Radha Mohan Chintakuntla wrote:
> Add base support as ROC(Rest of Chip) API which will be used by PMD
> dmadev driver.
>
> This patch adds routines to init, fini, configure the DPI DMA device
> found in Marvell's CN9k or CN10k SoC families.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
...
> --- /dev/null
> +++ b/drivers/common/cnxk/hw/dpi.h
> @@ -0,0 +1,141 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +/**
> + * DPI device HW definitions.
> + */
> +#ifndef __DEV_DPI_HW_H__
> +#define __DEV_DPI_HW_H__
suggest remove __ to avoid conflict with gcc reserved symbol.
...
> +
> +int
> +roc_dpi_configure(struct roc_dpi *roc_dpi)
> +{
> + struct plt_pci_device *pci_dev;
> + const struct plt_memzone *dpi_mz;
> + dpi_mbox_msg_t mbox_msg;
> + struct npa_pool_s pool;
> + struct npa_aura_s aura;
> + int rc, count, buflen;
> + uint64_t aura_handle;
> + plt_iova_t iova;
> + char name[32];
> +
> + if (!roc_dpi) {
> + plt_err("roc_dpi is NULL");
> + return -EINVAL;
> + }
> +
> + pci_dev = roc_dpi->pci_dev;
> + memset(&pool, 0, sizeof(struct npa_pool_s));
> + pool.nat_align = 1;
> +
> + memset(&aura, 0, sizeof(aura));
> + rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE,
> + DPI_CMD_QUEUE_BUFS, &aura, &pool);
> + if (rc) {
> + plt_err("Failed to create NPA pool, err %d\n", rc);
> + return rc;
> + }
> +
> + snprintf(name, sizeof(name), "dpimem%d", roc_dpi->vfid);
> + buflen = DPI_CMD_QUEUE_SIZE * DPI_CMD_QUEUE_BUFS;
> + dpi_mz = plt_memzone_reserve_aligned(name, buflen, 0,
> + DPI_CMD_QUEUE_SIZE);
> + if (dpi_mz == NULL) {
> + plt_err("dpi memzone reserve failed");
> + rc = -ENOMEM;
> + goto err1;
currently, err1 will free dpi_mz which is NULL,
it should invoke roc_npa_pool_destroy instead.
> + }
> +
> + roc_dpi->mz = dpi_mz;
> + iova = dpi_mz->iova;
> + for (count = 0; count < DPI_CMD_QUEUE_BUFS; count++) {
> + roc_npa_aura_op_free(aura_handle, 0, iova);
> + iova += DPI_CMD_QUEUE_SIZE;
> + }
> +
> + roc_dpi->chunk_base = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
> + if (!roc_dpi->chunk_base) {
> + plt_err("Failed to alloc buffer from NPA aura");
> + rc = -ENOMEM;
> + goto err2;
> + }
> +
> + roc_dpi->chunk_next = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
> + if (!roc_dpi->chunk_next) {
> + plt_err("Failed to alloc buffer from NPA aura");
> + rc = -ENOMEM;
> + goto err2;
> + }
> +
> + roc_dpi->aura_handle = aura_handle;
> + /* subtract 2 as they have already been alloc'ed above */
> + roc_dpi->pool_size_m1 = (DPI_CMD_QUEUE_SIZE >> 3) - 2;
> +
> + plt_write64(0x0, roc_dpi->rbase + DPI_VDMA_REQQ_CTL);
> + plt_write64(((uint64_t)(roc_dpi->chunk_base) >> 7) << 7,
> + roc_dpi->rbase + DPI_VDMA_SADDR);
> + mbox_msg.u[0] = 0;
> + mbox_msg.u[1] = 0;
> + /* DPI PF driver expects vfid starts from index 0 */
> + mbox_msg.s.vfid = roc_dpi->vfid;
> + mbox_msg.s.cmd = DPI_QUEUE_OPEN;
> + mbox_msg.s.csize = DPI_CMD_QUEUE_SIZE;
> + mbox_msg.s.aura = roc_npa_aura_handle_to_aura(aura_handle);
> + mbox_msg.s.sso_pf_func = idev_sso_pffunc_get();
> + mbox_msg.s.npa_pf_func = idev_npa_pffunc_get();
> +
> + rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
> + sizeof(dpi_mbox_msg_t));
> + if (rc < 0) {
> + plt_err("Failed to send mbox message %d to DPI PF, err %d",
> + mbox_msg.s.cmd, rc);
> + goto err2;
> + }
> +
> + return rc;
> +
> +err2:
> + roc_npa_pool_destroy(aura_handle);
> +err1:
> + plt_memzone_free(dpi_mz);
> + return rc;
> +}
> +
...
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH v2 2/4] dma/cnxk: create and initialize dmadev on pci probe
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
2021-11-02 4:02 ` Jerin Jacob
@ 2021-11-02 11:49 ` fengchengwen
1 sibling, 0 replies; 32+ messages in thread
From: fengchengwen @ 2021-11-02 11:49 UTC (permalink / raw)
To: Radha Mohan Chintakuntla, thomas, ndabilpuram, kirankumark,
skori, skoteshwar, jerinj, sburla
Cc: dev
On 2021/11/2 11:40, Radha Mohan Chintakuntla wrote:
> This patch creates and initializes a dmadev device on pci probe.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
...
> +RTE_PMD_REGISTER_PCI(cnxk_dmadev_pci_driver, cnxk_dmadev);
> +RTE_PMD_REGISTER_PCI_TABLE(cnxk_dmadev_pci_driver, cnxk_dma_pci_map);
> +RTE_PMD_REGISTER_KMOD_DEP(cnxk_dmadev_pci_driver, "vfio-pci");
> diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
> new file mode 100644
> index 0000000000..9e0bb7b2ce
> --- /dev/null
> +++ b/drivers/dma/cnxk/cnxk_dmadev.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell International Ltd.
> + */
> +#ifndef _CNXK_DMADEV_H_
> +#define _CNXK_DMADEV_H_
suggest remove underline
> +
> +struct cnxk_dpi_vf_s {
> + struct roc_dpi rdpi;
> +};
> +
> +#endif
> diff --git a/drivers/dma/cnxk/meson.build b/drivers/dma/cnxk/meson.build
> new file mode 100644
> index 0000000000..9489d6e6dc
> --- /dev/null
> +++ b/drivers/dma/cnxk/meson.build
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(C) 2021 Marvell International Ltd.
> +#
> +
> +deps += ['bus_pci', 'common_cnxk', 'dmadev']
> +sources = files('cnxk_dmadev.c')
> +headers = files('cnxk_dmadev.h')
> diff --git a/drivers/dma/meson.build b/drivers/dma/meson.build
> index a69418ce9b..c562c8b429 100644
> --- a/drivers/dma/meson.build
> +++ b/drivers/dma/meson.build
> @@ -2,6 +2,7 @@
> # Copyright 2021 HiSilicon Limited
>
> drivers = [
> + 'cnxk',
> 'idxd',
> 'ioat',
> 'skeleton',
>
Acked-by: Chengwen Feng <fengchengwen@huawei.com>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH v2 3/4] dma/cnxk: add dma channel operations
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 3/4] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
@ 2021-11-02 11:59 ` fengchengwen
2021-11-02 18:11 ` Radha Mohan
0 siblings, 1 reply; 32+ messages in thread
From: fengchengwen @ 2021-11-02 11:59 UTC (permalink / raw)
To: Radha Mohan Chintakuntla, thomas, ndabilpuram, kirankumark,
skori, skoteshwar, jerinj, sburla
Cc: dev
On 2021/11/2 11:40, Radha Mohan Chintakuntla wrote:
> Add functions for the dmadev vchan setup and DMA operations.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
...
>
> +static int
> +cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
> + struct rte_dma_info *dev_info, uint32_t size)
> +{
> + RTE_SET_USED(dev);
> + RTE_SET_USED(size);
> +
> + dev_info->max_vchans = 1;
> + dev_info->nb_vchans = 1;
> + dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
> + RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
> + RTE_DMA_CAPA_OPS_COPY;
> + dev_info->max_desc = DPI_MAX_DESC;
> + dev_info->min_desc = 1;
> + dev_info->max_sges = DPI_MAX_POINTER;
> +
> + return 0;
> +}
> +
> +static int
> +cnxk_dmadev_configure(struct rte_dma_dev *dev,
> + const struct rte_dma_conf *conf, uint32_t conf_sz)
> +{
> + struct cnxk_dpi_vf_s *dpivf = NULL;
> + int rc = 0;
> +
> + RTE_SET_USED(conf);
> + RTE_SET_USED(conf);
> + RTE_SET_USED(conf_sz);
> + RTE_SET_USED(conf_sz);
> + dpivf = dev->fp_obj->dev_private;
> + rc = roc_dpi_configure(&dpivf->rdpi);
> + if (rc < 0)
> + plt_err("DMA configure failed err = %d", rc);
> +
> + return rc;
> +}
> +
> +static int
> +cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
> + const struct rte_dma_vchan_conf *conf,
> + uint32_t conf_sz)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> + struct cnxk_dpi_compl_s *comp_data;
> + union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
> + int i;
> +
> + RTE_SET_USED(vchan);
> + RTE_SET_USED(conf_sz);
> +
> + header->s.pt = DPI_HDR_PT_ZBW_CA;
> +
> + switch (conf->direction) {
> + case RTE_DMA_DIR_DEV_TO_MEM:
> + header->s.xtype = DPI_XTYPE_INBOUND;
> + header->s.lport = conf->src_port.pcie.coreid;
> + header->s.fport = 0;
> + header->s.pvfe = 1;
> + break;
> + case RTE_DMA_DIR_MEM_TO_DEV:
> + header->s.xtype = DPI_XTYPE_OUTBOUND;
> + header->s.lport = 0;
> + header->s.fport = conf->dst_port.pcie.coreid;
> + header->s.pvfe = 1;
> + break;
> + case RTE_DMA_DIR_MEM_TO_MEM:
> + header->s.xtype = DPI_XTYPE_INTERNAL_ONLY;
> + header->s.lport = 0;
> + header->s.fport = 0;
> + header->s.pvfe = 0;
> + break;
> + case RTE_DMA_DIR_DEV_TO_DEV:
> + header->s.xtype = DPI_XTYPE_EXTERNAL_ONLY;
> + header->s.lport = conf->src_port.pcie.coreid;
> + header->s.fport = conf->dst_port.pcie.coreid;
capability don't declare support DEV_TO_DEV, and framework will ensure
not pass DEV_TO_DEV direction. so this code could remove...
> + };
> +
> + for (i = 0; i < conf->nb_desc; i++) {
> + comp_data = rte_zmalloc(NULL, sizeof(*comp_data), 0);
why not check comp_data's validation ?
> + dpivf->conf.c_desc.compl_ptr[i] = comp_data;
> + };
> + dpivf->conf.c_desc.max_cnt = DPI_MAX_DESC;
> + dpivf->conf.c_desc.head = 0;
> + dpivf->conf.c_desc.tail = 0;
> +
> + return 0;
> +}
> +
> +static int
> +cnxk_dmadev_start(struct rte_dma_dev *dev)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> +
> + roc_dpi_enable(&dpivf->rdpi);
> +
> + return 0;
> +}
> +
> +static int
> +cnxk_dmadev_stop(struct rte_dma_dev *dev)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> +
> + roc_dpi_disable(&dpivf->rdpi);
> +
> + return 0;
> +}
> +
> +static int
> +cnxk_dmadev_close(struct rte_dma_dev *dev)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> +
> + roc_dpi_disable(&dpivf->rdpi);
> + roc_dpi_dev_fini(&dpivf->rdpi);
> +
> + return 0;
> +}
> +
> +static inline int
> +__dpi_queue_write(struct roc_dpi *dpi, uint64_t *cmds, int cmd_count)
> +{
> + uint64_t *ptr = dpi->chunk_base;
> +
> + if ((cmd_count < DPI_MIN_CMD_SIZE) || (cmd_count > DPI_MAX_CMD_SIZE) ||
> + cmds == NULL)
> + return -EINVAL;
> +
> + /*
> + * Normally there is plenty of room in the current buffer for the
> + * command
> + */
> + if (dpi->chunk_head + cmd_count < dpi->pool_size_m1) {
> + ptr += dpi->chunk_head;
> + dpi->chunk_head += cmd_count;
> + while (cmd_count--)
> + *ptr++ = *cmds++;
> + } else {
> + int count;
> + uint64_t *new_buff = dpi->chunk_next;
> +
> + dpi->chunk_next =
> + (void *)roc_npa_aura_op_alloc(dpi->aura_handle, 0);
> + if (!dpi->chunk_next) {
> + plt_err("Failed to alloc next buffer from NPA");
> + return -ENOMEM;
> + }
> +
> + /*
> + * Figure out how many cmd words will fit in this buffer.
> + * One location will be needed for the next buffer pointer.
> + */
> + count = dpi->pool_size_m1 - dpi->chunk_head;
> + ptr += dpi->chunk_head;
> + cmd_count -= count;
> + while (count--)
> + *ptr++ = *cmds++;
> +
> + /*
> + * chunk next ptr is 2 DWORDS
> + * second DWORD is reserved.
> + */
> + *ptr++ = (uint64_t)new_buff;
> + *ptr = 0;
> +
> + /*
> + * The current buffer is full and has a link to the next
> + * buffers. Time to write the rest of the commands into the new
> + * buffer.
> + */
> + dpi->chunk_base = new_buff;
> + dpi->chunk_head = cmd_count;
> + ptr = new_buff;
> + while (cmd_count--)
> + *ptr++ = *cmds++;
> +
> + /* queue index may be greater than pool size */
> + if (dpi->chunk_head >= dpi->pool_size_m1) {
> + new_buff = dpi->chunk_next;
> + dpi->chunk_next =
> + (void *)roc_npa_aura_op_alloc(dpi->aura_handle,
> + 0);
> + if (!dpi->chunk_next) {
> + plt_err("Failed to alloc next buffer from NPA");
> + return -ENOMEM;
> + }
> + /* Write next buffer address */
> + *ptr = (uint64_t)new_buff;
> + dpi->chunk_base = new_buff;
> + dpi->chunk_head = 0;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int
> +cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
> + rte_iova_t dst, uint32_t length, uint64_t flags)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev_private;
> + union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
> + struct cnxk_dpi_compl_s *comp_ptr;
> + rte_iova_t fptr, lptr;
> + int num_words = 0;
> + int rc;
> +
> + RTE_SET_USED(vchan);
> +
> + comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
> + comp_ptr->cdata = DPI_REQ_CDATA;
> + header->s.ptr = (uint64_t)comp_ptr;
> + STRM_INC(dpivf->conf.c_desc);
> +
> + header->s.nfst = 1;
> + header->s.nlst = 1;
> +
> + /*
> + * For inbound case, src pointers are last pointers.
> + * For all other cases, src pointers are first pointers.
> + */
> + if (header->s.xtype == DPI_XTYPE_INBOUND) {
> + fptr = dst;
> + lptr = src;
> + } else {
> + fptr = src;
> + lptr = dst;
> + }
> +
> + dpivf->cmd[0] = header->u[0];
> + dpivf->cmd[1] = header->u[1];
> + dpivf->cmd[2] = header->u[2];
> + /* word3 is always 0 */
> + num_words += 4;
> + dpivf->cmd[num_words++] = length;
> + dpivf->cmd[num_words++] = fptr;
> + dpivf->cmd[num_words++] = length;
> + dpivf->cmd[num_words++] = lptr;
> +
> + rc = __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words);
> + if (!rc) {
> + if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
> + rte_wmb();
> + plt_write64(num_words,
> + dpivf->rdpi.rbase + DPI_VDMA_DBELL);
> + }
> + dpivf->num_words = num_words;
> + }
> +
> + return rc;
I notice __dpi_queue_write will return 0 if success, but I should return the
index in the range of [0, 0xffff].
> +}
> +
> +static uint16_t
> +cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
> + uint16_t *last_idx, bool *has_error)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev_private;
> + int cnt;
> +
> + RTE_SET_USED(vchan);
> + RTE_SET_USED(last_idx);
> + RTE_SET_USED(has_error);
> + for (cnt = 0; cnt < nb_cpls; cnt++) {
> + struct cnxk_dpi_compl_s *comp_ptr =
> + dpivf->conf.c_desc.compl_ptr[cnt];
> +
> + if (comp_ptr->cdata)
this mean error, should set *has_error = true.
> + break;
> + }
> +
> + dpivf->conf.c_desc.tail = cnt;
and also return the last_idx which framework demands.
> +
> + return cnt;
> +}
> +
> +static uint16_t
> +cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan,
> + const uint16_t nb_cpls, uint16_t *last_idx,
> + enum rte_dma_status_code *status)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev_private;
> + int cnt;
> +
> + RTE_SET_USED(vchan);
> + RTE_SET_USED(last_idx);
> + for (cnt = 0; cnt < nb_cpls; cnt++) {
> + struct cnxk_dpi_compl_s *comp_ptr =
> + dpivf->conf.c_desc.compl_ptr[cnt];
> + status[cnt] = comp_ptr->cdata;
> + }
> +
> + dpivf->conf.c_desc.tail = 0;
return the last_idx which framework demands.
> + return cnt;
> +}
> +
> +static int
> +cnxk_dmadev_submit(void *dev_private, uint16_t vchan __rte_unused)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev_private;
> +
> + rte_wmb();
> + plt_write64(dpivf->num_words, dpivf->rdpi.rbase + DPI_VDMA_DBELL);
> +
> + return 0;
> +}
> +
> +static const struct rte_dma_dev_ops cnxk_dmadev_ops = {
> + .dev_info_get = cnxk_dmadev_info_get,
> + .dev_configure = cnxk_dmadev_configure,
> + .dev_start = cnxk_dmadev_start,
> + .dev_stop = cnxk_dmadev_stop,
> + .vchan_setup = cnxk_dmadev_vchan_setup,
> + .dev_close = cnxk_dmadev_close,
> +};
> +
> static int
> cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
> struct rte_pci_device *pci_dev)
> @@ -50,6 +366,12 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
>
> dmadev->device = &pci_dev->device;
> dmadev->fp_obj->dev_private = dpivf;
> + dmadev->dev_ops = &cnxk_dmadev_ops;
> +
> + dmadev->fp_obj->copy = cnxk_dmadev_copy;
> + dmadev->fp_obj->submit = cnxk_dmadev_submit;
> + dmadev->fp_obj->completed = cnxk_dmadev_completed;
> + dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
>
> rdpi = &dpivf->rdpi;
>
> diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
> index 9e0bb7b2ce..efb09af03e 100644
> --- a/drivers/dma/cnxk/cnxk_dmadev.h
> +++ b/drivers/dma/cnxk/cnxk_dmadev.h
> @@ -4,8 +4,39 @@
> #ifndef _CNXK_DMADEV_H_
> #define _CNXK_DMADEV_H_
>
> +#define DPI_MAX_POINTER 15
> +#define DPI_QUEUE_STOP 0x0
> +#define DPI_QUEUE_START 0x1
> +#define STRM_INC(s) ((s).tail = ((s).tail + 1) % (s).max_cnt)
> +#define DPI_MAX_DESC DPI_MAX_POINTER
> +
> +/* Set Completion data to 0xFF when request submitted,
> + * upon successful request completion engine reset to completion status
> + */
> +#define DPI_REQ_CDATA 0xFF
> +
> +struct cnxk_dpi_compl_s {
> + uint64_t cdata;
> + void *cb_data;
> +};
> +
> +struct cnxk_dpi_cdesc_data_s {
> + struct cnxk_dpi_compl_s *compl_ptr[DPI_MAX_DESC];
> + uint16_t max_cnt;
> + uint16_t head;
> + uint16_t tail;
> +};
> +
> +struct cnxk_dpi_conf {
> + union dpi_instr_hdr_s hdr;
> + struct cnxk_dpi_cdesc_data_s c_desc;
> +};
> +
> struct cnxk_dpi_vf_s {
> struct roc_dpi rdpi;
> + struct cnxk_dpi_conf conf;
> + uint64_t cmd[DPI_MAX_CMD_SIZE];
> + uint32_t num_words;
> };
>
> #endif
> diff --git a/drivers/dma/cnxk/version.map b/drivers/dma/cnxk/version.map
> new file mode 100644
> index 0000000000..4a76d1d52d
> --- /dev/null
> +++ b/drivers/dma/cnxk/version.map
> @@ -0,0 +1,3 @@
> +DPDK_21 {
should be DPDK_22
> + local: *;
> +};
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH v2 4/4] dma/cnxk: add copy_sg function
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 4/4] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
@ 2021-11-02 12:02 ` fengchengwen
0 siblings, 0 replies; 32+ messages in thread
From: fengchengwen @ 2021-11-02 12:02 UTC (permalink / raw)
To: Radha Mohan Chintakuntla, thomas, ndabilpuram, kirankumark,
skori, skoteshwar, jerinj, sburla
Cc: dev
On 2021/11/2 11:40, Radha Mohan Chintakuntla wrote:
> Add the copy_sg function that will do the multiple DMA transfers of
> different sizes and different source/destination as well.
>
...
>
> +static int
> +cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan,
> + const struct rte_dma_sge *src,
> + const struct rte_dma_sge *dst,
> + uint16_t nb_src, uint16_t nb_dst, uint64_t flags)
> +{
> + struct cnxk_dpi_vf_s *dpivf = dev_private;
> + union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
> + const struct rte_dma_sge *fptr, *lptr;
> + struct cnxk_dpi_compl_s *comp_ptr;
> + int num_words = 0;
> + int i, rc;
> +
> + RTE_SET_USED(vchan);
> +
> + comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
> + comp_ptr->cdata = DPI_REQ_CDATA;
> + header->s.ptr = (uint64_t)comp_ptr;
> + STRM_INC(dpivf->conf.c_desc);
> +
> + /*
> + * For inbound case, src pointers are last pointers.
> + * For all other cases, src pointers are first pointers.
> + */
> + if (header->s.xtype == DPI_XTYPE_INBOUND) {
> + header->s.nfst = nb_dst & 0xf;
> + header->s.nlst = nb_src & 0xf;
> + fptr = &dst[0];
> + lptr = &src[0];
> + } else {
> + header->s.nfst = nb_src & 0xf;
> + header->s.nlst = nb_dst & 0xf;
> + fptr = &src[0];
> + lptr = &dst[0];
> + }
> +
> + dpivf->cmd[0] = header->u[0];
> + dpivf->cmd[1] = header->u[1];
> + dpivf->cmd[2] = header->u[2];
> + num_words += 4;
> + for (i = 0; i < header->s.nfst; i++) {
> + dpivf->cmd[num_words++] = (uint64_t)fptr->length;
> + dpivf->cmd[num_words++] = fptr->addr;
> + fptr++;
> + }
> +
> + for (i = 0; i < header->s.nlst; i++) {
> + dpivf->cmd[num_words++] = (uint64_t)lptr->length;
> + dpivf->cmd[num_words++] = lptr->addr;
> + lptr++;
> + }
> +
> + rc = __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words);
> + if (!rc) {
> + if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
> + rte_wmb();
> + plt_write64(num_words,
> + dpivf->rdpi.rbase + DPI_VDMA_DBELL);
> + }
> + dpivf->num_words = num_words;
> + }
> +
> + return rc;
should return ring index which in [0, 0xffff]
> +}
> +
> static uint16_t
> cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
> uint16_t *last_idx, bool *has_error)
> @@ -369,6 +434,7 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
> dmadev->dev_ops = &cnxk_dmadev_ops;
>
> dmadev->fp_obj->copy = cnxk_dmadev_copy;
> + dmadev->fp_obj->copy_sg = cnxk_dmadev_copy_sg;
> dmadev->fp_obj->submit = cnxk_dmadev_submit;
> dmadev->fp_obj->completed = cnxk_dmadev_completed;
> dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH v2 3/4] dma/cnxk: add dma channel operations
2021-11-02 11:59 ` fengchengwen
@ 2021-11-02 18:11 ` Radha Mohan
0 siblings, 0 replies; 32+ messages in thread
From: Radha Mohan @ 2021-11-02 18:11 UTC (permalink / raw)
To: fengchengwen
Cc: Radha Mohan Chintakuntla, Thomas Monjalon, Nithin Dabilpuram,
Kiran Kumar K, Sunil Kumar Kori, Satha Koteswara Rao Kottidi,
Jerin Jacob Kollanukkaran, Satananda Burla, dpdk-dev
On Tue, Nov 2, 2021 at 5:00 AM fengchengwen <fengchengwen@huawei.com> wrote:
>
> On 2021/11/2 11:40, Radha Mohan Chintakuntla wrote:
> > Add functions for the dmadev vchan setup and DMA operations.
> >
> > Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
>
> ...
>
> >
> > +static int
> > +cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
> > + struct rte_dma_info *dev_info, uint32_t size)
> > +{
> > + RTE_SET_USED(dev);
> > + RTE_SET_USED(size);
> > +
> > + dev_info->max_vchans = 1;
> > + dev_info->nb_vchans = 1;
> > + dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
> > + RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
> > + RTE_DMA_CAPA_OPS_COPY;
> > + dev_info->max_desc = DPI_MAX_DESC;
> > + dev_info->min_desc = 1;
> > + dev_info->max_sges = DPI_MAX_POINTER;
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +cnxk_dmadev_configure(struct rte_dma_dev *dev,
> > + const struct rte_dma_conf *conf, uint32_t conf_sz)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = NULL;
> > + int rc = 0;
> > +
> > + RTE_SET_USED(conf);
> > + RTE_SET_USED(conf);
> > + RTE_SET_USED(conf_sz);
> > + RTE_SET_USED(conf_sz);
> > + dpivf = dev->fp_obj->dev_private;
> > + rc = roc_dpi_configure(&dpivf->rdpi);
> > + if (rc < 0)
> > + plt_err("DMA configure failed err = %d", rc);
> > +
> > + return rc;
> > +}
> > +
> > +static int
> > +cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
> > + const struct rte_dma_vchan_conf *conf,
> > + uint32_t conf_sz)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
> > + struct cnxk_dpi_compl_s *comp_data;
> > + union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
> > + int i;
> > +
> > + RTE_SET_USED(vchan);
> > + RTE_SET_USED(conf_sz);
> > +
> > + header->s.pt = DPI_HDR_PT_ZBW_CA;
> > +
> > + switch (conf->direction) {
> > + case RTE_DMA_DIR_DEV_TO_MEM:
> > + header->s.xtype = DPI_XTYPE_INBOUND;
> > + header->s.lport = conf->src_port.pcie.coreid;
> > + header->s.fport = 0;
> > + header->s.pvfe = 1;
> > + break;
> > + case RTE_DMA_DIR_MEM_TO_DEV:
> > + header->s.xtype = DPI_XTYPE_OUTBOUND;
> > + header->s.lport = 0;
> > + header->s.fport = conf->dst_port.pcie.coreid;
> > + header->s.pvfe = 1;
> > + break;
> > + case RTE_DMA_DIR_MEM_TO_MEM:
> > + header->s.xtype = DPI_XTYPE_INTERNAL_ONLY;
> > + header->s.lport = 0;
> > + header->s.fport = 0;
> > + header->s.pvfe = 0;
> > + break;
> > + case RTE_DMA_DIR_DEV_TO_DEV:
> > + header->s.xtype = DPI_XTYPE_EXTERNAL_ONLY;
> > + header->s.lport = conf->src_port.pcie.coreid;
> > + header->s.fport = conf->dst_port.pcie.coreid;
>
> capability don't declare support DEV_TO_DEV, and framework will ensure
> not pass DEV_TO_DEV direction. so this code could remove...
I missed adding DEV_TO_DEV in capability. Thank you for pointing that out.
>
> > + };
> > +
> > + for (i = 0; i < conf->nb_desc; i++) {
> > + comp_data = rte_zmalloc(NULL, sizeof(*comp_data), 0);
>
> why not check comp_data's validation ?
Sure will add.
<snip>
> > +
> > +static int
> > +cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
> > + rte_iova_t dst, uint32_t length, uint64_t flags)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = dev_private;
> > + union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
> > + struct cnxk_dpi_compl_s *comp_ptr;
> > + rte_iova_t fptr, lptr;
> > + int num_words = 0;
> > + int rc;
> > +
> > + RTE_SET_USED(vchan);
> > +
> > + comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
> > + comp_ptr->cdata = DPI_REQ_CDATA;
> > + header->s.ptr = (uint64_t)comp_ptr;
> > + STRM_INC(dpivf->conf.c_desc);
> > +
> > + header->s.nfst = 1;
> > + header->s.nlst = 1;
> > +
> > + /*
> > + * For inbound case, src pointers are last pointers.
> > + * For all other cases, src pointers are first pointers.
> > + */
> > + if (header->s.xtype == DPI_XTYPE_INBOUND) {
> > + fptr = dst;
> > + lptr = src;
> > + } else {
> > + fptr = src;
> > + lptr = dst;
> > + }
> > +
> > + dpivf->cmd[0] = header->u[0];
> > + dpivf->cmd[1] = header->u[1];
> > + dpivf->cmd[2] = header->u[2];
> > + /* word3 is always 0 */
> > + num_words += 4;
> > + dpivf->cmd[num_words++] = length;
> > + dpivf->cmd[num_words++] = fptr;
> > + dpivf->cmd[num_words++] = length;
> > + dpivf->cmd[num_words++] = lptr;
> > +
> > + rc = __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words);
> > + if (!rc) {
> > + if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
> > + rte_wmb();
> > + plt_write64(num_words,
> > + dpivf->rdpi.rbase + DPI_VDMA_DBELL);
> > + }
> > + dpivf->num_words = num_words;
> > + }
> > +
> > + return rc;
>
> I notice __dpi_queue_write will return 0 if success, but I should return the
> index in the range of [0, 0xffff].
ack
>
> > +}
> > +
> > +static uint16_t
> > +cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
> > + uint16_t *last_idx, bool *has_error)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = dev_private;
> > + int cnt;
> > +
> > + RTE_SET_USED(vchan);
> > + RTE_SET_USED(last_idx);
> > + RTE_SET_USED(has_error);
> > + for (cnt = 0; cnt < nb_cpls; cnt++) {
> > + struct cnxk_dpi_compl_s *comp_ptr =
> > + dpivf->conf.c_desc.compl_ptr[cnt];
> > +
> > + if (comp_ptr->cdata)
>
> this mean error, should set *has_error = true.
>
> > + break;
> > + }
> > +
> > + dpivf->conf.c_desc.tail = cnt;
>
> and also return the last_idx which framework demands.
ack.
>
> > +
> > + return cnt;
> > +}
> > +
> > +static uint16_t
> > +cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan,
> > + const uint16_t nb_cpls, uint16_t *last_idx,
> > + enum rte_dma_status_code *status)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = dev_private;
> > + int cnt;
> > +
> > + RTE_SET_USED(vchan);
> > + RTE_SET_USED(last_idx);
> > + for (cnt = 0; cnt < nb_cpls; cnt++) {
> > + struct cnxk_dpi_compl_s *comp_ptr =
> > + dpivf->conf.c_desc.compl_ptr[cnt];
> > + status[cnt] = comp_ptr->cdata;
> > + }
> > +
> > + dpivf->conf.c_desc.tail = 0;
>
> return the last_idx which framework demands.
>
> > + return cnt;
> > +}
> > +
> > +static int
> > +cnxk_dmadev_submit(void *dev_private, uint16_t vchan __rte_unused)
> > +{
> > + struct cnxk_dpi_vf_s *dpivf = dev_private;
> > +
> > + rte_wmb();
> > + plt_write64(dpivf->num_words, dpivf->rdpi.rbase + DPI_VDMA_DBELL);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct rte_dma_dev_ops cnxk_dmadev_ops = {
> > + .dev_info_get = cnxk_dmadev_info_get,
> > + .dev_configure = cnxk_dmadev_configure,
> > + .dev_start = cnxk_dmadev_start,
> > + .dev_stop = cnxk_dmadev_stop,
> > + .vchan_setup = cnxk_dmadev_vchan_setup,
> > + .dev_close = cnxk_dmadev_close,
> > +};
> > +
> > static int
> > cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
> > struct rte_pci_device *pci_dev)
> > @@ -50,6 +366,12 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
> >
> > dmadev->device = &pci_dev->device;
> > dmadev->fp_obj->dev_private = dpivf;
> > + dmadev->dev_ops = &cnxk_dmadev_ops;
> > +
> > + dmadev->fp_obj->copy = cnxk_dmadev_copy;
> > + dmadev->fp_obj->submit = cnxk_dmadev_submit;
> > + dmadev->fp_obj->completed = cnxk_dmadev_completed;
> > + dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
> >
> > rdpi = &dpivf->rdpi;
> >
> > diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
> > index 9e0bb7b2ce..efb09af03e 100644
> > --- a/drivers/dma/cnxk/cnxk_dmadev.h
> > +++ b/drivers/dma/cnxk/cnxk_dmadev.h
> > @@ -4,8 +4,39 @@
> > #ifndef _CNXK_DMADEV_H_
> > #define _CNXK_DMADEV_H_
> >
> > +#define DPI_MAX_POINTER 15
> > +#define DPI_QUEUE_STOP 0x0
> > +#define DPI_QUEUE_START 0x1
> > +#define STRM_INC(s) ((s).tail = ((s).tail + 1) % (s).max_cnt)
> > +#define DPI_MAX_DESC DPI_MAX_POINTER
> > +
> > +/* Set Completion data to 0xFF when request submitted,
> > + * upon successful request completion engine reset to completion status
> > + */
> > +#define DPI_REQ_CDATA 0xFF
> > +
> > +struct cnxk_dpi_compl_s {
> > + uint64_t cdata;
> > + void *cb_data;
> > +};
> > +
> > +struct cnxk_dpi_cdesc_data_s {
> > + struct cnxk_dpi_compl_s *compl_ptr[DPI_MAX_DESC];
> > + uint16_t max_cnt;
> > + uint16_t head;
> > + uint16_t tail;
> > +};
> > +
> > +struct cnxk_dpi_conf {
> > + union dpi_instr_hdr_s hdr;
> > + struct cnxk_dpi_cdesc_data_s c_desc;
> > +};
> > +
> > struct cnxk_dpi_vf_s {
> > struct roc_dpi rdpi;
> > + struct cnxk_dpi_conf conf;
> > + uint64_t cmd[DPI_MAX_CMD_SIZE];
> > + uint32_t num_words;
> > };
> >
> > #endif
> > diff --git a/drivers/dma/cnxk/version.map b/drivers/dma/cnxk/version.map
> > new file mode 100644
> > index 0000000000..4a76d1d52d
> > --- /dev/null
> > +++ b/drivers/dma/cnxk/version.map
> > @@ -0,0 +1,3 @@
> > +DPDK_21 {
>
> should be DPDK_22
>
> > + local: *;
> > +};
> >
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH v3 1/5] common/cnxk: add DPI DMA support
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 " Radha Mohan Chintakuntla
` (3 preceding siblings ...)
2021-11-02 11:45 ` [dpdk-dev] [PATCH v2 1/4] common/cnxk: add DPI DMA support fengchengwen
@ 2021-11-03 18:01 ` Radha Mohan Chintakuntla
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
` (3 more replies)
4 siblings, 4 replies; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-11-03 18:01 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
Add base support as ROC(Rest of Chip) API which will be used by PMD
dmadev driver.
This patch adds routines to init, fini, configure the DPI DMA device
found in Marvell's CN9k or CN10k SoC families.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v2:
- added stats function
- update has_error when error condition happens
- return last_idx in the completed functions
Changes from v1:
- Changed to roc_dpi_enable() from roc_dpi_queue_start()
- Changed to roc_dpi_disable() from roc_dp_queue_stop()
- Moved part of DMA header preparation to vchan_setup() which can save
some CPU cycles in fastpath
drivers/common/cnxk/hw/dpi.h | 141 +++++++++++++++++++++
drivers/common/cnxk/meson.build | 1 +
drivers/common/cnxk/roc_api.h | 4 +
drivers/common/cnxk/roc_dpi.c | 193 +++++++++++++++++++++++++++++
drivers/common/cnxk/roc_dpi.h | 46 +++++++
drivers/common/cnxk/roc_dpi_priv.h | 40 ++++++
drivers/common/cnxk/roc_platform.h | 1 +
drivers/common/cnxk/roc_priv.h | 3 +
drivers/common/cnxk/version.map | 5 +
9 files changed, 434 insertions(+)
create mode 100644 drivers/common/cnxk/hw/dpi.h
create mode 100644 drivers/common/cnxk/roc_dpi.c
create mode 100644 drivers/common/cnxk/roc_dpi.h
create mode 100644 drivers/common/cnxk/roc_dpi_priv.h
diff --git a/drivers/common/cnxk/hw/dpi.h b/drivers/common/cnxk/hw/dpi.h
new file mode 100644
index 0000000000..2da123228f
--- /dev/null
+++ b/drivers/common/cnxk/hw/dpi.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+/**
+ * DPI device HW definitions.
+ */
+#ifndef DEV_DPI_HW_H
+#define DEV_DPI_HW_H
+
+#include <stdint.h>
+
+/* DPI VF register offsets from VF_BAR0 */
+#define DPI_VDMA_EN (0x0)
+#define DPI_VDMA_REQQ_CTL (0x8)
+#define DPI_VDMA_DBELL (0x10)
+#define DPI_VDMA_SADDR (0x18)
+#define DPI_VDMA_COUNTS (0x20)
+#define DPI_VDMA_NADDR (0x28)
+#define DPI_VDMA_IWBUSY (0x30)
+#define DPI_VDMA_CNT (0x38)
+#define DPI_VF_INT (0x100)
+#define DPI_VF_INT_W1S (0x108)
+#define DPI_VF_INT_ENA_W1C (0x110)
+#define DPI_VF_INT_ENA_W1S (0x118)
+
+/**
+ * Enumeration dpi_hdr_xtype_e
+ *
+ * DPI Transfer Type Enumeration
+ * Enumerates the pointer type in DPI_DMA_INSTR_HDR_S[XTYPE].
+ */
+#define DPI_XTYPE_OUTBOUND (0)
+#define DPI_XTYPE_INBOUND (1)
+#define DPI_XTYPE_INTERNAL_ONLY (2)
+#define DPI_XTYPE_EXTERNAL_ONLY (3)
+#define DPI_HDR_XTYPE_MASK 0x3
+
+#define DPI_HDR_PT_ZBW_CA 0x0
+#define DPI_HDR_PT_ZBW_NC 0x1
+#define DPI_HDR_PT_WQP 0x2
+#define DPI_HDR_PT_WQP_NOSTATUS 0x0
+#define DPI_HDR_PT_WQP_STATUSCA 0x1
+#define DPI_HDR_PT_WQP_STATUSNC 0x3
+#define DPI_HDR_PT_CNT 0x3
+#define DPI_HDR_PT_MASK 0x3
+
+#define DPI_HDR_TT_MASK 0x3
+#define DPI_HDR_GRP_MASK 0x3FF
+#define DPI_HDR_FUNC_MASK 0xFFFF
+
+/* Big endian data bit position in DMA local pointer */
+#define DPI_LPTR_BED_BIT_POS (60)
+
+#define DPI_MIN_CMD_SIZE 8
+#define DPI_MAX_CMD_SIZE 64
+
+/**
+ * Structure dpi_instr_hdr_s for CN9K
+ *
+ * DPI DMA Instruction Header Format
+ */
+union dpi_instr_hdr_s {
+ uint64_t u[4];
+ struct dpi_dma_instr_hdr_s_s {
+ uint64_t tag : 32;
+ uint64_t tt : 2;
+ uint64_t grp : 10;
+ uint64_t reserved_44_47 : 4;
+ uint64_t nfst : 4;
+ uint64_t reserved_52_53 : 2;
+ uint64_t nlst : 4;
+ uint64_t reserved_58_63 : 6;
+ /* Word 0 - End */
+ uint64_t aura : 20;
+ uint64_t func : 16;
+ uint64_t pt : 2;
+ uint64_t reserved_102 : 1;
+ uint64_t pvfe : 1;
+ uint64_t fl : 1;
+ uint64_t ii : 1;
+ uint64_t fi : 1;
+ uint64_t ca : 1;
+ uint64_t csel : 1;
+ uint64_t reserved_109_111 : 3;
+ uint64_t xtype : 2;
+ uint64_t reserved_114_119 : 6;
+ uint64_t fport : 2;
+ uint64_t reserved_122_123 : 2;
+ uint64_t lport : 2;
+ uint64_t reserved_126_127 : 2;
+ /* Word 1 - End */
+ uint64_t ptr : 64;
+ /* Word 2 - End */
+ uint64_t reserved_192_255 : 64;
+ /* Word 3 - End */
+ } s;
+};
+
+/**
+ * Structure dpi_cn10k_instr_hdr_s for CN10K
+ *
+ * DPI DMA Instruction Header Format
+ */
+union dpi_cn10k_instr_hdr_s {
+ uint64_t u[4];
+ struct dpi_cn10k_dma_instr_hdr_s_s {
+ uint64_t nfst : 4;
+ uint64_t reserved_4_5 : 2;
+ uint64_t nlst : 4;
+ uint64_t reserved_10_11 : 2;
+ uint64_t pvfe : 1;
+ uint64_t reserved_13 : 1;
+ uint64_t func : 16;
+ uint64_t aura : 20;
+ uint64_t xtype : 2;
+ uint64_t reserved_52_53 : 2;
+ uint64_t pt : 2;
+ uint64_t fport : 2;
+ uint64_t reserved_58_59 : 2;
+ uint64_t lport : 2;
+ uint64_t reserved_62_63 : 2;
+ /* Word 0 - End */
+ uint64_t ptr : 64;
+ /* Word 1 - End */
+ uint64_t tag : 32;
+ uint64_t tt : 2;
+ uint64_t grp : 10;
+ uint64_t reserved_172_173 : 2;
+ uint64_t fl : 1;
+ uint64_t ii : 1;
+ uint64_t fi : 1;
+ uint64_t ca : 1;
+ uint64_t csel : 1;
+ uint64_t reserved_179_191 : 3;
+ /* Word 2 - End */
+ uint64_t reserved_192_255 : 64;
+ /* Word 3 - End */
+ } s;
+};
+
+#endif /*__DEV_DPI_HW_H__*/
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index d9871a6b45..d0aeb6b68c 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -19,6 +19,7 @@ sources = files(
'roc_cpt.c',
'roc_cpt_debug.c',
'roc_dev.c',
+ 'roc_dpi.c',
'roc_hash.c',
'roc_idev.c',
'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index b8f3667c6c..359d31327a 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -33,6 +33,7 @@
/* HW structure definition */
#include "hw/cpt.h"
+#include "hw/dpi.h"
#include "hw/nix.h"
#include "hw/npa.h"
#include "hw/npc.h"
@@ -86,6 +87,9 @@
#include "roc_ie_ot.h"
#include "roc_se.h"
+/* DPI */
+#include "roc_dpi.h"
+
/* HASH computation */
#include "roc_hash.h"
diff --git a/drivers/common/cnxk/roc_dpi.c b/drivers/common/cnxk/roc_dpi.c
new file mode 100644
index 0000000000..23b2cc41a4
--- /dev/null
+++ b/drivers/common/cnxk/roc_dpi.c
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <fcntl.h>
+#include <sys/stat.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
+
+static inline int
+send_msg_to_pf(struct plt_pci_addr *pci_addr, const char *value, int size)
+{
+ char buf[255] = {0};
+ int res, fd;
+
+ res = snprintf(
+ buf, sizeof(buf), "/sys/bus/pci/devices/" PCI_PRI_FMT "/%s",
+ pci_addr->domain, pci_addr->bus, DPI_PF_DBDF_DEVICE & 0x7,
+ DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
+
+ if ((res < 0) || ((size_t)res > sizeof(buf)))
+ return -ERANGE;
+
+ fd = open(buf, O_WRONLY);
+ if (fd < 0)
+ return -EACCES;
+
+ res = write(fd, value, size);
+ close(fd);
+ if (res < 0)
+ return -EACCES;
+
+ return 0;
+}
+
+int
+roc_dpi_enable(struct roc_dpi *dpi)
+{
+ plt_write64(0x1, dpi->rbase + DPI_VDMA_EN);
+ return 0;
+}
+
+int
+roc_dpi_disable(struct roc_dpi *dpi)
+{
+ plt_write64(0x0, dpi->rbase + DPI_VDMA_EN);
+ return 0;
+}
+
+int
+roc_dpi_configure(struct roc_dpi *roc_dpi)
+{
+ struct plt_pci_device *pci_dev;
+ const struct plt_memzone *dpi_mz;
+ dpi_mbox_msg_t mbox_msg;
+ struct npa_pool_s pool;
+ struct npa_aura_s aura;
+ int rc, count, buflen;
+ uint64_t aura_handle;
+ plt_iova_t iova;
+ char name[32];
+
+ if (!roc_dpi) {
+ plt_err("roc_dpi is NULL");
+ return -EINVAL;
+ }
+
+ pci_dev = roc_dpi->pci_dev;
+ memset(&pool, 0, sizeof(struct npa_pool_s));
+ pool.nat_align = 1;
+
+ memset(&aura, 0, sizeof(aura));
+ rc = roc_npa_pool_create(&aura_handle, DPI_CMD_QUEUE_SIZE,
+ DPI_CMD_QUEUE_BUFS, &aura, &pool);
+ if (rc) {
+ plt_err("Failed to create NPA pool, err %d\n", rc);
+ return rc;
+ }
+
+ snprintf(name, sizeof(name), "dpimem%d", roc_dpi->vfid);
+ buflen = DPI_CMD_QUEUE_SIZE * DPI_CMD_QUEUE_BUFS;
+ dpi_mz = plt_memzone_reserve_aligned(name, buflen, 0,
+ DPI_CMD_QUEUE_SIZE);
+ if (dpi_mz == NULL) {
+ plt_err("dpi memzone reserve failed");
+ rc = -ENOMEM;
+ goto err1;
+ }
+
+ roc_dpi->mz = dpi_mz;
+ iova = dpi_mz->iova;
+ for (count = 0; count < DPI_CMD_QUEUE_BUFS; count++) {
+ roc_npa_aura_op_free(aura_handle, 0, iova);
+ iova += DPI_CMD_QUEUE_SIZE;
+ }
+
+ roc_dpi->chunk_base = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
+ if (!roc_dpi->chunk_base) {
+ plt_err("Failed to alloc buffer from NPA aura");
+ rc = -ENOMEM;
+ goto err2;
+ }
+
+ roc_dpi->chunk_next = (void *)roc_npa_aura_op_alloc(aura_handle, 0);
+ if (!roc_dpi->chunk_next) {
+ plt_err("Failed to alloc buffer from NPA aura");
+ rc = -ENOMEM;
+ goto err2;
+ }
+
+ roc_dpi->aura_handle = aura_handle;
+ /* subtract 2 as they have already been alloc'ed above */
+ roc_dpi->pool_size_m1 = (DPI_CMD_QUEUE_SIZE >> 3) - 2;
+
+ plt_write64(0x0, roc_dpi->rbase + DPI_VDMA_REQQ_CTL);
+ plt_write64(((uint64_t)(roc_dpi->chunk_base) >> 7) << 7,
+ roc_dpi->rbase + DPI_VDMA_SADDR);
+ mbox_msg.u[0] = 0;
+ mbox_msg.u[1] = 0;
+ /* DPI PF driver expects vfid starts from index 0 */
+ mbox_msg.s.vfid = roc_dpi->vfid;
+ mbox_msg.s.cmd = DPI_QUEUE_OPEN;
+ mbox_msg.s.csize = DPI_CMD_QUEUE_SIZE;
+ mbox_msg.s.aura = roc_npa_aura_handle_to_aura(aura_handle);
+ mbox_msg.s.sso_pf_func = idev_sso_pffunc_get();
+ mbox_msg.s.npa_pf_func = idev_npa_pffunc_get();
+
+ rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
+ sizeof(dpi_mbox_msg_t));
+ if (rc < 0) {
+ plt_err("Failed to send mbox message %d to DPI PF, err %d",
+ mbox_msg.s.cmd, rc);
+ goto err2;
+ }
+
+ return rc;
+
+err2:
+ plt_memzone_free(dpi_mz);
+err1:
+ roc_npa_pool_destroy(aura_handle);
+ return rc;
+}
+
+int
+roc_dpi_dev_init(struct roc_dpi *roc_dpi)
+{
+ struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
+ uint16_t vfid;
+
+ roc_dpi->rbase = pci_dev->mem_resource[0].addr;
+ vfid = ((pci_dev->addr.devid & 0x1F) << 3) |
+ (pci_dev->addr.function & 0x7);
+ vfid -= 1;
+ roc_dpi->vfid = vfid;
+ plt_spinlock_init(&roc_dpi->chunk_lock);
+
+ return 0;
+}
+
+int
+roc_dpi_dev_fini(struct roc_dpi *roc_dpi)
+{
+ struct plt_pci_device *pci_dev = roc_dpi->pci_dev;
+ dpi_mbox_msg_t mbox_msg;
+ uint64_t reg;
+ int rc;
+
+ /* Wait for SADDR to become idle */
+ reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
+ while (!(reg & BIT_ULL(63)))
+ reg = plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR);
+
+ mbox_msg.u[0] = 0;
+ mbox_msg.u[1] = 0;
+ mbox_msg.s.vfid = roc_dpi->vfid;
+ mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
+
+ rc = send_msg_to_pf(&pci_dev->addr, (const char *)&mbox_msg,
+ sizeof(dpi_mbox_msg_t));
+ if (rc < 0)
+ plt_err("Failed to send mbox message %d to DPI PF, err %d",
+ mbox_msg.s.cmd, rc);
+
+ roc_npa_pool_destroy(roc_dpi->aura_handle);
+ plt_memzone_free(roc_dpi->mz);
+
+ return rc;
+}
diff --git a/drivers/common/cnxk/roc_dpi.h b/drivers/common/cnxk/roc_dpi.h
new file mode 100644
index 0000000000..2f061b07c5
--- /dev/null
+++ b/drivers/common/cnxk/roc_dpi.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_DPI_H_
+#define _ROC_DPI_H_
+
+struct roc_dpi_args {
+ uint8_t num_ssegs;
+ uint8_t num_dsegs;
+ uint8_t comp_type;
+ uint8_t direction;
+ uint8_t sdevice;
+ uint8_t ddevice;
+ uint8_t swap;
+ uint8_t use_lock : 1;
+ uint8_t tt : 7;
+ uint16_t func;
+ uint16_t grp;
+ uint32_t tag;
+ uint64_t comp_ptr;
+};
+
+struct roc_dpi {
+ /* Input parameters */
+ struct plt_pci_device *pci_dev;
+ /* End of Input parameters */
+ const struct plt_memzone *mz;
+ uint8_t *rbase;
+ uint16_t vfid;
+ uint16_t pool_size_m1;
+ uint16_t chunk_head;
+ uint64_t *chunk_base;
+ uint64_t *chunk_next;
+ uint64_t aura_handle;
+ plt_spinlock_t chunk_lock;
+} __plt_cache_aligned;
+
+int __roc_api roc_dpi_dev_init(struct roc_dpi *roc_dpi);
+int __roc_api roc_dpi_dev_fini(struct roc_dpi *roc_dpi);
+
+int __roc_api roc_dpi_configure(struct roc_dpi *dpi);
+int __roc_api roc_dpi_enable(struct roc_dpi *dpi);
+int __roc_api roc_dpi_disable(struct roc_dpi *dpi);
+
+#endif
diff --git a/drivers/common/cnxk/roc_dpi_priv.h b/drivers/common/cnxk/roc_dpi_priv.h
new file mode 100644
index 0000000000..92953fbcfc
--- /dev/null
+++ b/drivers/common/cnxk/roc_dpi_priv.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_DPI_PRIV_H_
+#define _ROC_DPI_PRIV_H_
+
+#define DPI_MAX_VFS 8
+
+/* DPI PF DBDF information macros */
+#define DPI_PF_DBDF_DEVICE 0
+#define DPI_PF_DBDF_FUNCTION 0
+
+#define DPI_QUEUE_OPEN 0x1
+#define DPI_QUEUE_CLOSE 0x2
+#define DPI_REG_DUMP 0x3
+#define DPI_GET_REG_CFG 0x4
+
+#define DPI_CMD_QUEUE_SIZE 4096
+#define DPI_CMD_QUEUE_BUFS 1024
+
+typedef union dpi_mbox_msg_t {
+ uint64_t u[2];
+ struct dpi_mbox_message_s {
+ /* VF ID to configure */
+ uint64_t vfid : 4;
+ /* Command code */
+ uint64_t cmd : 4;
+ /* Command buffer size in 8-byte words */
+ uint64_t csize : 14;
+ /* aura of the command buffer */
+ uint64_t aura : 20;
+ /* SSO PF function */
+ uint64_t sso_pf_func : 16;
+ /* NPA PF function */
+ uint64_t npa_pf_func : 16;
+ } s;
+} dpi_mbox_msg_t;
+
+#endif
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index 5da23fe5f8..61d4781209 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -69,6 +69,7 @@
#define __roc_api __rte_internal
#define plt_iova_t rte_iova_t
+#define plt_pci_addr rte_pci_addr
#define plt_pci_device rte_pci_device
#define plt_pci_read_config rte_pci_read_config
#define plt_pci_find_ext_capability rte_pci_find_ext_capability
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index f72bbd568f..782b90cf8d 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -41,4 +41,7 @@
/* NIX Inline dev */
#include "roc_nix_inl_priv.h"
+/* DPI */
+#include "roc_dpi_priv.h"
+
#endif /* _ROC_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 8d4d42f476..56e8ea5501 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -68,6 +68,11 @@ INTERNAL {
roc_cpt_lmtline_init;
roc_cpt_parse_hdr_dump;
roc_cpt_rxc_time_cfg;
+ roc_dpi_dev_init;
+ roc_dpi_dev_fini;
+ roc_dpi_configure;
+ roc_dpi_enable;
+ roc_dpi_disable;
roc_error_msg_get;
roc_hash_sha1_gen;
roc_hash_sha256_gen;
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 1/5] " Radha Mohan Chintakuntla
@ 2021-11-03 18:01 ` Radha Mohan Chintakuntla
2021-11-07 20:55 ` Thomas Monjalon
2021-11-07 23:04 ` Thomas Monjalon
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 3/5] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
` (2 subsequent siblings)
3 siblings, 2 replies; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-11-03 18:01 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
This patch creates and initializes a dmadev device on pci probe.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
MAINTAINERS | 6 ++
doc/guides/dmadevs/cnxk.rst | 58 +++++++++++++++++++
doc/guides/dmadevs/index.rst | 1 +
doc/guides/platform/cnxk.rst | 5 +-
drivers/dma/cnxk/cnxk_dmadev.c | 100 +++++++++++++++++++++++++++++++++
drivers/dma/cnxk/cnxk_dmadev.h | 11 ++++
drivers/dma/cnxk/meson.build | 7 +++
drivers/dma/meson.build | 1 +
8 files changed, 188 insertions(+), 1 deletion(-)
create mode 100644 doc/guides/dmadevs/cnxk.rst
create mode 100644 drivers/dma/cnxk/cnxk_dmadev.c
create mode 100644 drivers/dma/cnxk/cnxk_dmadev.h
create mode 100644 drivers/dma/cnxk/meson.build
diff --git a/MAINTAINERS b/MAINTAINERS
index be2c9b6815..60560a6a3b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1202,6 +1202,12 @@ M: Conor Walsh <conor.walsh@intel.com>
F: drivers/dma/ioat/
F: doc/guides/dmadevs/ioat.rst
+Marvell CNXK DPI DMA
+M: Radha Mohan Chintakuntla <radhac@marvell.com>
+M: Veerasenareddy Burru <vburru@marvell.com>
+F: drivers/dma/cnxk/
+F: doc/guides/dmadevs/cnxk.rst
+
RegEx Drivers
-------------
diff --git a/doc/guides/dmadevs/cnxk.rst b/doc/guides/dmadevs/cnxk.rst
new file mode 100644
index 0000000000..b29bd59a01
--- /dev/null
+++ b/doc/guides/dmadevs/cnxk.rst
@@ -0,0 +1,58 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+ Copyright(c) 2021 Marvell International Ltd.
+
+.. include:: <isonum.txt>
+
+CNXK DMA Device Driver
+======================
+
+The ``cnxk`` dmadev driver provides a poll-mode driver (PMD) for Marvell DPI DMA
+Hardware Accelerator block found in OCTEONTX2 and OCTEONTX3 family of SoCs. Each
+DMA queue is exposed as a VF function when SRIOV is enabled.
+
+The block supports following modes of DMA transfers
+
+#. Internal - DMA within SoC DRAM to DRAM
+
+#. Inbound - Host DRAM to SoC DRAM when SoC is in PCIe Endpoint
+
+#. Outbound - SoC DRAM to Host DRAM when SoC is in PCIe Endpoint
+
+Prerequisites and Compilation procedure
+---------------------------------------
+
+ See :doc:`../platform/cnxk` for setup information.
+
+Device Setup
+-------------
+The ``dpdk-devbind.py`` script, included with DPDK, can be used to show the
+presence of supported hardware. Running ``dpdk-devbind.py --status-dev dma``
+will show all the CNXK DMA devices.
+
+Devices using VFIO drivers
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The HW devices to be used will need to be bound to a user-space IO driver for use.
+The ``dpdk-devbind.py`` script can be used to view the state of the devices
+and to bind them to a suitable DPDK-supported driver, such as ``vfio-pci``.
+For example::
+
+ $ dpdk-devbind.py -b vfio-pci 0000:05:00.1
+
+Device Probing and Initialization
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To use the devices from an application, the dmadev API can be used.
+CNXK DMA device configuration requirements:
+
+* Only one ``vchan`` is supported per device.
+* CNXK DMA devices do not support silent mode.
+
+Once configured, the device can then be made ready for use by calling the
+ ``rte_dma_start()`` API.
+
+Performing Data Copies
+~~~~~~~~~~~~~~~~~~~~~~~
+
+Refer to the :ref:`Enqueue / Dequeue APIs <dmadev_enqueue_dequeue>` section of the dmadev library
+documentation for details on operation enqueue and submission API usage.
diff --git a/doc/guides/dmadevs/index.rst b/doc/guides/dmadevs/index.rst
index 20476039a5..227fa00c68 100644
--- a/doc/guides/dmadevs/index.rst
+++ b/doc/guides/dmadevs/index.rst
@@ -11,5 +11,6 @@ an application through DMA API.
:maxdepth: 2
:numbered:
+ cnxk
idxd
ioat
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index d7adf43165..770f5e846b 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -62,7 +62,7 @@ DPDK subsystem.
+---+-----+--------------------------------------------------------------+
| 7 | LBK | rte_ethdev |
+---+-----+--------------------------------------------------------------+
- | 8 | DPI | rte_rawdev |
+ | 8 | DPI | rte_dmadev |
+---+-----+--------------------------------------------------------------+
| 9 | SDP | rte_ethdev |
+---+-----+--------------------------------------------------------------+
@@ -151,6 +151,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
#. **Baseband PHY Driver**
See :doc:`../rawdevs/cnxk_bphy` for Baseband PHY driver information.
+#. **Dmadev Driver**
+ See :doc:`../dmadevs/cnxk` for DPI Dmadev driver information.
+
Procedure to Setup Platform
---------------------------
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
new file mode 100644
index 0000000000..268482677d
--- /dev/null
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2021 Marvell International Ltd.
+ */
+
+#include <string.h>
+#include <unistd.h>
+
+#include <rte_bus.h>
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_eal.h>
+#include <rte_lcore.h>
+#include <rte_mempool.h>
+#include <rte_pci.h>
+#include <rte_dmadev.h>
+#include <rte_dmadev_pmd.h>
+
+#include <roc_api.h>
+#include <cnxk_dmadev.h>
+
+static int
+cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
+ struct rte_pci_device *pci_dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = NULL;
+ char name[RTE_DEV_NAME_MAX_LEN];
+ struct rte_dma_dev *dmadev;
+ struct roc_dpi *rdpi = NULL;
+ int rc;
+
+ if (!pci_dev->mem_resource[0].addr)
+ return -ENODEV;
+
+ rc = roc_plt_init();
+ if (rc) {
+ plt_err("Failed to initialize platform model, rc=%d", rc);
+ return rc;
+ }
+ memset(name, 0, sizeof(name));
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+ dmadev = rte_dma_pmd_allocate(name, pci_dev->device.numa_node,
+ sizeof(*dpivf));
+ if (dmadev == NULL) {
+ plt_err("dma device allocation failed for %s", name);
+ return -ENOMEM;
+ }
+
+ dpivf = dmadev->data->dev_private;
+
+ dmadev->device = &pci_dev->device;
+ dmadev->fp_obj->dev_private = dpivf;
+
+ rdpi = &dpivf->rdpi;
+
+ rdpi->pci_dev = pci_dev;
+ rc = roc_dpi_dev_init(rdpi);
+ if (rc < 0)
+ goto err_out_free;
+
+ return 0;
+
+err_out_free:
+ if (dmadev)
+ rte_dma_pmd_release(name);
+
+ return rc;
+}
+
+static int
+cnxk_dmadev_remove(struct rte_pci_device *pci_dev)
+{
+ char name[RTE_DEV_NAME_MAX_LEN];
+
+ memset(name, 0, sizeof(name));
+ rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+ return rte_dma_pmd_release(name);
+}
+
+static const struct rte_pci_id cnxk_dma_pci_map[] = {
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVID_CNXK_DPI_VF)
+ },
+ {
+ .vendor_id = 0,
+ },
+};
+
+static struct rte_pci_driver cnxk_dmadev = {
+ .id_table = cnxk_dma_pci_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+ .probe = cnxk_dmadev_probe,
+ .remove = cnxk_dmadev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(cnxk_dmadev_pci_driver, cnxk_dmadev);
+RTE_PMD_REGISTER_PCI_TABLE(cnxk_dmadev_pci_driver, cnxk_dma_pci_map);
+RTE_PMD_REGISTER_KMOD_DEP(cnxk_dmadev_pci_driver, "vfio-pci");
diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
new file mode 100644
index 0000000000..f573e17bf6
--- /dev/null
+++ b/drivers/dma/cnxk/cnxk_dmadev.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+#ifndef CNXK_DMADEV_H
+#define CNXK_DMADEV_H
+
+struct cnxk_dpi_vf_s {
+ struct roc_dpi rdpi;
+};
+
+#endif
diff --git a/drivers/dma/cnxk/meson.build b/drivers/dma/cnxk/meson.build
new file mode 100644
index 0000000000..9489d6e6dc
--- /dev/null
+++ b/drivers/dma/cnxk/meson.build
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2021 Marvell International Ltd.
+#
+
+deps += ['bus_pci', 'common_cnxk', 'dmadev']
+sources = files('cnxk_dmadev.c')
+headers = files('cnxk_dmadev.h')
diff --git a/drivers/dma/meson.build b/drivers/dma/meson.build
index a69418ce9b..c562c8b429 100644
--- a/drivers/dma/meson.build
+++ b/drivers/dma/meson.build
@@ -2,6 +2,7 @@
# Copyright 2021 HiSilicon Limited
drivers = [
+ 'cnxk',
'idxd',
'ioat',
'skeleton',
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH v3 3/5] dma/cnxk: add dma channel operations
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 1/5] " Radha Mohan Chintakuntla
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
@ 2021-11-03 18:01 ` Radha Mohan Chintakuntla
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 4/5] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 5/5] dma/cnxk: add stats function Radha Mohan Chintakuntla
3 siblings, 0 replies; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-11-03 18:01 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
Add functions for the dmadev vchan setup and DMA operations.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
drivers/dma/cnxk/cnxk_dmadev.c | 331 +++++++++++++++++++++++++++++++++
drivers/dma/cnxk/cnxk_dmadev.h | 32 ++++
drivers/dma/cnxk/version.map | 3 +
3 files changed, 366 insertions(+)
create mode 100644 drivers/dma/cnxk/version.map
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
index 268482677d..1738129fa1 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.c
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -18,6 +18,331 @@
#include <roc_api.h>
#include <cnxk_dmadev.h>
+static int
+cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
+ struct rte_dma_info *dev_info, uint32_t size)
+{
+ RTE_SET_USED(dev);
+ RTE_SET_USED(size);
+
+ dev_info->max_vchans = 1;
+ dev_info->nb_vchans = 1;
+ dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
+ RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
+ RTE_DMA_CAPA_DEV_TO_DEV | RTE_DMA_CAPA_OPS_COPY;
+ dev_info->max_desc = DPI_MAX_DESC;
+ dev_info->min_desc = 1;
+ dev_info->max_sges = DPI_MAX_POINTER;
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_configure(struct rte_dma_dev *dev,
+ const struct rte_dma_conf *conf, uint32_t conf_sz)
+{
+ struct cnxk_dpi_vf_s *dpivf = NULL;
+ int rc = 0;
+
+ RTE_SET_USED(conf);
+ RTE_SET_USED(conf);
+ RTE_SET_USED(conf_sz);
+ RTE_SET_USED(conf_sz);
+ dpivf = dev->fp_obj->dev_private;
+ rc = roc_dpi_configure(&dpivf->rdpi);
+ if (rc < 0)
+ plt_err("DMA configure failed err = %d", rc);
+
+ return rc;
+}
+
+static int
+cnxk_dmadev_vchan_setup(struct rte_dma_dev *dev, uint16_t vchan,
+ const struct rte_dma_vchan_conf *conf,
+ uint32_t conf_sz)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+ struct cnxk_dpi_compl_s *comp_data;
+ union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
+ int i;
+
+ RTE_SET_USED(vchan);
+ RTE_SET_USED(conf_sz);
+
+ header->s.pt = DPI_HDR_PT_ZBW_CA;
+
+ switch (conf->direction) {
+ case RTE_DMA_DIR_DEV_TO_MEM:
+ header->s.xtype = DPI_XTYPE_INBOUND;
+ header->s.lport = conf->src_port.pcie.coreid;
+ header->s.fport = 0;
+ header->s.pvfe = 1;
+ break;
+ case RTE_DMA_DIR_MEM_TO_DEV:
+ header->s.xtype = DPI_XTYPE_OUTBOUND;
+ header->s.lport = 0;
+ header->s.fport = conf->dst_port.pcie.coreid;
+ header->s.pvfe = 1;
+ break;
+ case RTE_DMA_DIR_MEM_TO_MEM:
+ header->s.xtype = DPI_XTYPE_INTERNAL_ONLY;
+ header->s.lport = 0;
+ header->s.fport = 0;
+ header->s.pvfe = 0;
+ break;
+ case RTE_DMA_DIR_DEV_TO_DEV:
+ header->s.xtype = DPI_XTYPE_EXTERNAL_ONLY;
+ header->s.lport = conf->src_port.pcie.coreid;
+ header->s.fport = conf->dst_port.pcie.coreid;
+ };
+
+ for (i = 0; i < conf->nb_desc; i++) {
+ comp_data = rte_zmalloc(NULL, sizeof(*comp_data), 0);
+ if (comp_data == NULL) {
+ plt_err("Failed to allocate for comp_data");
+ return -ENOMEM;
+ }
+ dpivf->conf.c_desc.compl_ptr[i] = comp_data;
+ };
+ dpivf->conf.c_desc.max_cnt = DPI_MAX_DESC;
+ dpivf->conf.c_desc.head = 0;
+ dpivf->conf.c_desc.tail = 0;
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_start(struct rte_dma_dev *dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+
+ dpivf->desc_idx = 0;
+ dpivf->num_words = 0;
+ roc_dpi_enable(&dpivf->rdpi);
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_stop(struct rte_dma_dev *dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+
+ roc_dpi_disable(&dpivf->rdpi);
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_close(struct rte_dma_dev *dev)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+
+ roc_dpi_disable(&dpivf->rdpi);
+ roc_dpi_dev_fini(&dpivf->rdpi);
+
+ return 0;
+}
+
+static inline int
+__dpi_queue_write(struct roc_dpi *dpi, uint64_t *cmds, int cmd_count)
+{
+ uint64_t *ptr = dpi->chunk_base;
+
+ if ((cmd_count < DPI_MIN_CMD_SIZE) || (cmd_count > DPI_MAX_CMD_SIZE) ||
+ cmds == NULL)
+ return -EINVAL;
+
+ /*
+ * Normally there is plenty of room in the current buffer for the
+ * command
+ */
+ if (dpi->chunk_head + cmd_count < dpi->pool_size_m1) {
+ ptr += dpi->chunk_head;
+ dpi->chunk_head += cmd_count;
+ while (cmd_count--)
+ *ptr++ = *cmds++;
+ } else {
+ int count;
+ uint64_t *new_buff = dpi->chunk_next;
+
+ dpi->chunk_next =
+ (void *)roc_npa_aura_op_alloc(dpi->aura_handle, 0);
+ if (!dpi->chunk_next) {
+ plt_err("Failed to alloc next buffer from NPA");
+ return -ENOMEM;
+ }
+
+ /*
+ * Figure out how many cmd words will fit in this buffer.
+ * One location will be needed for the next buffer pointer.
+ */
+ count = dpi->pool_size_m1 - dpi->chunk_head;
+ ptr += dpi->chunk_head;
+ cmd_count -= count;
+ while (count--)
+ *ptr++ = *cmds++;
+
+ /*
+ * chunk next ptr is 2 DWORDS
+ * second DWORD is reserved.
+ */
+ *ptr++ = (uint64_t)new_buff;
+ *ptr = 0;
+
+ /*
+ * The current buffer is full and has a link to the next
+ * buffers. Time to write the rest of the commands into the new
+ * buffer.
+ */
+ dpi->chunk_base = new_buff;
+ dpi->chunk_head = cmd_count;
+ ptr = new_buff;
+ while (cmd_count--)
+ *ptr++ = *cmds++;
+
+ /* queue index may be greater than pool size */
+ if (dpi->chunk_head >= dpi->pool_size_m1) {
+ new_buff = dpi->chunk_next;
+ dpi->chunk_next =
+ (void *)roc_npa_aura_op_alloc(dpi->aura_handle,
+ 0);
+ if (!dpi->chunk_next) {
+ plt_err("Failed to alloc next buffer from NPA");
+ return -ENOMEM;
+ }
+ /* Write next buffer address */
+ *ptr = (uint64_t)new_buff;
+ dpi->chunk_base = new_buff;
+ dpi->chunk_head = 0;
+ }
+ }
+
+ return 0;
+}
+
+static int
+cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
+ rte_iova_t dst, uint32_t length, uint64_t flags)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
+ struct cnxk_dpi_compl_s *comp_ptr;
+ rte_iova_t fptr, lptr;
+ int num_words = 0;
+ int rc;
+
+ RTE_SET_USED(vchan);
+
+ comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
+ comp_ptr->cdata = DPI_REQ_CDATA;
+ header->s.ptr = (uint64_t)comp_ptr;
+ STRM_INC(dpivf->conf.c_desc);
+
+ header->s.nfst = 1;
+ header->s.nlst = 1;
+
+ /*
+ * For inbound case, src pointers are last pointers.
+ * For all other cases, src pointers are first pointers.
+ */
+ if (header->s.xtype == DPI_XTYPE_INBOUND) {
+ fptr = dst;
+ lptr = src;
+ } else {
+ fptr = src;
+ lptr = dst;
+ }
+
+ dpivf->cmd[0] = header->u[0];
+ dpivf->cmd[1] = header->u[1];
+ dpivf->cmd[2] = header->u[2];
+ /* word3 is always 0 */
+ num_words += 4;
+ dpivf->cmd[num_words++] = length;
+ dpivf->cmd[num_words++] = fptr;
+ dpivf->cmd[num_words++] = length;
+ dpivf->cmd[num_words++] = lptr;
+
+ rc = __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words);
+ if (!rc) {
+ if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
+ rte_wmb();
+ plt_write64(num_words,
+ dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+ }
+ dpivf->num_words += num_words;
+ }
+
+ return dpivf->desc_idx++;
+}
+
+static uint16_t
+cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
+ uint16_t *last_idx, bool *has_error)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ int cnt;
+
+ RTE_SET_USED(vchan);
+ for (cnt = 0; cnt < nb_cpls; cnt++) {
+ struct cnxk_dpi_compl_s *comp_ptr =
+ dpivf->conf.c_desc.compl_ptr[cnt];
+
+ if (comp_ptr->cdata) {
+ *has_error = 1;
+ break;
+ }
+ }
+
+ *last_idx = cnt - 1;
+ dpivf->conf.c_desc.tail = cnt;
+
+ return cnt;
+}
+
+static uint16_t
+cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan,
+ const uint16_t nb_cpls, uint16_t *last_idx,
+ enum rte_dma_status_code *status)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ int cnt;
+
+ RTE_SET_USED(vchan);
+ RTE_SET_USED(last_idx);
+ for (cnt = 0; cnt < nb_cpls; cnt++) {
+ struct cnxk_dpi_compl_s *comp_ptr =
+ dpivf->conf.c_desc.compl_ptr[cnt];
+ status[cnt] = comp_ptr->cdata;
+ }
+
+ *last_idx = cnt - 1;
+ dpivf->conf.c_desc.tail = 0;
+
+ return cnt;
+}
+
+static int
+cnxk_dmadev_submit(void *dev_private, uint16_t vchan __rte_unused)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+
+ rte_wmb();
+ plt_write64(dpivf->num_words, dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+
+ return 0;
+}
+
+static const struct rte_dma_dev_ops cnxk_dmadev_ops = {
+ .dev_info_get = cnxk_dmadev_info_get,
+ .dev_configure = cnxk_dmadev_configure,
+ .dev_start = cnxk_dmadev_start,
+ .dev_stop = cnxk_dmadev_stop,
+ .vchan_setup = cnxk_dmadev_vchan_setup,
+ .dev_close = cnxk_dmadev_close,
+};
+
static int
cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
struct rte_pci_device *pci_dev)
@@ -50,6 +375,12 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
dmadev->device = &pci_dev->device;
dmadev->fp_obj->dev_private = dpivf;
+ dmadev->dev_ops = &cnxk_dmadev_ops;
+
+ dmadev->fp_obj->copy = cnxk_dmadev_copy;
+ dmadev->fp_obj->submit = cnxk_dmadev_submit;
+ dmadev->fp_obj->completed = cnxk_dmadev_completed;
+ dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
rdpi = &dpivf->rdpi;
diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
index f573e17bf6..eb94ff8ec7 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.h
+++ b/drivers/dma/cnxk/cnxk_dmadev.h
@@ -4,8 +4,40 @@
#ifndef CNXK_DMADEV_H
#define CNXK_DMADEV_H
+#define DPI_MAX_POINTER 15
+#define DPI_QUEUE_STOP 0x0
+#define DPI_QUEUE_START 0x1
+#define STRM_INC(s) ((s).tail = ((s).tail + 1) % (s).max_cnt)
+#define DPI_MAX_DESC DPI_MAX_POINTER
+
+/* Set Completion data to 0xFF when request submitted,
+ * upon successful request completion engine reset to completion status
+ */
+#define DPI_REQ_CDATA 0xFF
+
+struct cnxk_dpi_compl_s {
+ uint64_t cdata;
+ void *cb_data;
+};
+
+struct cnxk_dpi_cdesc_data_s {
+ struct cnxk_dpi_compl_s *compl_ptr[DPI_MAX_DESC];
+ uint16_t max_cnt;
+ uint16_t head;
+ uint16_t tail;
+};
+
+struct cnxk_dpi_conf {
+ union dpi_instr_hdr_s hdr;
+ struct cnxk_dpi_cdesc_data_s c_desc;
+};
+
struct cnxk_dpi_vf_s {
struct roc_dpi rdpi;
+ struct cnxk_dpi_conf conf;
+ uint64_t cmd[DPI_MAX_CMD_SIZE];
+ uint32_t num_words;
+ uint16_t desc_idx;
};
#endif
diff --git a/drivers/dma/cnxk/version.map b/drivers/dma/cnxk/version.map
new file mode 100644
index 0000000000..c2e0723b4c
--- /dev/null
+++ b/drivers/dma/cnxk/version.map
@@ -0,0 +1,3 @@
+DPDK_22 {
+ local: *;
+};
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH v3 4/5] dma/cnxk: add copy_sg function
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 1/5] " Radha Mohan Chintakuntla
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 3/5] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
@ 2021-11-03 18:01 ` Radha Mohan Chintakuntla
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 5/5] dma/cnxk: add stats function Radha Mohan Chintakuntla
3 siblings, 0 replies; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-11-03 18:01 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
Add the copy_sg function that will do the multiple DMA transfers of
different sizes and different source/destination as well.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
drivers/dma/cnxk/cnxk_dmadev.c | 69 +++++++++++++++++++++++++++++++++-
1 file changed, 68 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
index 1738129fa1..360e92f7ce 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.c
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -29,7 +29,8 @@ cnxk_dmadev_info_get(const struct rte_dma_dev *dev,
dev_info->nb_vchans = 1;
dev_info->dev_capa = RTE_DMA_CAPA_MEM_TO_MEM |
RTE_DMA_CAPA_MEM_TO_DEV | RTE_DMA_CAPA_DEV_TO_MEM |
- RTE_DMA_CAPA_DEV_TO_DEV | RTE_DMA_CAPA_OPS_COPY;
+ RTE_DMA_CAPA_DEV_TO_DEV | RTE_DMA_CAPA_OPS_COPY |
+ RTE_DMA_CAPA_OPS_COPY_SG;
dev_info->max_desc = DPI_MAX_DESC;
dev_info->min_desc = 1;
dev_info->max_sges = DPI_MAX_POINTER;
@@ -277,6 +278,71 @@ cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
return dpivf->desc_idx++;
}
+static int
+cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan,
+ const struct rte_dma_sge *src,
+ const struct rte_dma_sge *dst,
+ uint16_t nb_src, uint16_t nb_dst, uint64_t flags)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev_private;
+ union dpi_instr_hdr_s *header = &dpivf->conf.hdr;
+ const struct rte_dma_sge *fptr, *lptr;
+ struct cnxk_dpi_compl_s *comp_ptr;
+ int num_words = 0;
+ int i, rc;
+
+ RTE_SET_USED(vchan);
+
+ comp_ptr = dpivf->conf.c_desc.compl_ptr[dpivf->conf.c_desc.tail];
+ comp_ptr->cdata = DPI_REQ_CDATA;
+ header->s.ptr = (uint64_t)comp_ptr;
+ STRM_INC(dpivf->conf.c_desc);
+
+ /*
+ * For inbound case, src pointers are last pointers.
+ * For all other cases, src pointers are first pointers.
+ */
+ if (header->s.xtype == DPI_XTYPE_INBOUND) {
+ header->s.nfst = nb_dst & 0xf;
+ header->s.nlst = nb_src & 0xf;
+ fptr = &dst[0];
+ lptr = &src[0];
+ } else {
+ header->s.nfst = nb_src & 0xf;
+ header->s.nlst = nb_dst & 0xf;
+ fptr = &src[0];
+ lptr = &dst[0];
+ }
+
+ dpivf->cmd[0] = header->u[0];
+ dpivf->cmd[1] = header->u[1];
+ dpivf->cmd[2] = header->u[2];
+ num_words += 4;
+ for (i = 0; i < header->s.nfst; i++) {
+ dpivf->cmd[num_words++] = (uint64_t)fptr->length;
+ dpivf->cmd[num_words++] = fptr->addr;
+ fptr++;
+ }
+
+ for (i = 0; i < header->s.nlst; i++) {
+ dpivf->cmd[num_words++] = (uint64_t)lptr->length;
+ dpivf->cmd[num_words++] = lptr->addr;
+ lptr++;
+ }
+
+ rc = __dpi_queue_write(&dpivf->rdpi, dpivf->cmd, num_words);
+ if (!rc) {
+ if (flags & RTE_DMA_OP_FLAG_SUBMIT) {
+ rte_wmb();
+ plt_write64(num_words,
+ dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+ }
+ dpivf->num_words += num_words;
+ }
+
+ return dpivf->desc_idx++;
+}
+
static uint16_t
cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
uint16_t *last_idx, bool *has_error)
@@ -378,6 +444,7 @@ cnxk_dmadev_probe(struct rte_pci_driver *pci_drv __rte_unused,
dmadev->dev_ops = &cnxk_dmadev_ops;
dmadev->fp_obj->copy = cnxk_dmadev_copy;
+ dmadev->fp_obj->copy_sg = cnxk_dmadev_copy_sg;
dmadev->fp_obj->submit = cnxk_dmadev_submit;
dmadev->fp_obj->completed = cnxk_dmadev_completed;
dmadev->fp_obj->completed_status = cnxk_dmadev_completed_status;
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [dpdk-dev] [PATCH v3 5/5] dma/cnxk: add stats function
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 1/5] " Radha Mohan Chintakuntla
` (2 preceding siblings ...)
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 4/5] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
@ 2021-11-03 18:01 ` Radha Mohan Chintakuntla
3 siblings, 0 replies; 32+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-11-03 18:01 UTC (permalink / raw)
To: thomas, fengchengwen, ndabilpuram, kirankumark, skori,
skoteshwar, jerinj, sburla
Cc: dev, Radha Mohan Chintakuntla
Add the stats function to get the DMA statistics.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
drivers/dma/cnxk/cnxk_dmadev.c | 41 ++++++++++++++++++++++++++++++++--
drivers/dma/cnxk/cnxk_dmadev.h | 1 +
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c
index 360e92f7ce..2824c1b44f 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.c
+++ b/drivers/dma/cnxk/cnxk_dmadev.c
@@ -271,6 +271,7 @@ cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src,
rte_wmb();
plt_write64(num_words,
dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+ dpivf->stats.submitted++;
}
dpivf->num_words += num_words;
}
@@ -336,6 +337,7 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan,
rte_wmb();
plt_write64(num_words,
dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+ dpivf->stats.submitted += nb_src;
}
dpivf->num_words += num_words;
}
@@ -357,12 +359,14 @@ cnxk_dmadev_completed(void *dev_private, uint16_t vchan, const uint16_t nb_cpls,
if (comp_ptr->cdata) {
*has_error = 1;
+ dpivf->stats.errors++;
break;
}
}
*last_idx = cnt - 1;
dpivf->conf.c_desc.tail = cnt;
+ dpivf->stats.completed += cnt;
return cnt;
}
@@ -381,10 +385,13 @@ cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan,
struct cnxk_dpi_compl_s *comp_ptr =
dpivf->conf.c_desc.compl_ptr[cnt];
status[cnt] = comp_ptr->cdata;
+ if (comp_ptr->cdata)
+ dpivf->stats.errors++;
}
*last_idx = cnt - 1;
dpivf->conf.c_desc.tail = 0;
+ dpivf->stats.completed += cnt;
return cnt;
}
@@ -396,17 +403,47 @@ cnxk_dmadev_submit(void *dev_private, uint16_t vchan __rte_unused)
rte_wmb();
plt_write64(dpivf->num_words, dpivf->rdpi.rbase + DPI_VDMA_DBELL);
+ dpivf->stats.submitted++;
return 0;
}
+static int
+cnxk_stats_get(const struct rte_dma_dev *dev, uint16_t vchan,
+ struct rte_dma_stats *rte_stats, uint32_t size)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+ struct rte_dma_stats *stats = &dpivf->stats;
+
+ RTE_SET_USED(vchan);
+
+ if (size < sizeof(rte_stats))
+ return -EINVAL;
+ if (rte_stats == NULL)
+ return -EINVAL;
+
+ *rte_stats = *stats;
+ return 0;
+}
+
+static int
+cnxk_stats_reset(struct rte_dma_dev *dev, uint16_t vchan __rte_unused)
+{
+ struct cnxk_dpi_vf_s *dpivf = dev->fp_obj->dev_private;
+
+ dpivf->stats = (struct rte_dma_stats){0};
+ return 0;
+}
+
static const struct rte_dma_dev_ops cnxk_dmadev_ops = {
- .dev_info_get = cnxk_dmadev_info_get,
+ .dev_close = cnxk_dmadev_close,
.dev_configure = cnxk_dmadev_configure,
+ .dev_info_get = cnxk_dmadev_info_get,
.dev_start = cnxk_dmadev_start,
.dev_stop = cnxk_dmadev_stop,
+ .stats_get = cnxk_stats_get,
+ .stats_reset = cnxk_stats_reset,
.vchan_setup = cnxk_dmadev_vchan_setup,
- .dev_close = cnxk_dmadev_close,
};
static int
diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h
index eb94ff8ec7..5fc241b55e 100644
--- a/drivers/dma/cnxk/cnxk_dmadev.h
+++ b/drivers/dma/cnxk/cnxk_dmadev.h
@@ -35,6 +35,7 @@ struct cnxk_dpi_conf {
struct cnxk_dpi_vf_s {
struct roc_dpi rdpi;
struct cnxk_dpi_conf conf;
+ struct rte_dma_stats stats;
uint64_t cmd[DPI_MAX_CMD_SIZE];
uint32_t num_words;
uint16_t desc_idx;
--
2.17.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
@ 2021-11-07 20:55 ` Thomas Monjalon
2021-11-07 23:04 ` Thomas Monjalon
1 sibling, 0 replies; 32+ messages in thread
From: Thomas Monjalon @ 2021-11-07 20:55 UTC (permalink / raw)
To: Radha Mohan Chintakuntla
Cc: fengchengwen, ndabilpuram, kirankumark, skori, skoteshwar,
jerinj, sburla, dev
03/11/2021 19:01, Radha Mohan Chintakuntla:
> This patch creates and initializes a dmadev device on pci probe.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
> MAINTAINERS | 6 ++
> doc/guides/dmadevs/cnxk.rst | 58 +++++++++++++++++++
> doc/guides/dmadevs/index.rst | 1 +
> doc/guides/platform/cnxk.rst | 5 +-
> drivers/dma/cnxk/cnxk_dmadev.c | 100 +++++++++++++++++++++++++++++++++
> drivers/dma/cnxk/cnxk_dmadev.h | 11 ++++
> drivers/dma/cnxk/meson.build | 7 +++
> drivers/dma/meson.build | 1 +
> 8 files changed, 188 insertions(+), 1 deletion(-)
This patch does not compile because drivers/dma/cnxk/version.map is missing.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
2021-11-07 20:55 ` Thomas Monjalon
@ 2021-11-07 23:04 ` Thomas Monjalon
2021-11-09 3:52 ` Radha Mohan
1 sibling, 1 reply; 32+ messages in thread
From: Thomas Monjalon @ 2021-11-07 23:04 UTC (permalink / raw)
To: Radha Mohan Chintakuntla
Cc: fengchengwen, ndabilpuram, kirankumark, skori, skoteshwar,
jerinj, sburla, dev
03/11/2021 19:01, Radha Mohan Chintakuntla:
> This patch creates and initializes a dmadev device on pci probe.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
Series applied with few small improvements in the doc,
compilation and other more or less important details
like the release notes.
I think you forgot to update dpdk-devbind script.
See also this patch:
https://patches.dpdk.org/project/dpdk/patch/20211107225708.3087968-1-thomas@monjalon.net/
Overall I have doubts about the quality but I want to move forward
with the new DMA drivers.
I will be probably less flexible with the next patches.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe
2021-11-07 23:04 ` Thomas Monjalon
@ 2021-11-09 3:52 ` Radha Mohan
2021-11-09 8:11 ` Thomas Monjalon
0 siblings, 1 reply; 32+ messages in thread
From: Radha Mohan @ 2021-11-09 3:52 UTC (permalink / raw)
To: Thomas Monjalon
Cc: Radha Mohan Chintakuntla, Chengwen Feng, Nithin Dabilpuram,
Kiran Kumar K, Sunil Kumar Kori, Satha Koteswara Rao Kottidi,
Jerin Jacob Kollanukkaran, Satananda Burla, dpdk-dev
On Sun, Nov 7, 2021 at 6:04 PM Thomas Monjalon <thomas@monjalon.net> wrote:
>
> 03/11/2021 19:01, Radha Mohan Chintakuntla:
> > This patch creates and initializes a dmadev device on pci probe.
> >
> > Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
>
> Series applied with few small improvements in the doc,
> compilation and other more or less important details
> like the release notes.
Thank you.
>
> I think you forgot to update dpdk-devbind script.
> See also this patch:
> https://patches.dpdk.org/project/dpdk/patch/20211107225708.3087968-1-thomas@monjalon.net/
Yes need to remove it from "misc" but also rename octeontx2_dma to
cnxk_dma and add under "dma_devices". I missed this.
I can push a patch which does both or if are ok to update yours then
that would be great.
diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index bb00f43702..643860b3ae 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -41,7 +41,7 @@
'SVendor': None, 'SDevice': None}
octeontx2_npa = {'Class': '08', 'Vendor': '177d', 'Device': 'a0fb,a0fc',
'SVendor': None, 'SDevice': None}
-octeontx2_dma = {'Class': '08', 'Vendor': '177d', 'Device': 'a081',
+cnxk_dma = {'Class': '08', 'Vendor': '177d', 'Device': 'a081',
'SVendor': None, 'SDevice': None}
octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',
'SVendor': None, 'SDevice': None}
@@ -71,13 +71,14 @@
network_devices = [network_class, cavium_pkx, avp_vnic, ifpga_class]
baseband_devices = [acceleration_class]
crypto_devices = [encryption_class, intel_processor_class]
-dma_devices = [intel_idxd_spr, intel_ioat_bdw, intel_ioat_icx, intel_ioat_skx]
+dma_devices = [intel_idxd_spr, intel_ioat_bdw, intel_ioat_icx, intel_ioat_skx
+ cnxk_dma]
eventdev_devices = [cavium_sso, cavium_tim, intel_dlb, octeontx2_sso]
mempool_devices = [cavium_fpa, octeontx2_npa]
compress_devices = [cavium_zip]
regex_devices = [octeontx2_ree]
-misc_devices = [cnxk_bphy, cnxk_bphy_cgx, cnxk_inl_dev, intel_ntb_skx,
- intel_ntb_icx, octeontx2_dma]
+misc_devices = [cnxk_bphy, cnxk_bphy_cgx, cnxk_inl_dev,
+ intel_ntb_skx, intel_ntb_icx]
>
> Overall I have doubts about the quality but I want to move forward
> with the new DMA drivers.
> I will be probably less flexible with the next patches.
Ok. Please let know if you find any specific ones that needs improvements.
>
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe
2021-11-09 3:52 ` Radha Mohan
@ 2021-11-09 8:11 ` Thomas Monjalon
0 siblings, 0 replies; 32+ messages in thread
From: Thomas Monjalon @ 2021-11-09 8:11 UTC (permalink / raw)
To: Radha Mohan
Cc: Radha Mohan Chintakuntla, Chengwen Feng, Nithin Dabilpuram,
Kiran Kumar K, Sunil Kumar Kori, Satha Koteswara Rao Kottidi,
Jerin Jacob Kollanukkaran, Satananda Burla, dpdk-dev
09/11/2021 04:52, Radha Mohan:
> On Sun, Nov 7, 2021 at 6:04 PM Thomas Monjalon <thomas@monjalon.net> wrote:
> >
> > 03/11/2021 19:01, Radha Mohan Chintakuntla:
> > > This patch creates and initializes a dmadev device on pci probe.
> > >
> > > Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> >
> > Series applied with few small improvements in the doc,
> > compilation and other more or less important details
> > like the release notes.
>
> Thank you.
> >
> > I think you forgot to update dpdk-devbind script.
> > See also this patch:
> > https://patches.dpdk.org/project/dpdk/patch/20211107225708.3087968-1-thomas@monjalon.net/
>
> Yes need to remove it from "misc" but also rename octeontx2_dma to
> cnxk_dma and add under "dma_devices". I missed this.
>
> I can push a patch which does both or if are ok to update yours then
> that would be great.
I'll wait for your patch.
Please make sure to rebase on the latest branch.
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2021-11-09 8:11 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-26 4:12 [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support Radha Mohan Chintakuntla
2021-10-26 4:12 ` [dpdk-dev] [PATCH 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
2021-10-26 8:36 ` Jerin Jacob
2021-10-26 21:05 ` Radha Mohan
2021-10-26 4:12 ` [dpdk-dev] [PATCH 3/4] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
2021-10-26 8:41 ` Jerin Jacob
2021-10-28 18:18 ` Radha Mohan
2021-10-29 14:54 ` Jerin Jacob
2021-10-29 18:02 ` Radha Mohan
2021-10-26 4:13 ` [dpdk-dev] [PATCH 4/4] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
2021-10-26 8:42 ` Jerin Jacob
2021-10-26 8:33 ` [dpdk-dev] [PATCH 1/4] common/cnxk: add DPI DMA support Jerin Jacob
2021-10-26 15:57 ` Radha Mohan
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 " Radha Mohan Chintakuntla
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 2/4] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
2021-11-02 4:02 ` Jerin Jacob
2021-11-02 11:49 ` fengchengwen
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 3/4] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
2021-11-02 11:59 ` fengchengwen
2021-11-02 18:11 ` Radha Mohan
2021-11-02 3:40 ` [dpdk-dev] [PATCH v2 4/4] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
2021-11-02 12:02 ` fengchengwen
2021-11-02 11:45 ` [dpdk-dev] [PATCH v2 1/4] common/cnxk: add DPI DMA support fengchengwen
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 1/5] " Radha Mohan Chintakuntla
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 2/5] dma/cnxk: create and initialize dmadev on pci probe Radha Mohan Chintakuntla
2021-11-07 20:55 ` Thomas Monjalon
2021-11-07 23:04 ` Thomas Monjalon
2021-11-09 3:52 ` Radha Mohan
2021-11-09 8:11 ` Thomas Monjalon
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 3/5] dma/cnxk: add dma channel operations Radha Mohan Chintakuntla
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 4/5] dma/cnxk: add copy_sg function Radha Mohan Chintakuntla
2021-11-03 18:01 ` [dpdk-dev] [PATCH v3 5/5] dma/cnxk: add stats function Radha Mohan Chintakuntla
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