From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6FABCA04B4; Sat, 8 Aug 2020 16:40:26 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 980092BF9; Sat, 8 Aug 2020 16:40:25 +0200 (CEST) Received: from mail-oi1-f194.google.com (mail-oi1-f194.google.com [209.85.167.194]) by dpdk.org (Postfix) with ESMTP id 7EB8E1E35 for ; Sat, 8 Aug 2020 16:40:24 +0200 (CEST) Received: by mail-oi1-f194.google.com with SMTP id z22so4777208oid.1 for ; Sat, 08 Aug 2020 07:40:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=B+V+BdV9mR3G3d14z/3NSuV2RaL7xnWhWwPZfCpOB1s=; b=dn+Do+fv9T6zMZg/zadX2ACNMGQDj3iY+aTFVXIISby2ccAiADA0oijtzB+7zWxXyp fgcS8CppjNZGYAa3qvQ+9wPdBxVxrxuPB5gbO9j+1NmJgPjKEBmp2CeChWITZkHcZao/ JwCbzvSEm0HAvYiW8ELyOXuMxid+DG8s0JEjQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=B+V+BdV9mR3G3d14z/3NSuV2RaL7xnWhWwPZfCpOB1s=; b=BWRwDE9DHg6Hc/dOoBvLS5/XzldS/o2A50QnrG3mQ9E7mtVfoi9U96jizAjLZmqsMp 4czsZjhgwwCYhMyX46ghQdG7GcXAMTU6OUoyH2NCuBdvv1kYfSBSefGJ1vb/Bt0qw/sO RaaulszryIgMLahjFn9UpvoN67L9SsD4vw1hNgcrgqv2WsyhcZDhSy7ySlB4qhvx1Pou XXvEDdeihE7n02fuaTOGBFv2X1+WE5lBZ39gzrunKd8qOzUeM1XnffkrCy0x05nu0QUk YC91TJqiO84zbKv4HsgL6BQSkRki6JOOQ+vzacWLB/5qA4qKrX7a13JdWvHjxMc8COh4 b/vA== X-Gm-Message-State: AOAM530mZcfH2tPCBEIW8sgr/gYvG+cw8GOUVHvOAEL0Kkv8newUl1h7 0NlG9DQXr7RAhD7/UcHHpR9DETmazjwdgeS+g8BlzQ== X-Google-Smtp-Source: ABdhPJw9I/brLXxlMbpe2Wd5aUSp3d93qOeyI0Vk2foM2+SFzsgiIEbQb3HXyiv4Ef8V41n5s4OEFnruP6RgaX/mujs= X-Received: by 2002:a54:4f85:: with SMTP id g5mr15795872oiy.27.1596897623624; Sat, 08 Aug 2020 07:40:23 -0700 (PDT) MIME-Version: 1.0 References: <20200807120434.1701726-1-kirankumark@marvell.com> <20200808143631.1704756-1-kirankumark@marvell.com> In-Reply-To: <20200808143631.1704756-1-kirankumark@marvell.com> From: Ajit Khaparde Date: Sat, 8 Aug 2020 07:40:12 -0700 Message-ID: To: kirankumark@marvell.com Cc: Andrew Rybchenko , Ferruh Yigit , Thomas Monjalon , beilei.xing@intel.com, chas3@att.com, cloud.wangxiaoyun@huawei.com, cristian.dumitrescu@intel.com, dev@dpdk.org, grive@u256.net, hemant.agrawal@nxp.com, humin29@huawei.com, hyonkim@cisco.com, jasvinder.singh@intel.com, jerinj@marvell.com, jia.guo@intel.com, jingjing.wu@intel.com, johndale@cisco.com, keith.wiles@intel.com, lironh@marvell.com, matan@mellanox.com, ndabilpuram@marvell.com, orika@mellanox.com, qi.z.zhang@intel.com, qiming.yang@intel.com, rahul.lakkireddy@chelsio.com, rmody@marvell.com, rosen.xu@intel.com, sachin.saxena@nxp.com, shahafs@mellanox.com, shshaikh@marvell.com, somnath.kotur@broadcom.com, viacheslavo@mellanox.com, wei.zhao1@intel.com, xavier.huwei@huawei.com, xuanziyang2@huawei.com, yisen.zhuang@huawei.com, zhouguoyang@huawei.com Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH v2 1/2] ethdev: add level support for RSS offload types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Sat, Aug 8, 2020 at 7:36 AM wrote: > From: Kiran Kumar K > > This patch reserves 2 bits as input selection to select Inner and > outer layers for RSS computation. It is combined with existing > ETH_RSS_* to choose Inner or outer layers for L2, L3 and L4. How do you plan to use this? Do you need to make any changes to testpmd? > This functionality already exists in rte_flow through level parameter in > RSS action configuration rte_flow_action_rss. > > Signed-off-by: Kiran Kumar K > --- > v2 changes: > * Reserved bit 50 & 51 > > lib/librte_ethdev/rte_ethdev.h | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/lib/librte_ethdev/rte_ethdev.h > b/lib/librte_ethdev/rte_ethdev.h > index d29930fd8..28184cc85 100644 > --- a/lib/librte_ethdev/rte_ethdev.h > +++ b/lib/librte_ethdev/rte_ethdev.h > @@ -552,6 +552,33 @@ struct rte_eth_rss_conf { > #define RTE_ETH_RSS_L3_PRE64 (1ULL << 53) > #define RTE_ETH_RSS_L3_PRE96 (1ULL << 52) > > +/* > + * We use the following macros to combine with the above layers to choose > + * inner and outer layers or both for RSS computation. > + * Note: Default is 0: inner layers, 1: outer layers, 2: both > + * bit 50 and 51 are reserved for this. > + */ > + > +/** > + * Level 0, It basically stands for the innermost encapsulation level RSS > + * can be performed on according to PMD and device capabilities. > + */ > +#define ETH_RSS_LEVEL_INNER (0ULL << 50) > +/** > + * Level 1, It basically stands for the outermost encapsulation level RSS > + * can be performed on according to PMD and device capabilities. > + */ > +#define ETH_RSS_LEVEL_OUTER (1ULL << 50) > +/** > + * Level 2, It basically stands for the both inner and outermost > + * encapsulation level RSS can be performed on according to PMD and > + * device capabilities. > + */ > +#define ETH_RSS_LEVEL_INNER_OUTER (2ULL << 50) > +#define ETH_RSS_LEVEL_MASK (3ULL << 50) > + > +#define ETH_RSS_LEVEL(rss_hf) ((rss_hf & ETH_RSS_LEVEL_MASK) >> 50) > + > /** > * For input set change of hash filter, if SRC_ONLY and DST_ONLY of > * the same level are used simultaneously, it is the same case as > -- > 2.25.1 > >