From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt0-f170.google.com (mail-qt0-f170.google.com [209.85.216.170]) by dpdk.org (Postfix) with ESMTP id 4DF324A63 for ; Tue, 6 Jun 2017 16:01:34 +0200 (CEST) Received: by mail-qt0-f170.google.com with SMTP id w1so130347861qtg.2 for ; Tue, 06 Jun 2017 07:01:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=2n+bX1sYdRMCYT/t6ZEzE6mGV3k1k31j0CaODAq8QGc=; b=Y1gHQysFno3+CKc3m5Z/mc14A50popVma0+5h6FdUXRuO5+LwB3iWPggv824EE97kC niJj2130p6Qu1ODCyMcD/we/O8ecYHxwtpf8/1Rm8HfHIxCMLEFefObcjJkHPDzuE62y NDF712w63s/xKq/n8KgpMgnECLVPsBfpOFpb4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=2n+bX1sYdRMCYT/t6ZEzE6mGV3k1k31j0CaODAq8QGc=; b=ZTy5ONvOzuzZxHbE7prqPmOJ9RkpDaggLXpq9pdUB+3rYeE7z9BJvF5xruWVb/Io4C Py4EbAfvIuMfK74VcSvbTAi1xTJp4LLdYyinOylYq3coM8dQSOcOuAtxkyOqwayxb20h jceWGDsGsbRrYSVkDEO/JuC7bfc9GxVNFcB2fBUxo7KAw6qF0pp7DkbuckgM7hZ3yyYw tJzQxI3y76ge6iu/nUEv9sUk4wgpvzHaVJ/k3Dr5CiVWLGtzcnbrxiwRq+zX9yuW7h00 UH/xIoHggPVSa2xOF8sjqDN4D9uMReeUeB7aWnyP6Q/UM7I21tP9++qYks6IKA+H7wcO oehQ== X-Gm-Message-State: AODbwcCBac3wqeBl5/n0bKBgnqhOCNVCjrZ7znhQJYLwo9UZfRflGj/5 wzZBrXTfryuXVG9FpZG34A9F2J/gBcNB X-Received: by 10.237.56.234 with SMTP id k97mr15755772qte.45.1496757692771; Tue, 06 Jun 2017 07:01:32 -0700 (PDT) MIME-Version: 1.0 Received: by 10.237.49.132 with HTTP; Tue, 6 Jun 2017 07:00:52 -0700 (PDT) In-Reply-To: <8e3b1d20-dad2-53b3-a4cf-aaf0b5590212@intel.com> References: <20170601030232.38677-1-ajit.khaparde@broadcom.com> <20170601170723.48709-1-ajit.khaparde@broadcom.com> <20170601170723.48709-13-ajit.khaparde@broadcom.com> <8e3b1d20-dad2-53b3-a4cf-aaf0b5590212@intel.com> From: Ajit Khaparde Date: Tue, 6 Jun 2017 09:00:52 -0500 Message-ID: To: Ferruh Yigit Cc: dev@dpdk.org, Steeven Li Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [PATCH v4 12/26] net/bnxt: add support to set MTU X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Jun 2017 14:01:35 -0000 Ferruh, if it save times, can you please do that. Thanks Ajit On Tue, Jun 6, 2017 at 7:47 AM, Ferruh Yigit wrote: > On 6/1/2017 6:07 PM, Ajit Khaparde wrote: > > This patch adds support to modify MTU using the set_mtu dev_op. > > To support frames > 2k, the PMD creates an aggregator ring. > > When a frame greater than 2k is received, it is fragmented > > and the resulting fragments are DMA'ed to the aggregator ring. > > Now the driver can support jumbo frames upto 9500 bytes. > > > > Signed-off-by: Steeven Li > > Signed-off-by: Ajit Khaparde > > > > -- > > v1->v2: regroup related patches and incorporate other review comments > > > > v2->v3: > > - rebasing to next-net tree > > - Use net/bnxt instead of just bnxt in patch subject > > <...> > > > +int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp, > > + struct bnxt_vnic_info *vnic) > > +{ > > + int rc = 0; > > + struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 }; > > + struct hwrm_vnic_plcmodes_cfg_output *resp = > bp->hwrm_cmd_resp_addr; > > + uint16_t size; > > + > > + HWRM_PREP(req, VNIC_PLCMODES_CFG, -1, resp); > > + > > + req.flags = rte_cpu_to_le_32( > > +// HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT > | > > + HWRM_VNIC_PLCMODES_CFG_INPUT_ > FLAGS_JUMBO_PLACEMENT); > > +// HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 | > //TODO > > +// HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6); > > Hi Ajit, > > Would you mind if I remove these commented code, in this patch and other > patches, while applying? > > Of course it would be better if you send the new version of the patch to > fix them, but I believe I can do this faster. Just let me know please. > > Thanks, > ferruh > > > + req.enables = rte_cpu_to_le_32( > > + HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID); > > +// HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID); > > + > > + size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); > > + size -= RTE_PKTMBUF_HEADROOM; > > + > > + req.jumbo_thresh = rte_cpu_to_le_16(size); > > +// req.hds_threshold = rte_cpu_to_le_16(size); > > + req.vnic_id = rte_cpu_to_le_32(vnic->fw_vnic_id); > > + > > + rc = bnxt_hwrm_send_message(bp, &req, sizeof(req)); > > + > > + HWRM_CHECK_RESULT; > > + > > + return rc; > > +} > > <...> > >