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Fri, 22 Mar 2024 08:15:18 -0700 (PDT) MIME-Version: 1.0 References: <20240312075238.3319480-4-huangdengdui@huawei.com> <20240322070923.244417-1-huangdengdui@huawei.com> <20240322070923.244417-2-huangdengdui@huawei.com> <4413054.MSiuQNM8U4@thomas> In-Reply-To: <4413054.MSiuQNM8U4@thomas> From: Ajit Khaparde Date: Fri, 22 Mar 2024 08:15:00 -0700 Message-ID: Subject: Re: [PATCH v2 1/6] ethdev: support setting lanes To: Thomas Monjalon Cc: Dengdui Huang , dev@dpdk.org, ferruh.yigit@amd.com, aman.deep.singh@intel.com, yuying.zhang@intel.com, andrew.rybchenko@oktetlabs.ru, damodharam.ammepalli@broadcom.com, stephen@networkplumber.org, jerinjacobk@gmail.com, liuyonglong@huawei.com, fengchengwen@huawei.com, haijie1@huawei.com, lihuisong@huawei.com Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="000000000000ae6d5c0614414a46" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --000000000000ae6d5c0614414a46 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Mar 22, 2024 at 6:58=E2=80=AFAM Thomas Monjalon wrote: > > 22/03/2024 08:09, Dengdui Huang: > > -#define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps */ > > -#define RTE_ETH_LINK_SPEED_20G RTE_BIT32(9) /**< 20 Gbps */ > > -#define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps */ > > -#define RTE_ETH_LINK_SPEED_40G RTE_BIT32(11) /**< 40 Gbps */ > > -#define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps */ > > -#define RTE_ETH_LINK_SPEED_56G RTE_BIT32(13) /**< 56 Gbps */ > > -#define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps */ > > -#define RTE_ETH_LINK_SPEED_200G RTE_BIT32(15) /**< 200 Gbps */ > > -#define RTE_ETH_LINK_SPEED_400G RTE_BIT32(16) /**< 400 Gbps */ > > +#define RTE_ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps *= / > > +#define RTE_ETH_LINK_SPEED_20G RTE_BIT32(9) /**< 20 Gbps 2= lanes */ > > +#define RTE_ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps *= / > > +#define RTE_ETH_LINK_SPEED_40G RTE_BIT32(11) /**< 40 Gbps 4= lanes */ > > +#define RTE_ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps *= / > > +#define RTE_ETH_LINK_SPEED_56G RTE_BIT32(13) /**< 56 Gbps 4= lanes */ > > +#define RTE_ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps = */ > > +#define RTE_ETH_LINK_SPEED_200G RTE_BIT32(15) /**< 200 Gbps = 4lanes */ > > +#define RTE_ETH_LINK_SPEED_400G RTE_BIT32(16) /**< 400 Gbps = 4lanes */ > > +#define RTE_ETH_LINK_SPEED_10G_4LANES RTE_BIT32(17) /**< 10 Gbps = 4lanes */ > > +#define RTE_ETH_LINK_SPEED_50G_2LANES RTE_BIT32(18) /**< 50 Gbps 2= lanes */ > > +#define RTE_ETH_LINK_SPEED_100G_2LANES RTE_BIT32(19) /**< 100 Gbps = 2 lanes */ > > +#define RTE_ETH_LINK_SPEED_100G_4LANES RTE_BIT32(20) /**< 100 Gbps = 4lanes */ > > +#define RTE_ETH_LINK_SPEED_200G_2LANES RTE_BIT32(21) /**< 200 Gbps = 2lanes */ > > +#define RTE_ETH_LINK_SPEED_400G_8LANES RTE_BIT32(22) /**< 400 Gbps = 8lanes */ > > I don't think it is a good idea to make this more complex. > It brings nothing as far as I can see, compared to having speed and lanes= separated. > Can we have lanes information a separate value? no need for bitmask. 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