From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-f68.google.com (mail-ed1-f68.google.com [209.85.208.68]) by dpdk.org (Postfix) with ESMTP id 7DDD41B455 for ; Tue, 10 Jul 2018 17:37:09 +0200 (CEST) Received: by mail-ed1-f68.google.com with SMTP id d17-v6so4829274eds.11 for ; Tue, 10 Jul 2018 08:37:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=netronome-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=5r50ERLha33XG07iL6wyKAStVZka4Xuv58s/5bBZC2k=; b=xyNG5CAPtTPzEjsuHXGlbCgubkYL/99FIS9FTLzL1LSg3WEOFjY40Xl2L3jEQDu+k5 iW63fNAiiOVnjiDnqRHALBrGVk5xWULKuYvZPOfgl+4tAvqcp64WsC5ZCIBz5/P+TVJi JFy+/yTgVGcJoiuEckpjMmVm2ms9QsbQA/J+i+/Qt7O3fRwYLgdcXSyHYn9nUPGZnUER 6IK1eQAniKIuPYih14GLdTV8BMgXwYwvfFYkSEO66QLQL4seC1zET0P1oq+wpf7t4D8f 8Xfw+1Tk9j4+P7Myq3VtQdmPIBQfQobXEqqhfbL9Q4jxPYXnHDQBdFEIYDEW+QXM5++i OOpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=5r50ERLha33XG07iL6wyKAStVZka4Xuv58s/5bBZC2k=; b=X206UA5zYxvm70Ztb1HXkC0XWT/FG6PPf8/I5YqV0Xtvd7scIsgr3DSO0Ty6iqpjvi Ucgpy+b0OKDLk1E83YVFiKn1EYT5bCa3HVBoaOlxZ73YbyJcnFktSI9yNnRdFXf7g8OA NVpWHheGYu4cTrFTKOvUx6DTG7LYSxI9QfAwIRT/WinUH7fngVckEereIXRbQJSpcg/0 JCXBZCnlaNKb9Crewyb9rvNgtljdQELY1cDvW8GIkMPbtREfrNedHKxDxx8JqO1/T2v/ 0iOUNHmrXBa1HthH4inXPVDspX3tbo6w2hErbWN/ulUFvPkXrCvy+XtlPjtuH27wjQ9/ GoJg== X-Gm-Message-State: AOUpUlG+7BxRiY9vYns0Rtq8MsDv9BmTda5n/J4gTdYyXLGtqxS9sl6/ M40k+y6Hp97lsC8JXGG/lNNr/+RJ1UAR6huBu+6lSQ== X-Google-Smtp-Source: AAOMgpcHB+lN8qoDkiCyEKz9OOLPWZLxrFYwmz6S8ZLu/8fa48J9XsWUMRtR8bu3TAud0KEG6LyMNXZfKtIVzOaPeNc= X-Received: by 2002:a50:ade6:: with SMTP id b35-v6mr1317853edd.168.1531237029242; Tue, 10 Jul 2018 08:37:09 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a50:b194:0:0:0:0:0 with HTTP; Tue, 10 Jul 2018 08:37:08 -0700 (PDT) In-Reply-To: <79AD128F-0B7B-49B6-8F20-3C9A72036769@redhat.com> References: <1530708838-2682-1-git-send-email-alejandro.lucero@netronome.com> <1530708838-2682-4-git-send-email-alejandro.lucero@netronome.com> <79AD128F-0B7B-49B6-8F20-3C9A72036769@redhat.com> From: Alejandro Lucero Date: Tue, 10 Jul 2018 16:37:08 +0100 Message-ID: To: Eelco Chaudron Cc: dev , stable@dpdk.org, "Burakov, Anatoly" , Maxime Coquelin , Ferruh Yigit Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v3 3/6] bus/pci: use IOVAs check when setting IOVA mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jul 2018 15:37:09 -0000 On Tue, Jul 10, 2018 at 11:14 AM, Eelco Chaudron wrote: > > > On 4 Jul 2018, at 14:53, Alejandro Lucero wrote: > > Although VT-d emulation currently only supports 39 bits, it could >> be iovas being within that supported range. This patch allows >> IOVA mode in such a case. >> >> Indeed, memory initialization code can be modified for using lower >> virtual addresses than those used by the kernel for 64 bits processes >> by default, and therefore memsegs iovas can use 39 bits or less for >> most system. And this is likely 100% true for VMs. >> >> Signed-off-by: Alejandro Lucero >> --- >> drivers/bus/pci/linux/pci.c | 15 +++++++++++---- >> 1 file changed, 11 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c >> index 74deef3..792c819 100644 >> --- a/drivers/bus/pci/linux/pci.c >> +++ b/drivers/bus/pci/linux/pci.c >> @@ -43,6 +43,7 @@ >> #include >> #include >> #include >> +#include >> >> #include "eal_private.h" >> #include "eal_filesystem.h" >> @@ -613,10 +614,12 @@ >> fclose(fp); >> >> mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) >> + 1; >> - if (mgaw < X86_VA_WIDTH) >> + >> + if (!rte_eal_check_dma_mask(mgaw)) >> > > If think in this case we still need to check the X86_VA_WIDTH, i.e. > if (mgaw < X86_VA_WIDTH && !rte_eal_check_dma_mask(mgaw)) > > > + return true; >> + else >> return false; >> >> - return true; >> } >> #elif defined(RTE_ARCH_PPC_64) >> static bool >> @@ -640,13 +643,17 @@ >> { >> struct rte_pci_device *dev = NULL; >> struct rte_pci_driver *drv = NULL; >> + int iommu_dma_mask_check_done = 0; >> >> FOREACH_DRIVER_ON_PCIBUS(drv) { >> FOREACH_DEVICE_ON_PCIBUS(dev) { >> if (!rte_pci_match(drv, dev)) >> continue; >> - if (!pci_one_device_iommu_support_va(dev)) >> - return false; >> + if (!iommu_dma_mask_check_done) { >> + if (pci_one_device_iommu_support_va(dev) >> < 0) >> + return false; >> + iommu_dma_mask_check_done = 1; >> > > Not sure why this change? Why do we only need to check one device on the > bus? > > Because there is just one emulated IOMMU hardware. The limitation in this case is not in a specific PCI device. And I do not think it is possible to have two different (emulated or not) IOMMU hardware. Yes, you can have more than one controller but being same IOMMU type. > In addition, if this is what was intended, rather than a variable you can > return true in this case, or did you intended to clear the > iommu_dma_mask_check_done on every PCI BUS iteration? > > If pci_one_device_iommu_support_va, because the dma check, finds out the IOVAs are out of range, then the IOVA mode is PA and no further checks are required. But there could be a PCI device precluding the IOVA VA, so all the PCI devices need to be processed. > + } >> } >> } >> return true; >> -- >> 1.9.1 >> >