From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-f66.google.com (mail-ed1-f66.google.com [209.85.208.66]) by dpdk.org (Postfix) with ESMTP id 2550A58EC for ; Tue, 10 Jul 2018 13:40:41 +0200 (CEST) Received: by mail-ed1-f66.google.com with SMTP id g12-v6so16319402edi.9 for ; Tue, 10 Jul 2018 04:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=netronome-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=UWoVVmkXmMjRu4etPlRndFtikMI1jQS/jO/6O1Ssz4c=; b=JLv8vQEA3jsiSIcpVNIrDM01GygBdcYHL1qgr2Cgq/AgX5ZE5bKhPVXjoHcHK/pTSu S59dn3rwUUI/J7E3+pPqcaB2dXe3YEhvbN1G3646eZOXozX8nJiByq+NE4WUVMaMnlLm LjbBa4zTE1YCawTLZSqSulLPEY0EIABxjf0sWtsLR4RbEyBFHWcibeFf4j3QTHOCNuya M0qgeL51I9rKpb5VB2d3k59J/X6OwjB7f6FJWdnEp2VF5Jc+ZRg4oRHgqdZSzpxMLFR5 Ph//YTQ9aspXdCarzCeSxfqGmHLTLO0hbQin9R6Gcwk6IGQReEHU/iQPrWFno3L3J67g PXJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=UWoVVmkXmMjRu4etPlRndFtikMI1jQS/jO/6O1Ssz4c=; b=rhzrpdOAbl/UZP+iOkh9GINH8cxjxRbwh1HCLRpzSP2N3yLdrWLzILmXVOdzKWk/ab aLoIJXwJhed0RCFQZrsp3AcPoRto0/SrKVGL9ag5XaeCIhA+CUR7MZBpbAIUGiuRjsH0 vBM8rYSKYQjRBa1EXWtZWB6sxKM5putHzJ+M/YsUn9AEYRP4raL1sclLiFTUUZffh6N8 UHsc7DaxuuKrwFJSez8+26o9xLKpAO+gT1zsZj6Lq5uG5MnDjbHuyMl3DZJbbvfO2HG2 0LcsEHTjV25NUdPURdH3Nq+Py91ysA2QpXTcptt9bndPpwTcKlg7ibWqpgIekR7PPXtw S2NA== X-Gm-Message-State: APt69E3wNsxt7pEcydJgtm+9lldEVK75zCS2N7cG1GogA0+PlGbauQOY DsGHLmbcbjCx6M7U3TTnJC8/B4zkV1lNakfuayxJpA== X-Google-Smtp-Source: AAOMgpfrODKq9SaXHEaKtpi44ZmjN8nGc4bpNbyxFSq2CVcInPr1CG/htT+VPzRwGWGfaEwLWmfX+L1zASiaBL8fpC4= X-Received: by 2002:a50:a347:: with SMTP id 65-v6mr23869499edn.299.1531222840921; Tue, 10 Jul 2018 04:40:40 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a50:b194:0:0:0:0:0 with HTTP; Tue, 10 Jul 2018 04:40:40 -0700 (PDT) In-Reply-To: <24D4D56B-BE3A-43DC-AEEE-A063A11C73EC@redhat.com> References: <1530708838-2682-1-git-send-email-alejandro.lucero@netronome.com> <1530708838-2682-2-git-send-email-alejandro.lucero@netronome.com> <24D4D56B-BE3A-43DC-AEEE-A063A11C73EC@redhat.com> From: Alejandro Lucero Date: Tue, 10 Jul 2018 12:40:40 +0100 Message-ID: To: Eelco Chaudron Cc: dev , stable@dpdk.org, "Burakov, Anatoly" , Maxime Coquelin , Ferruh Yigit Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.15 Subject: Re: [dpdk-dev] [dpdk-stable] [PATCH v3 1/6] mem: add function for checking memsegs IOVAs addresses X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jul 2018 11:40:41 -0000 On Tue, Jul 10, 2018 at 12:14 PM, Eelco Chaudron wrote: > > > On 10 Jul 2018, at 12:52, Alejandro Lucero wrote: > > On Tue, Jul 10, 2018 at 11:06 AM, Eelco Chaudron >> wrote: >> >> >>> >>> On 10 Jul 2018, at 11:34, Alejandro Lucero wrote: >>> >>> On Tue, Jul 10, 2018 at 9:56 AM, Eelco Chaudron >>> >>>> wrote: >>>> >>>> >>>> >>>>> On 4 Jul 2018, at 14:53, Alejandro Lucero wrote: >>>>> >>>>> A device can suffer addressing limitations. This functions checks >>>>> >>>>> memsegs have iovas within the supported range based on dma mask. >>>>>> >>>>>> PMD should use this during initialization if supported devices >>>>>> suffer addressing limitations, returning an error if this function >>>>>> returns memsegs out of range. >>>>>> >>>>>> Another potential usage is for emulated IOMMU hardware with addressing >>>>>> limitations. >>>>>> >>>>>> Signed-off-by: Alejandro Lucero >>>>>> Acked-by: Anatoly Burakov >>>>>> --- >>>>>> lib/librte_eal/common/eal_common_memory.c | 33 >>>>>> ++++++++++++++++++++++++++++++ >>>>>> lib/librte_eal/common/include/rte_memory.h | 3 +++ >>>>>> lib/librte_eal/rte_eal_version.map | 1 + >>>>>> 3 files changed, 37 insertions(+) >>>>>> >>>>>> diff --git a/lib/librte_eal/common/eal_common_memory.c >>>>>> b/lib/librte_eal/common/eal_common_memory.c >>>>>> index fc6c44d..f5efebe 100644 >>>>>> --- a/lib/librte_eal/common/eal_common_memory.c >>>>>> +++ b/lib/librte_eal/common/eal_common_memory.c >>>>>> @@ -109,6 +109,39 @@ >>>>>> } >>>>>> } >>>>>> >>>>>> +/* check memseg iovas are within the required range based on dma mask >>>>>> */ >>>>>> +int >>>>>> +rte_eal_check_dma_mask(uint8_t maskbits) >>>>>> +{ >>>>>> + >>>>>> + const struct rte_mem_config *mcfg; >>>>>> + uint64_t mask; >>>>>> + int i; >>>>>> + >>>>>> >>>>>> >>>>>> I think we should add some sanity check to the input maskbits, i.e. >>>>> [64,0) >>>>> or [64, 32]? What would be a reasonable lower bound. >>>>> >>>>> >>>>> This is not a user's API, so any invocation will be reviewed, but I >>>>> guess >>>>> >>>> adding a sanity check here does not harm. >>>> >>>> Not sure about lower bound but upper should 64, although it does not >>>> make >>>> sense but it is safe. Lower bound is not so problematic. >>>> >>>> >>>> >>>> + /* create dma mask */ >>>>> >>>>> + mask = ~((1ULL << maskbits) - 1); >>>>>> + >>>>>> + /* get pointer to global configuration */ >>>>>> + mcfg = rte_eal_get_configuration()->mem_config; >>>>>> + >>>>>> + for (i = 0; i < RTE_MAX_MEMSEG; i++) { >>>>>> + if (mcfg->memseg[i].addr == NULL) >>>>>> + break; >>>>>> >>>>>> >>>>> Looking at some other code, it looks like NULL entries might exists. So >>> should a continue; rather than a break; be used here? >>> >>> >>> I do not think so. memsegs are allocated sequentially, so first with addr >> as NULL implies no more memsegs. >> > > I was referring to the mem walk functions, rte_memseg_list_walk(). Maybe > some having more experience with this area can review/comment. > > This patchset applies to 17.11.3 which has not that function implemented. You can see what rte_eal_get_physmem_size and rte_dump_physmem_layout do in lib/librte_eal/common/eal_common_memory.c file regarding memseg "walks" when addr is NULL. > > >> >> >>> + >>> >>>> + if (mcfg->memseg[i].iova & mask) { >>>>>> + RTE_LOG(INFO, EAL, >>>>>> + "memseg[%d] iova %"PRIx64" out of >>>>>> range:\n", >>>>>> + i, mcfg->memseg[i].iova); >>>>>> + >>>>>> + RTE_LOG(INFO, EAL, "\tusing dma mask >>>>>> %"PRIx64"\n", >>>>>> + mask); >>>>>> + return -1; >>>>>> + } >>>>>> + } >>>>>> + >>>>>> + return 0; >>>>>> +} >>>>>> + >>>>>> /* return the number of memory channels */ >>>>>> unsigned rte_memory_get_nchannel(void) >>>>>> { >>>>>> diff --git a/lib/librte_eal/common/include/rte_memory.h >>>>>> b/lib/librte_eal/common/include/rte_memory.h >>>>>> index 80a8fc0..b2a0168 100644 >>>>>> --- a/lib/librte_eal/common/include/rte_memory.h >>>>>> +++ b/lib/librte_eal/common/include/rte_memory.h >>>>>> @@ -209,6 +209,9 @@ struct rte_memseg { >>>>>> */ >>>>>> unsigned rte_memory_get_nrank(void); >>>>>> >>>>>> +/* check memsegs iovas are within a range based on dma mask */ >>>>>> +int rte_eal_check_dma_mask(uint8_t maskbits); >>>>>> + >>>>>> /** >>>>>> * Drivers based on uio will not load unless physical >>>>>> * addresses are obtainable. It is only possible to get >>>>>> diff --git a/lib/librte_eal/rte_eal_version.map >>>>>> b/lib/librte_eal/rte_eal_version.map >>>>>> index f4f46c1..aa6cf87 100644 >>>>>> --- a/lib/librte_eal/rte_eal_version.map >>>>>> +++ b/lib/librte_eal/rte_eal_version.map >>>>>> @@ -184,6 +184,7 @@ DPDK_17.11 { >>>>>> >>>>>> rte_eal_create_uio_dev; >>>>>> rte_bus_get_iommu_class; >>>>>> + rte_eal_check_dma_mask; >>>>>> rte_eal_has_pci; >>>>>> rte_eal_iova_mode; >>>>>> rte_eal_mbuf_default_mempool_ops; >>>>>> -- >>>>>> 1.9.1 >>>>>> >>>>>> >>>>>> >>>>> >>> >>> > >