From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ig0-f175.google.com (mail-ig0-f175.google.com [209.85.213.175]) by dpdk.org (Postfix) with ESMTP id B8ADF952 for ; Wed, 1 Jul 2015 16:22:36 +0200 (CEST) Received: by igblr2 with SMTP id lr2so98744990igb.0 for ; Wed, 01 Jul 2015 07:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=6LC17zuoGH40KROXBHMOcNXuNUZuK82JC6Zf/aPYqnc=; b=tV8cBvZh96t8YWLBAZA1iinnV1PVsHwrwrmsekJMqb7iiBDzl45uT6/ImDKt8sjg0q MtB9MwQBkzKuumnQ4uKD6PP26pNe5hS5EJtXmVx01dup5nSiE3Vs1vaMLw/62GaFrzrM 1X2YftnG/QvEl1UrU5y+sWC/iqf/z3NnDygN8l3EqYvxovRDX7nqBJmv5O4B4zFEGpgy CH4Ne/tfLG8Pjj0DZjIboyho8agPgpDMJu613gYFDJDZT/emwayi6NCUO7JjAgaoMCUP B7Ki8LknUjfcyYsmVk50s5mBPq3Ec8sMkY2A3Et1JyTqVY4F2RdXgdZ9K6RijEevwuai wpsw== MIME-Version: 1.0 X-Received: by 10.43.173.70 with SMTP id ob6mr4454334icc.45.1435760555271; Wed, 01 Jul 2015 07:22:35 -0700 (PDT) Received: by 10.79.107.148 with HTTP; Wed, 1 Jul 2015 07:22:35 -0700 (PDT) In-Reply-To: References: <20150701125918.GA6960@bricha3-MOBL3> Date: Wed, 1 Jul 2015 10:22:35 -0400 Message-ID: From: Anuj Kalia To: Vladimir Medvedkin Content-Type: text/plain; charset=UTF-8 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] Could not achieve wire speed for 40GE with any DPDK version on XL710 NIC's X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Jul 2015 14:22:37 -0000 Vladimir, Few possible fixes to your PCIe analysis (let me know if I'm wrong): - ECRC is probably disabled (check using sudo lspci -vvv | grep CGenEn-), so TLP header is 26 bytes - Descriptor writeback can be batched using high value of WTHRESH, which is what DPDK uses by default - Read request contains full TLP header (26 bytes) Assuming WTHRESH = 4, bytes transferred from NIC to host per packet = 26 + 64 (packet itself) + (26 + 32) / 4 (batched descriptor writeback) + (26 / 4) (read request for new descriptors) = 111 bytes / packet This corresponds to 70.9 Mpps over PCIe 3.0 x8. Assuming 5% DLLP overhead, rate = 67.4 Mpps --Anuj On Wed, Jul 1, 2015 at 9:40 AM, Vladimir Medvedkin wrote: > In case with syn flood you should take into account return syn-ack traffic, > which generates PCIe DLLP's from NIC to host, thus pcie bandwith exceeds > faster. And don't forget about DLLP's generated by rx traffic, which > saturates host-to-NIC bus. > > 2015-07-01 16:05 GMT+03:00 Pavel Odintsov : > >> Yes, Bruce, we understand this. But we are working with huge SYN >> attacks processing and they are 64byte only :( >> >> On Wed, Jul 1, 2015 at 3:59 PM, Bruce Richardson >> wrote: >> > On Wed, Jul 01, 2015 at 03:44:57PM +0300, Pavel Odintsov wrote: >> >> Thanks for answer, Vladimir! So we need look for x16 NIC if we want >> >> achieve 40GE line rate... >> >> >> > Note that this would only apply for your minimal i.e. 64-byte, packet >> sizes. >> > Once you go up to larger e.g. 128B packets, your PCI bandwidth >> requirements >> > are lower and you can easier achieve line rate. >> > >> > /Bruce >> > >> >> On Wed, Jul 1, 2015 at 3:06 PM, Vladimir Medvedkin < >> medvedkinv@gmail.com> wrote: >> >> > Hi Pavel, >> >> > >> >> > Looks like you ran into pcie bottleneck. So let's calculate xl710 rx >> only >> >> > case. >> >> > Assume we have 32byte descriptors (if we want more offload). >> >> > DMA makes one pcie transaction with packet payload, one descriptor >> writeback >> >> > and one memory request for free descriptors for every 4 packets. For >> >> > Transaction Layer Packet (TLP) there is 30 bytes overhead (4 PHY + 6 >> DLL + >> >> > 16 header + 4 ECRC). So for 1 rx packet dma sends 30 + 64(packet >> itself) + >> >> > 30 + 32 (writeback descriptor) + (16 / 4) (read request for new >> >> > descriptors). Note that we do not take into account PCIe ACK/NACK/FC >> Update >> >> > DLLP. So we have 160 bytes per packet. One lane PCIe 3.0 transmits 1 >> byte in >> >> > 1 ns, so x8 transmits 8 bytes in 1 ns. 1 packet transmits in 20 ns. >> Thus >> >> > in theory pcie 3.0 x8 may transfer not more than 50mpps. >> >> > Correct me if I'm wrong. >> >> > >> >> > Regards, >> >> > Vladimir >> >> > >> >> > >> >> >> >> -- >> Sincerely yours, Pavel Odintsov >>