From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5F20DA0C48; Thu, 8 Jul 2021 15:51:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D2D5241602; Thu, 8 Jul 2021 15:51:30 +0200 (CEST) Received: from mail-io1-f51.google.com (mail-io1-f51.google.com [209.85.166.51]) by mails.dpdk.org (Postfix) with ESMTP id 6CE4540696 for ; Thu, 8 Jul 2021 15:51:29 +0200 (CEST) Received: by mail-io1-f51.google.com with SMTP id b1so8262825ioz.8 for ; Thu, 08 Jul 2021 06:51:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=T5InNVUkyOdah130M+MGj9/mId4pf23b2H3YpOESVdI=; b=Q3DjauNi6Y9Twn1p/y+8MLnEv0w3EEXAkrlGrbsPpTLBOgWlDo4v/jBcgMGU6zUVb3 NXw6TZY4nBEZE2XswBunt/ywk+AtUtzIUU87kh67d4YpXNk571G7Sa1NT1pIuXvfRgco 9CKZKk/eQZLIBplZizL7SNdrPW4tmTvNQiJUk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=T5InNVUkyOdah130M+MGj9/mId4pf23b2H3YpOESVdI=; b=DrGNmpYF7BYH43QA8YgdroLuWMprvwtq5bthVsNJ5e/5bekCXwRaM3h3dPeIQrUoxQ aZJIbqPvealPI5NO+fbolFXVZoyNUntz7lW0g/k5bx2cL2giFROzl0j7QrQgq5tkVz7a vg+zM8a7UBWc3MFG4lSXMbQVEINSQNvN4gYo1Rhn+XFERqVYRbuzLObCdGLC2ePHPSbo Lq4PRAprHKIdwD5ittEtzlRT0dhc44e4DXhFJP3mjf4UcajZcTM2Vewe7ndrmcXrc3fi INpXrmr5wOJ2jx4Rd31SRXHlUsZ1/7W6IzDDNzCEiY9Y/sTLKcmGRugwnwa1rlwVGS65 alng== X-Gm-Message-State: AOAM530n9vu2XQL/hI/G2OMl9a+K8VL14Q2bKglofbtGxI+mPHwNMTk7 LVL6Q70dST3KaCKGIgZjaJSPV8spjwY49I0qnWLgNQ== X-Google-Smtp-Source: ABdhPJwDR86Fd613r94fKUlndCPtJsHCplGzgCmu1epaL4R8elyjRucYYM9jev9tKFTzoojTbqvTGdU8gGrjgO3LcL4= X-Received: by 2002:a6b:ec07:: with SMTP id c7mr5737403ioh.115.1625752288563; Thu, 08 Jul 2021 06:51:28 -0700 (PDT) MIME-Version: 1.0 References: <20210604073405.14880-1-joyce.kong@arm.com> <20210706065404.25137-1-joyce.kong@arm.com> <20210706065404.25137-3-joyce.kong@arm.com> <061d231c5ff848a19be50a62aed44087@intel.com> In-Reply-To: <061d231c5ff848a19be50a62aed44087@intel.com> From: Lance Richardson Date: Thu, 8 Jul 2021 09:51:17 -0400 Message-ID: To: "Zhang, Qi Z" Cc: Joyce Kong , "Xing, Beilei" , "ruifeng.wang@arm.com" , "honnappa.nagarahalli@arm.com" , "Richardson, Bruce" , "Zhang, Helin" , "dev@dpdk.org" , "stable@dpdk.org" , "nd@arm.com" Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="000000000000ad7e4405c69cf3aa" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: Re: [dpdk-dev] [PATCH v3 2/2] net/i40e: replace SMP barrier with thread fence X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" --000000000000ad7e4405c69cf3aa Content-Type: text/plain; charset="UTF-8" On Thu, Jul 8, 2021 at 8:09 AM Zhang, Qi Z wrote: > > > > > -----Original Message----- > > From: Joyce Kong > > Sent: Tuesday, July 6, 2021 2:54 PM > > To: Xing, Beilei ; Zhang, Qi Z ; > > ruifeng.wang@arm.com; honnappa.nagarahalli@arm.com; Richardson, Bruce > > ; Zhang, Helin > > Cc: dev@dpdk.org; stable@dpdk.org; nd@arm.com > > Subject: [PATCH v3 2/2] net/i40e: replace SMP barrier with thread fence > > > > Simply replace the SMP barrier with atomic thread fence for i40e hw ring sacn, > > if there is no synchronization point. > > > > Signed-off-by: Joyce Kong > > Reviewed-by: Ruifeng Wang > > --- > > drivers/net/i40e/i40e_rxtx.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index > > 9aaabfd92..86e2f083e 100644 > > --- a/drivers/net/i40e/i40e_rxtx.c > > +++ b/drivers/net/i40e/i40e_rxtx.c > > @@ -482,7 +482,8 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) > > I40E_RXD_QW1_STATUS_SHIFT; > > } > > > > - rte_smp_rmb(); > > + /* This barrier is to order loads of different words in the descriptor */ > > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); > > Now for x86, you actually replace a compiler barrier with a memory fence, this may have potential performance impact which need additional resource to investigate No memory fence instruction is generated for __ATOMIC_ACQUIRE on x86 for any version of gcc or clang that I've tried, based on experiments here: https://godbolt.org/z/Yxr1vGhKP --000000000000ad7e4405c69cf3aa--