From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 178EAA0568; Wed, 11 Mar 2020 10:38:50 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 32BE91BFFF; Wed, 11 Mar 2020 10:38:49 +0100 (CET) Received: from us-smtp-delivery-1.mimecast.com (us-smtp-1.mimecast.com [205.139.110.61]) by dpdk.org (Postfix) with ESMTP id DA74D1BFF7 for ; Wed, 11 Mar 2020 10:38:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1583919527; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=z8PoDYAy5kRcELfUwrRdd78yjuTO/Y+jo3/dfkk+vA4=; b=esdYAyfkHL7F/B6UR7jhWKCaQppr/lTmq2xTPuhhMWDy2/svlOAJc09HsOvheefXWGdZgP zE2WQApRExa9HMax8UJXuWAnCDmWOh4ET7ROg64bZvTeLnZepSh3hdFCZWwssV8i4XAi9Y Q94IGtc2mTbDu4zPUSkxz6ZJ2vWV424= Received: from mail-vk1-f200.google.com (mail-vk1-f200.google.com [209.85.221.200]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-46-3P4cc7JMPkOzdCe-KItLYw-1; Wed, 11 Mar 2020 05:38:43 -0400 X-MC-Unique: 3P4cc7JMPkOzdCe-KItLYw-1 Received: by mail-vk1-f200.google.com with SMTP id n8so698589vke.13 for ; Wed, 11 Mar 2020 02:38:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0Hvge+4JpJE/WhlbQqErOUhfhdlXJNWaBGCYpAMrJvs=; b=iqy9XKV+PGt+fLuhnJ9Ck2NobgbyvyriBlj1FfPXc3L7EIw1T6vKjl0uhuBeXWCDRG +zhc+6w3sJNJmu/no0ML2nvH9VCB+cuLS9OS2QB1SGEz5SZ7HtVZNL5vC6vBH8FG/1fG 6S3BM3CiVJAxTKmOVtS+0lb9MTBXyUDl71GvVar9LIBKmTsenQti2VFIrPk11sP59w1I Tr3LTL9oWMYwYRNu+BYR2mIhfB9DHe/24nNQvUVx1/wzEem/Ri7Cgeuqmo3rcQjeUn8B BKpEDpUEJuW1LrYRA1Rd0kyvntsElah8CVxyu7oMvauyYC6L/Ih+P1Y0ebLFitG6qTF8 +W6A== X-Gm-Message-State: ANhLgQ23v81LqVuBkbBKcooqyoTzRAlGV9R2duE63uMGOq0/ju6kj2kV q4G7larEK13+lq5xOWn40GVdZGMHmn7XSxP5MOvOdUr7914/VuTbB8FrM4RVJOLiBlaWVFJFEfX guJA4pAuCW8YoYh3bgFQ= X-Received: by 2002:a67:69d8:: with SMTP id e207mr1398537vsc.141.1583919523222; Wed, 11 Mar 2020 02:38:43 -0700 (PDT) X-Google-Smtp-Source: ADFU+vshUXxoprXCo2otT4i187a4p4BCo3bd336Pibm05sn16SA08ZhwqNvUuzf83vf02hjWIxuvfrMdzeZZdNTGfHs= X-Received: by 2002:a67:69d8:: with SMTP id e207mr1398523vsc.141.1583919522891; Wed, 11 Mar 2020 02:38:42 -0700 (PDT) MIME-Version: 1.0 References: <4099DE2E54AFAD489356C6C9161D53339729FAD0@DGGEML502-MBX.china.huawei.com> In-Reply-To: <4099DE2E54AFAD489356C6C9161D53339729FAD0@DGGEML502-MBX.china.huawei.com> From: David Marchand Date: Wed, 11 Mar 2020 10:38:31 +0100 Message-ID: To: Linhaifeng Cc: Jerin Jacob , Gavin Hu , "dev@dpdk.org" , "thomas@monjalon.net" , chenchanghu , xudingke , "Lilijun (Jerry)" , Honnappa Nagarahalli , Steve Capper , nd X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v6] eal/arm64: fix rdtsc precise version X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Mar 11, 2020 at 8:24 AM Linhaifeng wrote: > > In order to get more accurate the cntvct_el0 reading, > SW must invoke isb and arch_counter_enforce_ordering. > > Reference of linux kernel: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/ > linux.git/tree/arch/arm64/include/asm/arch_timer.h?h=3Dv5.5#n220 > > Fixes: ccad39ea0712 ("eal/arm: add cpu cycle operations for ARMv8") > Cc: stable@dpdk.org > > Reviewed-by: Jerin Jacob > Reviewed-by: Gavin Hu > Signed-off-by: Haifeng Lin > --- > .../common/include/arch/arm/rte_cycles_64.h | 26 +++++++++++++++++-- > 1 file changed, 24 insertions(+), 2 deletions(-) > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h b/lib= /librte_eal/common/include/arch/arm/rte_cycles_64.h > index 68e7c7338..6b0df5b0a 100644 > --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > @@ -59,11 +59,33 @@ rte_rdtsc(void) > } > #endif > > +static inline void > +isb(void) > +{ > + asm volatile("isb" : : : "memory"); > +} NAK. Don't export badly named stuff like this. > + > +static inline void > +__rte_arm64_cntvct_el0_enforce_ordering(uint64_t val) > +{ > + uint64_t tmp; > + > + asm volatile( > + " eor %0, %1, %1\n" > + " add %0, sp, %0\n" > + " ldr xzr, [%0]" > + : "=3Dr" (tmp) : "r" (val)); > +} > + I can see no point in exporting this. Please move this inline of rte_rdtsc_precise(). If one day, ARM needs this elsewhere, we can reevaluate and introduce a helper, but I don't see this atm. > static inline uint64_t > rte_rdtsc_precise(void) > { > - rte_mb(); > - return rte_rdtsc(); > + uint64_t tsc; > + > + isb(); > + tsc =3D rte_rdtsc(); > + __rte_arm64_cntvct_el0_enforce_ordering(tsc); > + return tsc; > } > > static inline uint64_t > -- > 2.24.1.windows.2 > --=20 David Marchand