From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 757CBA054F; Mon, 15 Mar 2021 15:16:35 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E3B944068C; Mon, 15 Mar 2021 15:16:34 +0100 (CET) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mails.dpdk.org (Postfix) with ESMTP id B308940687 for ; Mon, 15 Mar 2021 15:16:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1615817793; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Xe+MP6SS9sXdsU8oZy22sNPO8AVE7Lx/+Gc4YccBM4Q=; b=iY91l2H8vDRTYuTDZXFQIi481c84w7NiAT3axgOJt+yT3/du1GdAknSfGw1iymtNZIdkvC G8I6MtWIx6Oe5znyr8Yw9PwFFgFT7nYd/JprSzVq7PhHvvUemdqaeDdt+eyR5yhF7fVbPs MITDj3aKM0bjMm2jH7dxwJcgRrZJLEE= Received: from mail-vs1-f69.google.com (mail-vs1-f69.google.com [209.85.217.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-559-x05uciJuPRm8NRNbqNs2Jw-1; Mon, 15 Mar 2021 10:16:31 -0400 X-MC-Unique: x05uciJuPRm8NRNbqNs2Jw-1 Received: by mail-vs1-f69.google.com with SMTP id 125so5340602vsj.0 for ; Mon, 15 Mar 2021 07:16:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=Xe+MP6SS9sXdsU8oZy22sNPO8AVE7Lx/+Gc4YccBM4Q=; b=Vhm00RhxM4fVFZ4WuiuYdXB8D8xJ/CiON1OJt0AwBWy0eid2AmSdq0YrXXoqLgF0BG qCjxUx1r4H69/GotS/e4a7ebOK6WH6855Emf0S/pMdJZ/ErSusq7YxWpxwXRSIPmDRJs sQd9GO+QebHi6FMKwGlFsb1gzBa8W4w+i9wmf6ibjsEb/MKlKERhW0+UP2wu6+dNT7KL ZFoRZli3L6GYg+ojrzrHw+D38HU7DwJrp/EX8e3HDSWZG98Cmwqd/8AvBhKAcVickPSZ yi8nCopBpYy3lMPDZpbA75/lRwL2tKusxv6acQa+Wj9yogWoSqQHX3QQrBGOwc/mZtFe cPFA== X-Gm-Message-State: AOAM533nvFUbZXaRcfR7bHghyKLSrVbALqmt4V5+16w8Jm/7fyM9Z3lh fjGlvpEcMxVm127cNa7jt1L7ldteM4kCZNgGrItTxwRws5RjYioUQQs7bzpgkUicubvfJRklzJf Myp16MHjfYKevCgghAtk= X-Received: by 2002:a9f:2722:: with SMTP id a31mr4895704uaa.86.1615817790982; Mon, 15 Mar 2021 07:16:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7p8lK5kK/gs5r/0xNUrNvggkj0jsawWGAvZ4DHIqXDnuS9CPef3YIj4nQ7nJ6RNU1FvCMUM05BHpW7JCGgOk= X-Received: by 2002:a9f:2722:: with SMTP id a31mr4895671uaa.86.1615817790732; Mon, 15 Mar 2021 07:16:30 -0700 (PDT) MIME-Version: 1.0 References: <1614797225-114594-1-git-send-email-huawei.xhw@alibaba-inc.com> <1615397790-16169-1-git-send-email-huawei.xhw@alibaba-inc.com> In-Reply-To: <1615397790-16169-1-git-send-email-huawei.xhw@alibaba-inc.com> From: David Marchand Date: Mon, 15 Mar 2021 15:16:19 +0100 Message-ID: To: =?UTF-8?B?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?= Cc: Maxime Coquelin , "Yigit, Ferruh" , dev , "Burakov, Anatoly" , xuemingl@nvidia.com, Gaetan Rivet , "Wang, Yinan" , "Wang, Haiyue" Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dmarchan@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v11 0/2] support both PIO and MMIO BAR for legacy virito device X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Mar 10, 2021 at 6:37 PM =E8=B0=A2=E5=8D=8E=E4=BC=9F(=E6=AD=A4=E6=97= =B6=E6=AD=A4=E5=88=BB=EF=BC=89 wrote: > > virtio PMD assumes legacy device only supports PIO(port-mapped) BAR > resource. This is wrong. As we need to create lots of devices, adn PIO > resource on x86 is very limited, we expose MMIO(memory-mapped I/O) BAR. > > Kernel supports both PIO and MMIO BAR for legacy virtio-pci device, and > for all other pci devices. This patchset handles different type of BAR in > the similar way. > > In previous implementation, under igb_uio driver we get PIO address from > igb_uio sysfs entry; with uio_pci_generic, we get PIO address from > /proc/ioports for x86, and for other ARCHs, we get PIO address from > standard PCI sysfs entry. For PIO/MMIO RW, there is different path for > different drivers and arch. > > All of the above is too much twisted. This patchset unifies the way to ge= t > both PIO and MMIO address for different driver and ARCHs, all from standa= rd > resource attr under pci sysfs. This is most generic. > > We distinguish PIO and MMIO by their address range like how kernel does. > It is ugly but works. > > v2 changes: > - add more explanation in the commit message > > v3 changes: > - fix patch format issues > > v4 changes: > - fixes for RTE_KDRV_UIO_GENERIC -> RTE_PCI_KDRV_UIO_GENERIC > > v5 changes: > - split into three seperate patches > > v6 changes: > - change to DEBUG level for IO bar detection in pci_uio_ioport_map > - rework the code in iobar branch > - fixes commit message format issue > - temporarily remove the 3rd patch for vfio path, leave it for future= discusssion > - rework against virtio_pmd_rework_v2 > > v7 changes: > - fix compilation issues of in/out instruction on non X86 archs > > v8 changes: > - change the word fix to refactor in patch 1's commit message > > v9 changes: > - keep pause version in in/out instructions > > v10 changes: > - trival fixes in commit message, like > 75 chars > > v11 changes: > - commit message fix and change > Aligned Sob and Author to fix the last checkpatch warning. Series applied to the main branch. Thanks Huawei and thanks too to reviewers/testers. --=20 David Marchand