Re: [PATCH v7 1/2] bus/pci: support PASID control

[David Marchand <david.marchand@redhat.com>]

Hello,

On Mon, Nov 6, 2023 at 7:50 PM Sevincer, Abdullah
<abdullah.sevincer@intel.com> wrote:
> Hi David,
> >++       pasid_offset = rte_pci_find_ext_capability(dev,
> >+RTE_PCI_EXT_CAP_ID_PASID);
>
> That  rte_pci_find_ext_capability() api does not work for PASID since PASID is not exposed to user from kernel.
> So, we can not retrieve offset. Instead we came up with a solution that passes an offset to an internal function to disable PASID and make the function internal so we can change it later.
> When the linux limitation is lifted we can re-write the functions and use rte_pci_find_ext_capability api to retrieve offset and your
> solution above can be done.

Adding PCI bus maintainers, Chenbo and Nipun.

Ok, that is indeed an issue.
I found some patches exposing this capability with vfio-pci but I am
not sure what is the latest work on the topic.
Do you have pointers to the latest kernel patches?


In any case, even if, in the future, the kernel exposes this
capability, we need to live with the current behavior (and probably
for a long time).
As the discovery of pasid offset is not possible, the common API merit
is low, but at least it shows what is being done by the driver.

Can we make a change so that this new API takes only the offset to the
pasid *structure* and not to the exact register controlling the
feature?
It should be something like:

$ git diff
diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c
index ba5e280d33..c66cefcd63 100644
--- a/drivers/bus/pci/pci_common.c
+++ b/drivers/bus/pci/pci_common.c
@@ -943,9 +943,9 @@ rte_pci_pasid_set_state(const struct rte_pci_device *dev,
                off_t offset, bool enable)
 {
        uint16_t pasid = enable;
-       return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0
-               ? -1
-               : 0;
+
+       return rte_pci_write_config(dev, &pasid, sizeof(pasid),
+               offset + RTE_PCI_PASID_CTRL) < 0 ? -1 : 0;
 }

 struct rte_pci_bus rte_pci_bus = {
diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
index f07bf9b588..b1d17996cb 100644
--- a/drivers/bus/pci/rte_bus_pci.h
+++ b/drivers/bus/pci/rte_bus_pci.h
@@ -161,9 +161,12 @@ int rte_pci_set_bus_master(const struct
rte_pci_device *dev, bool enable);
  * @param dev
  *   A pointer to a rte_pci_device structure.
  * @param offset
- *   Offset of the PASID external capability.
+ *   Offset of the PASID external capability structure.
  * @param enable
  *   Flag to enable or disable PASID.
+ *
+ *  @return
+ *  0 on success, -1 on error in PCI config space read/write.
  */
 __rte_internal
 int rte_pci_pasid_set_state(const struct rte_pci_device *dev,
diff --git a/drivers/event/dlb2/pf/dlb2_main.c
b/drivers/event/dlb2/pf/dlb2_main.c
index 61a7b39eef..a95d3227a4 100644
--- a/drivers/event/dlb2/pf/dlb2_main.c
+++ b/drivers/event/dlb2/pf/dlb2_main.c
@@ -518,8 +518,8 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
        /* Disable PASID if it is enabled by default, which
         * breaks the DLB if enabled.
         */
-       off = DLB2_PCI_PASID_CAP_OFFSET + RTE_PCI_PASID_CTRL;
-       if (rte_pci_pasid_set_state(pdev, off, false)) {
+       off = DLB2_PCI_PASID_CAP_OFFSET;
+       if (rte_pci_pasid_set_state(pdev, off, false) < 0) {
                DLB2_LOG_ERR("[%s()] failed to write the pcie config
space at offset %d\n",
                                __func__, (int)off);
                return -1;
diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
index 0d2d8d8fed..94219792de 100644
--- a/lib/pci/rte_pci.h
+++ b/lib/pci/rte_pci.h
@@ -101,7 +101,7 @@ extern "C" {
 #define RTE_PCI_EXT_CAP_ID_ACS         0x0d    /* Access Control Services */
 #define RTE_PCI_EXT_CAP_ID_SRIOV       0x10    /* SR-IOV */
 #define RTE_PCI_EXT_CAP_ID_PRI         0x13    /* Page Request Interface */
-#define RTE_PCI_EXT_CAP_ID_PASID       0x1B    /* Process Address Space ID */
+#define RTE_PCI_EXT_CAP_ID_PASID       0x1b    /* Process Address Space ID */

 /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */
 #define RTE_PCI_ERR_UNCOR_STATUS       0x04    /* Uncorrectable Error Status */



-- 
David Marchand