From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6EABA0546; Tue, 27 Apr 2021 11:28:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 96E4340150; Tue, 27 Apr 2021 11:28:46 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mails.dpdk.org (Postfix) with ESMTP id E893C4003E for ; Tue, 27 Apr 2021 11:28:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1619515725; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=3YDiO3Pim1tjcScPggPnCHeqQb31ENUSjOsGbluPuYo=; b=Cru3M3Y6mCLt3VojBlfcumHJ7O8C8XGrcysU6Oii1fkZNx3ALOChkA7eJehW6UM212Acnr 1rawJdo3WB2F7vaPQyHCay1X4pz/3qEj0N3PM4sOGU2/O4iKZiH4VPpUWf9VZXZj8+krWr wkq8A2bZbiuGRTcYmdZFZqNYz8PrL3c= Received: from mail-vs1-f72.google.com (mail-vs1-f72.google.com [209.85.217.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-242-HwFDP-utPOWgAul91oQG2A-1; Tue, 27 Apr 2021 05:28:43 -0400 X-MC-Unique: HwFDP-utPOWgAul91oQG2A-1 Received: by mail-vs1-f72.google.com with SMTP id d1-20020a67e1010000b0290221de2c5f91so9192083vsl.23 for ; Tue, 27 Apr 2021 02:28:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=3YDiO3Pim1tjcScPggPnCHeqQb31ENUSjOsGbluPuYo=; b=qPhJAkDyfjT1t9uUAoUjG0deWmW2nxqdJF4LUdYRl31ubtUTWnXiC0EWRDVknrau6v Y7aHsVP4I+R/Y0NrYhThnnKuU6rkIYOqNiwC5Ip/sy7Q0xH8CulwfNXnxBGnCgFwgjHE dzeKc445ar5PSHNa2aaJt2+dXz4xxPdWhBy7F5GwEDzUuaJ/8YXM5OBgWyRALe5/UY+z AwibiqwaJrya8QBgL+MaLmlp6DMWQAL4tNWInTIyZFmBxD3yDjdNEpO6cmTINZgoe43s Rp5zCMjoiKDAn4xOSKGbAXAsewGgPv+U5Fwp2h3nparXiVUgVgMJE+tEYMROYMDP/5bs f4Dg== X-Gm-Message-State: AOAM53150i/oOJEToPryuJ+v1p+fEG5rlhsMRd6tyidErbJ2AoBV25KB zHOADlaFvQFO8KMI7NXzKoSPe1AZCmEpWG+836eE+6w7Ptlamo2qP/ucI2C8AD05QFb2kclZOFb Cm+JCSC62G3ucy+XHZmY= X-Received: by 2002:a67:fdd8:: with SMTP id l24mr7185115vsq.18.1619515723186; Tue, 27 Apr 2021 02:28:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwu/vgRGO9DBdxs7Zqd204FNYURPFzC7Fz709mx9hOX4MBGIfyAk9zNPihW2z1I3qa79Kilty6ztDoBOqaybNk= X-Received: by 2002:a67:fdd8:: with SMTP id l24mr7185095vsq.18.1619515722898; Tue, 27 Apr 2021 02:28:42 -0700 (PDT) MIME-Version: 1.0 References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210423114001.174723-1-haiyue.wang@intel.com> <20210423114001.174723-2-haiyue.wang@intel.com> In-Reply-To: <20210423114001.174723-2-haiyue.wang@intel.com> From: David Marchand Date: Tue, 27 Apr 2021 11:28:31 +0200 Message-ID: To: Haiyue Wang , Gaetan Rivet Cc: dev , Qi Zhang , liang-min.wang@intel.com, Ray Kinsella , Neil Horman Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dmarchan@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v3 1/3] bus/pci: enable PCI master in command register X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Apr 23, 2021 at 2:06 PM Haiyue Wang wrote: > diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h > index 64886b473..83caf477b 100644 > --- a/drivers/bus/pci/rte_bus_pci.h > +++ b/drivers/bus/pci/rte_bus_pci.h > @@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f); > __rte_experimental > off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap); > > +/** > + * Enables Bus Master for device's PCI command register. > + * > + * @param dev > + * A pointer to rte_pci_device structure. > + * > + * @return > + * 0 on success, -1 on error in PCI config space read/write. > + */ > +__rte_experimental > +int rte_pci_enable_bus_master(struct rte_pci_device *dev); I can see pci/vfio and net/hns3 has a similar helper to enable *and* disable bus master. I'd rather go with a "set" helper, and then we can clean existing drivers who had their own helper: drivers/bus/pci/linux/pci_uio.c drivers/bus/pci/linux/pci_vfio.c drivers/net/hns3/hns3_ethdev_vf.c > + > /** > * Register a PCI driver. > * > diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map > index f33ed0abd..9dbec12a0 100644 > --- a/drivers/bus/pci/version.map > +++ b/drivers/bus/pci/version.map > @@ -21,4 +21,7 @@ EXPERIMENTAL { > global: > > rte_pci_find_ext_capability; > + > + # added in 21.05 > + rte_pci_enable_bus_master; > }; > diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h > index a8f8e404a..1f33d687f 100644 > --- a/lib/pci/rte_pci.h > +++ b/lib/pci/rte_pci.h > @@ -32,6 +32,10 @@ extern "C" { > > #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */ > #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */ > +#define RTE_PCI_COMMAND 0x04 /* 16 bits */ This file uses tab for indent. > + > +/* PCI Command Register */ > +#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */ > > /* PCI Express capability registers */ > #define RTE_PCI_EXP_DEVCTL 8 /* Device Control */ > -- > 2.31.1 > -- David Marchand