From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 30285A0093; Mon, 3 Oct 2022 09:48:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2286D40695; Mon, 3 Oct 2022 09:48:34 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mails.dpdk.org (Postfix) with ESMTP id 3CAC740693 for ; Mon, 3 Oct 2022 09:48:32 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1664783311; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=KXpBlqTCm8qC+F8fVtCQN6u71NnM4FtimlchZNo3MR8=; b=Wx6eiXvRR5t8w1KeNrhSumbvr3AhSrRYfhl1VHW3CCJnD20n58uKqbk+ilMZRkrNC3s6Go 6rYwQ23+gCcyOOKOnUtS8VuxCpEHVvVfrLytgb22EFw4X1/tUYPOWWpxUUHrue/SArvsfq 0i0YMBeiGQvQSc+w2+pX+e0XaHkxCvk= Received: from mail-pg1-f197.google.com (mail-pg1-f197.google.com [209.85.215.197]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-619-Yi2ulKMcPE2GvLF_w8hnpw-1; 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Mon, 03 Oct 2022 00:48:29 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6CTrZ+Dr1fhdmu6+benYgXzbmu/laa1IlB5VsgIyCu4m7DGwjD7amuTUDYou5QtJHcNJjDotdLV7x8PA3qX68= X-Received: by 2002:a17:90a:428e:b0:205:d5fe:e0b3 with SMTP id p14-20020a17090a428e00b00205d5fee0b3mr10761289pjg.33.1664783309432; Mon, 03 Oct 2022 00:48:29 -0700 (PDT) MIME-Version: 1.0 References: <20220912160157.3642968-2-mpiszczek@ddn.com> <20220914134950.3675770-1-mpiszczek@ddn.com> In-Reply-To: <20220914134950.3675770-1-mpiszczek@ddn.com> From: David Marchand Date: Mon, 3 Oct 2022 09:48:18 +0200 Message-ID: Subject: Re: [PATCH v2] pci: read amd iommu virtual address width To: Michael Piszczek , Ferruh Yigit , Chandubabu Namburu , bhagyada.modali@amd.com, Sunil Uttarwar , andrew.boyer@amd.com Cc: dev@dpdk.org X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, Sep 15, 2022 at 8:40 AM Michael Piszczek wrote: > > Add code to read the virtual address width for AMD processors. > > Signed-off-by: Michael Piszczek > --- > drivers/bus/pci/linux/pci.c | 43 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c > index e521459870..0c6d79ca74 100644 > --- a/drivers/bus/pci/linux/pci.c > +++ b/drivers/bus/pci/linux/pci.c > @@ -4,6 +4,7 @@ > > #include > #include > +#include > > #include > #include > @@ -492,6 +493,38 @@ rte_pci_scan(void) > } > > #if defined(RTE_ARCH_X86) > + > +static uint64_t > +pci_device_amd_iommu_support_va(const struct rte_pci_addr *addr) > +{ > +#define RD_AMD_CAP_VASIZE_SHIFT 15 > +#define RD_AMD_CAP_VASIZE_MASK (0x7F << RD_AMD_CAP_VASIZE_SHIFT) > + > + char filename[PATH_MAX]; > + FILE *fp; > + uint64_t amd_cap_reg = 0; > + > + snprintf(filename, sizeof(filename), > + "%s/" PCI_PRI_FMT "/iommu/amd-iommu/cap", > + rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid, > + addr->function); > + > + fp = fopen(filename, "r"); > + if (fp == NULL) > + return 0; > + > + /* We have an Amd IOMMU */ > + if (fscanf(fp, "%" PRIx64, &amd_cap_reg) != 1) { > + RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename); > + fclose(fp); > + return 0; > + } > + > + fclose(fp); > + > + return ((amd_cap_reg & RD_AMD_CAP_VASIZE_MASK) >> RD_AMD_CAP_VASIZE_SHIFT) + 1; > +} > + > bool > pci_device_iommu_support_va(const struct rte_pci_device *dev) > { > @@ -501,6 +534,16 @@ pci_device_iommu_support_va(const struct rte_pci_device *dev) > char filename[PATH_MAX]; > FILE *fp; > uint64_t mgaw, vtd_cap_reg = 0; > + struct stat s; > + > + if (stat("/sys/class/iommu/ivhd2/amd-iommu", &s) == 0) { > + mgaw = pci_device_amd_iommu_support_va(addr); > + if (mgaw > 0) { > + rte_mem_set_dma_mask(mgaw); > + return true; > + } > + return false; > + } > > snprintf(filename, sizeof(filename), > "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap", > -- > 2.34.1 > Sorry, I picked you guys with @amd.com mail addresses. If there is someone with knowledge of this piece of AMD hw available, can this patch be reviewed? Thanks. -- David Marchand