From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4658A0C49; Tue, 20 Jul 2021 13:03:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4318B40689; Tue, 20 Jul 2021 13:03:31 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mails.dpdk.org (Postfix) with ESMTP id D66C940140 for ; Tue, 20 Jul 2021 13:03:29 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1626779008; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=KJUiBDeRcTyN59ZWnGA2MF6L7+dy/bxjowjU4fvNXek=; b=HXPf+zLenyhLRuMIhe9el6t2MGfLOB5DsOf6BFofcy7F7BEiL6jJbxcIgKAQIxLa5gXxkF pN5U/yX8zH/WYWpj4noZB5KmkBd1g7fyE2XLPlDhuqSq90vkiPfm9E++Ug3NqYMDVLBsw2 STcwHtu7fCcdD7AdtrATYUNuCG6f+v8= Received: from mail-vk1-f199.google.com (mail-vk1-f199.google.com [209.85.221.199]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-423-NKSIweWCMH2w1Epk4FIGKQ-1; Tue, 20 Jul 2021 07:03:27 -0400 X-MC-Unique: NKSIweWCMH2w1Epk4FIGKQ-1 Received: by mail-vk1-f199.google.com with SMTP id y3-20020ac5c8030000b0290258ad5d117cso3795326vkl.13 for ; Tue, 20 Jul 2021 04:03:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=KJUiBDeRcTyN59ZWnGA2MF6L7+dy/bxjowjU4fvNXek=; b=tbBGDFiB0ornXRTo0gtDa3T+80ohGrMlrhBYJaUyXLCJlCffdoGxQNrbd61QOutRxC 8oZn2OgaNCSif0jae8/i/mwzBeTp8Os2HK0MfNg2y+Ew946JfV6Ru9DOHE8pZvBegEbb ITcRvEd2AZjjlmqQrbHejR4YiNYpqOuFz75NlhYGQ42ZKXmTWZ0nh0Y4i1oBZWMHu4Aj Ftjhvj2HYeabT3TG+b5V+ddjVOCWjbalnXmAk1vGUURQtldJXZL788raQ2KWbLZoivP6 wyXduEJBZOitMpa7aZpi9JY1oiLxzx65r7l5lpNO1TF3yint3grIB0O0TGpOQ4jgM+te C6/A== X-Gm-Message-State: AOAM530MTH4QHuoBBjESxEYU2nB6Et/fHMpk5boBX1A6v/Aj9de5fpIS tKEQfCgvqo6U88gkA3PRMIigvqNQGZy7W5HFMAEUA96UBCF8e2vcdQb7nh5Wo8hjbk/0CFI+H+b /3wz+V3cY1p3FcPGfnF4= X-Received: by 2002:a67:f78a:: with SMTP id j10mr1293359vso.10.1626779005931; Tue, 20 Jul 2021 04:03:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxTwy3F1PFRiCR8DnS4bsdh4C/DTu9wDIkj30WeH2k+6SJP79wkSpTFIs7hj4EJXte7SVSEU9NWPrMdCvjxpBk= X-Received: by 2002:a67:f78a:: with SMTP id j10mr1293332vso.10.1626779005633; Tue, 20 Jul 2021 04:03:25 -0700 (PDT) MIME-Version: 1.0 References: <20210711232958.2191-1-pbhagavatula@marvell.com> <20210714090209.2744-1-pbhagavatula@marvell.com> <20210714090209.2744-2-pbhagavatula@marvell.com> In-Reply-To: <20210714090209.2744-2-pbhagavatula@marvell.com> From: David Marchand Date: Tue, 20 Jul 2021 13:03:14 +0200 Message-ID: To: Pavan Nikhilesh Cc: Jerin Jacob Kollanukkaran , Shijith Thotton , dev Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dmarchan@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v9 2/7] event/cnxk: add Rx adapter fastpath ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Jul 14, 2021 at 11:02 AM wrote: > > From: Pavan Nikhilesh > > Add support for event eth Rx adapter fastpath operations. > > Signed-off-by: Pavan Nikhilesh This patch triggers a build issue for arm64 cross compiling on my system with a 8.3 toolchain from Linaro. I ended up upgrading my toolchain (which solved the issue), but some users might hit this, so posting for info: [2813/2834] Compiling C object drivers/libtmp_rte_event_cnxk.a.p/event_cnxk_cn10k_worker_deq.c.o FAILED: drivers/libtmp_rte_event_cnxk.a.p/event_cnxk_cn10k_worker_deq.c.o aarch64-linux-gnu-gcc -Idrivers/libtmp_rte_event_cnxk.a.p -Idrivers -I../../dpdk/drivers -Idrivers/event/cnxk -I../../dpdk/drivers/event/cnxk -Ilib/eventdev -I../../dpdk/lib/eventdev -I. -I../../dpdk -Iconfig -I../../dpdk/config -Ilib/eal/include -I../../dpdk/lib/eal/include -Ilib/eal/linux/include -I../../dpdk/lib/eal/linux/include -Ilib/eal/arm/include -I../../dpdk/lib/eal/arm/include -Ilib/eal/common -I../../dpdk/lib/eal/common -Ilib/eal -I../../dpdk/lib/eal -Ilib/kvargs -I../../dpdk/lib/kvargs -Ilib/metrics -I../../dpdk/lib/metrics -Ilib/telemetry -I../../dpdk/lib/telemetry -Ilib/ring -I../../dpdk/lib/ring -Ilib/ethdev -I../../dpdk/lib/ethdev -Ilib/net -I../../dpdk/lib/net -Ilib/mbuf -I../../dpdk/lib/mbuf -Ilib/mempool -I../../dpdk/lib/mempool -Ilib/meter -I../../dpdk/lib/meter -Ilib/hash -I../../dpdk/lib/hash -Ilib/rcu -I../../dpdk/lib/rcu -Ilib/timer -I../../dpdk/lib/timer -Ilib/cryptodev -I../../dpdk/lib/cryptodev -Idrivers/bus/pci -I../../dpdk/drivers/bus/pci -I../../dpdk/drivers/bus/pci/linux -Ilib/pci -I../../dpdk/lib/pci -Idrivers/common/cnxk -I../../dpdk/drivers/common/cnxk -Ilib/security -I../../dpdk/lib/security -Idrivers/net/cnxk -I../../dpdk/drivers/net/cnxk -Idrivers/bus/vdev -I../../dpdk/drivers/bus/vdev -Idrivers/mempool/cnxk -I../../dpdk/drivers/mempool/cnxk -fdiagnostics-color=always -pipe -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch -Werror -O2 -g -include rte_config.h -Wextra -Wcast-qual -Wdeprecated -Wformat -Wformat-nonliteral -Wformat-security -Wmissing-declarations -Wmissing-prototypes -Wnested-externs -Wold-style-definition -Wpointer-arith -Wsign-compare -Wstrict-prototypes -Wundef -Wwrite-strings -Wno-packed-not-aligned -Wno-missing-field-initializers -D_GNU_SOURCE -fPIC -march=armv8-a+crc -DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API -Wno-format-truncation -flax-vector-conversions -Wno-strict-aliasing -DRTE_LOG_DEFAULT_LOGTYPE=pmd.event.cnxk -MD -MQ drivers/libtmp_rte_event_cnxk.a.p/event_cnxk_cn10k_worker_deq.c.o -MF drivers/libtmp_rte_event_cnxk.a.p/event_cnxk_cn10k_worker_deq.c.o.d -o drivers/libtmp_rte_event_cnxk.a.p/event_cnxk_cn10k_worker_deq.c.o -c ../../dpdk/drivers/event/cnxk/cn10k_worker_deq.c {standard input}: Assembler messages: {standard input}:1392: Error: reg pair must start from even reg at operand 1 -- `caspl x23,x24,x23,x24,[x2]' {standard input}:10473: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:15726: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:19146: Error: reg pair must start from even reg at operand 1 -- `caspl x9,x10,x9,x10,[x4]' {standard input}:28825: Error: reg pair must start from even reg at operand 1 -- `caspl x7,x8,x7,x8,[x3]' {standard input}:30845: Error: reg pair must start from even reg at operand 1 -- `caspl x27,x28,x27,x28,[x2]' {standard input}:34301: Error: reg pair must start from even reg at operand 1 -- `caspl x9,x10,x9,x10,[x3]' {standard input}:40152: Error: reg pair must start from even reg at operand 1 -- `caspl x7,x8,x7,x8,[x2]' {standard input}:44998: Error: reg pair must start from even reg at operand 1 -- `caspl x7,x8,x7,x8,[x2]' {standard input}:52457: Error: reg pair must start from even reg at operand 1 -- `caspl x27,x28,x27,x28,[x2]' {standard input}:58407: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:62121: Error: reg pair must start from even reg at operand 1 -- `caspl x7,x8,x7,x8,[x4]' {standard input}:64121: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:67572: Error: reg pair must start from even reg at operand 1 -- `caspl x11,x12,x11,x12,[x4]' {standard input}:69764: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:88814: Error: reg pair must start from even reg at operand 1 -- `caspl x27,x28,x27,x28,[x2]' {standard input}:92747: Error: reg pair must start from even reg at operand 1 -- `caspl x9,x10,x9,x10,[x4]' {standard input}:95490: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:99628: Error: reg pair must start from even reg at operand 1 -- `caspl x9,x10,x9,x10,[x2]' {standard input}:102765: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:115148: Error: reg pair must start from even reg at operand 1 -- `caspl x11,x12,x11,x12,[x4]' {standard input}:122005: Error: reg pair must start from even reg at operand 1 -- `caspl x11,x12,x11,x12,[x4]' {standard input}:140039: Error: reg pair must start from even reg at operand 1 -- `caspl x21,x22,x21,x22,[x2]' {standard input}:147676: Error: reg pair must start from even reg at operand 1 -- `caspl x21,x22,x21,x22,[x2]' {standard input}:154953: Error: reg pair must start from even reg at operand 1 -- `caspl x21,x22,x21,x22,[x2]' {standard input}:159334: Error: reg pair must start from even reg at operand 1 -- `caspl x9,x10,x9,x10,[x2]' {standard input}:162769: Error: reg pair must start from even reg at operand 1 -- `caspl x17,x18,x17,x18,[x2]' {standard input}:167453: Error: reg pair must start from even reg at operand 1 -- `caspl x11,x12,x11,x12,[x2]' {standard input}:171071: Error: reg pair must start from even reg at operand 1 -- `caspl x17,x18,x17,x18,[x2]' {standard input}:179105: Error: reg pair must start from even reg at operand 1 -- `caspl x23,x24,x23,x24,[x2]' {standard input}:186966: Error: reg pair must start from even reg at operand 1 -- `caspl x23,x24,x23,x24,[x2]' {standard input}:191653: Error: reg pair must start from even reg at operand 1 -- `caspl x11,x12,x11,x12,[x3]' {standard input}:195360: Error: reg pair must start from even reg at operand 1 -- `caspl x15,x16,x15,x16,[x3]' {standard input}:204312: Error: reg pair must start from even reg at operand 1 -- `caspl x15,x16,x15,x16,[x3]' {standard input}:209537: Error: reg pair must start from even reg at operand 1 -- `caspl x5,x6,x5,x6,[x2]' {standard input}:222601: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:228793: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:234946: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:240956: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:258235: Error: reg pair must start from even reg at operand 1 -- `caspl x5,x6,x5,x6,[x2]' {standard input}:264084: Error: reg pair must start from even reg at operand 1 -- `caspl x5,x6,x5,x6,[x2]' {standard input}:270355: Error: reg pair must start from even reg at operand 1 -- `caspl x7,x8,x7,x8,[x3]' {standard input}:272988: Error: reg pair must start from even reg at operand 1 -- `caspl x21,x22,x21,x22,[x2]' {standard input}:277045: Error: reg pair must start from even reg at operand 1 -- `caspl x7,x8,x7,x8,[x3]' {standard input}:279878: Error: reg pair must start from even reg at operand 1 -- `caspl x21,x22,x21,x22,[x2]' {standard input}:297340: Error: reg pair must start from even reg at operand 1 -- `caspl x9,x10,x9,x10,[x3]' {standard input}:304594: Error: reg pair must start from even reg at operand 1 -- `caspl x11,x12,x11,x12,[x3]' {standard input}:315184: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:322794: Error: reg pair must start from even reg at operand 1 -- `caspl x19,x20,x19,x20,[x2]' {standard input}:327357: Error: reg pair must start from even reg at operand 1 -- `caspl x9,x10,x9,x10,[x2]' {standard input}:335754: Error: reg pair must start from even reg at operand 1 -- `caspl x11,x12,x11,x12,[x2]' {standard input}:361049: Error: reg pair must start from even reg at operand 1 -- `caspl x9,x10,x9,x10,[x3]' {standard input}:364869: Error: reg pair must start from even reg at operand 1 -- `caspl x15,x16,x15,x16,[x2]' {standard input}:370062: Error: reg pair must start from even reg at operand 1 -- `caspl x11,x12,x11,x12,[x3]' {standard input}:374066: Error: reg pair must start from even reg at operand 1 -- `caspl x15,x16,x15,x16,[x2]' {standard input}:382804: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:391016: Error: reg pair must start from even reg at operand 1 -- `caspl x3,x4,x3,x4,[x2]' {standard input}:441361: Error: reg pair must start from even reg at operand 1 -- `caspl x11,x12,x11,x12,[x3]' -- David Marchand