From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C21164234A; Tue, 10 Oct 2023 11:00:06 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4A2FC40297; Tue, 10 Oct 2023 11:00:06 +0200 (CEST) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mails.dpdk.org (Postfix) with ESMTP id 3359D40278 for ; Tue, 10 Oct 2023 11:00:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1696928403; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NL+We8QEA4/4YYERVwOqnbVrB4Jv7EKh3q/kUa4c73c=; b=ZWIzPN1o44OWSDsv/IbHuW3Ce1byJtAMPz/gsqB3LFO4Ra2vhc4lb61xC1pAtkHl6P8TUn IMg/JJAUB/ZjNUR98gIqhjxxlifPp+H1hAPwnnicuOWO7bpkFFdFK+Q+mD43Pb0RH+OUCZ MkhW1pAmlUVuoKX+9ZWJzCNe7e3AtB8= Received: from mail-lj1-f198.google.com (mail-lj1-f198.google.com [209.85.208.198]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-608-hVrKTy3RNDCxuqKZemkUcA-1; Tue, 10 Oct 2023 05:00:01 -0400 X-MC-Unique: hVrKTy3RNDCxuqKZemkUcA-1 Received: by mail-lj1-f198.google.com with SMTP id 38308e7fff4ca-2bfeaf8cc4bso45435531fa.0 for ; Tue, 10 Oct 2023 02:00:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696928400; x=1697533200; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NL+We8QEA4/4YYERVwOqnbVrB4Jv7EKh3q/kUa4c73c=; b=G1K/B3tXfGDNAjohhjW2+Li8Io7fmdE/ervvoTFDqQHOCh0Wm09rvY6HS9U/MEm7D7 sSb7yRJkyX+qSaU/LbosiWqNEr0C1o57c4z0r6sw3CJZ6uYu7lfM0hLOY8dDIqO1H8VF HtLj10U2GCRyKOdT6G7o7v8dn+VgJxUrmhUEEn9x/8+k+Stn9PfXaR05BJrQk63BXOEH JAXL/powRSNvuvXNqML5u5CXf+BE9f0evsM7vzdpfPlKyPE4fnpP/Ew/X2ov5FzNSXo+ LhgPBJOBawX3767GXRK3OLPDwI+4QAvKwdzgCr7W5H/y0zYTf1ylZvGkL9i4I8IxlXxG NQmg== X-Gm-Message-State: AOJu0YwstJcjEC8dXagxZDxzdOc2PwW25coZwlHg4Guys2STNs2xcEQ7 Em82g1TfErc79wKvtER053EAj/nJHMxDK4TBrGeF+hlXjEReFf96ecmJq9Oq/G0/FkyhxCjgSLg FnI4kpI3QaLF2FTXyYTg= X-Received: by 2002:a2e:8099:0:b0:2bc:e470:1412 with SMTP id i25-20020a2e8099000000b002bce4701412mr14967700ljg.43.1696928400444; Tue, 10 Oct 2023 02:00:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH+lfd3pkAdoP5+LD2K6nj/WfOL8MD3dXdleqB5NSdfiIZVyNct5QK1Fa7CIbUaPSsgWVdKHOawgzNlEHti+YQ= X-Received: by 2002:a2e:8099:0:b0:2bc:e470:1412 with SMTP id i25-20020a2e8099000000b002bce4701412mr14967681ljg.43.1696928400096; Tue, 10 Oct 2023 02:00:00 -0700 (PDT) MIME-Version: 1.0 References: <20230816185959.1331336-3-sivaprasad.tummala@amd.com> <20231009140546.862553-1-sivaprasad.tummala@amd.com> <20231009140546.862553-3-sivaprasad.tummala@amd.com> In-Reply-To: <20231009140546.862553-3-sivaprasad.tummala@amd.com> From: David Marchand Date: Tue, 10 Oct 2023 10:59:48 +0200 Message-ID: Subject: Re: [PATCH v6 3/3] power: amd power monitor support To: Sivaprasad Tummala Cc: david.hunt@intel.com, konstantin.v.ananyev@yandex.ru, roretzla@linux.microsoft.com, anatoly.burakov@intel.com, thomas@monjalon.net, ferruh.yigit@amd.com, dev@dpdk.org X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hello Siva, On Mon, Oct 9, 2023 at 4:06=E2=80=AFPM Sivaprasad Tummala wrote: > > mwaitx allows EPYC processors to enter a implementation dependent > power/performance optimized state (C1 state) for a specific period > or until a store to the monitored address range. > > Signed-off-by: Sivaprasad Tummala > Acked-by: Anatoly Burakov > --- Please put some changelog to make life easier for reviewers (and me). I diffed with the previous version to check what had been changed and I see this: static void amd_mwaitx(const uint64_t timeout) ... - "c"(2), /* enable timer */ - "b"(timeout)); + "c"(0)); /* no time-out */ I will take this series as is, but please confirm why this change was neede= d. > lib/eal/x86/rte_power_intrinsics.c | 108 ++++++++++++++++++++++------- > 1 file changed, 84 insertions(+), 24 deletions(-) > > diff --git a/lib/eal/x86/rte_power_intrinsics.c b/lib/eal/x86/rte_power_i= ntrinsics.c > index 664cde01e9..0d2953f570 100644 > --- a/lib/eal/x86/rte_power_intrinsics.c > +++ b/lib/eal/x86/rte_power_intrinsics.c > @@ -17,6 +17,78 @@ static struct power_wait_status { > volatile void *monitor_addr; /**< NULL if not currently sleeping = */ > } __rte_cache_aligned wait_status[RTE_MAX_LCORE]; > > +/** > + * This functions uses UMONITOR/UMWAIT instructions and will enter C0.2 = state. Fixed while applying, function* > + * For more information about usage of these instructions, please refer = to > + * Intel(R) 64 and IA-32 Architectures Software Developer's Manual. > + */ > +static void intel_umonitor(volatile void *addr) > +{ > +#if defined(RTE_TOOLCHAIN_MSVC) || defined(__WAITPKG__) > + /* cast away "volatile" when using the intrinsic */ > + _umonitor((void *)(uintptr_t)addr); > +#else > + /* > + * we're using raw byte codes for compiler versions which > + * don't support this instruction natively. > + */ > + asm volatile(".byte 0xf3, 0x0f, 0xae, 0xf7;" > + : > + : "D"(addr)); > +#endif > +} > + > +static void intel_umwait(const uint64_t timeout) > +{ > + const uint32_t tsc_l =3D (uint32_t)timeout; > + const uint32_t tsc_h =3D (uint32_t)(timeout >> 32); > +#if defined(RTE_TOOLCHAIN_MSVC) || defined(__WAITPKG__) > + _umwait(tsc_l, tsc_h); > +#else > + asm volatile(".byte 0xf2, 0x0f, 0xae, 0xf7;" > + : /* ignore rflags */ > + : "D"(0), /* enter C0.2 */ > + "a"(tsc_l), "d"(tsc_h)); > +#endif > +} > + > +/** > + * This functions uses MONITORX/MWAITX instructions and will enter C1 st= ate. > + * For more information about usage of these instructions, please refer = to > + * AMD64 Architecture Programmer=E2=80=99s Manual. > + */ > +static void amd_monitorx(volatile void *addr) > +{ > +#if defined(__MWAITX__) This part probably breaks build with MSVC. I could not determine whether MSVC supports this intrinsic. I'll rely on Tyler to fix it later. Series applied. --=20 David Marchand