From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A1611A0503; Fri, 6 May 2022 11:14:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 42F1840395; Fri, 6 May 2022 11:14:06 +0200 (CEST) Received: from us-smtp-delivery-74.mimecast.com (us-smtp-delivery-74.mimecast.com [170.10.129.74]) by mails.dpdk.org (Postfix) with ESMTP id 718EA4014F for ; Fri, 6 May 2022 11:14:00 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1651828439; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=WKeD9qtdTVnMqD0y4lRPTokOfFZ7oBIYkiUWjQykeFk=; b=eUds3kbQOl4MQIQDHMD0g5SknyZCZED0rs4/iQVdYomcowgLG7/g7zz3iiz+GzrW30ZPFR MWyzGdvR0faChWNf6rONwW8/MXWnc4GfricXd6lwDLT2e0wH9NRiAZYFjARXTyPX7pKSv8 HNvb7AvbR4dYJK7JnFulm2NEF2BCZHg= Received: from mail-lj1-f199.google.com (mail-lj1-f199.google.com [209.85.208.199]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-93-jcMk26PmP3GFhvprgnWf7A-1; Fri, 06 May 2022 05:13:55 -0400 X-MC-Unique: jcMk26PmP3GFhvprgnWf7A-1 Received: by mail-lj1-f199.google.com with SMTP id f6-20020a2e9186000000b0024f3dfdf894so2126074ljg.2 for ; Fri, 06 May 2022 02:13:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=WKeD9qtdTVnMqD0y4lRPTokOfFZ7oBIYkiUWjQykeFk=; b=45RD1nVNMgwDBX4zUiAGcmyB17FgAWKQyb29byTZ/AzcPvkJjcK65oA1hpaVF9anHS mFm8xA4hh4nPXDjazWcG3Lzqymu6iAN+wYu+WjsRzGdGf0Ah7Ux++zt/Z8DOE0/Ca37t lA6rXfk75a9jnBFKbl8mQDxMzytJOuGv8ALhyPluLJtrM+luGw6xvJlz80ahwWwAQUuH FxYa0qG4Iw5NEGqsau16XkXhKGZoORX8OYv6sKtGbDfDtwyNboRWCK/ZJV2EzLa4jEIz C7J404Cm9cHNOJ8ibKbMccBaxwUBil1+fpywNA/a5y5nCNm+Xzp8lJwWBXeVzr9tf4WH 0Pyw== X-Gm-Message-State: AOAM532jx1w9Fd9QfdNDHYpCvC20FxAe6bnXj/HofTa7s5Rxq7rCBCnJ 1a0kVX0jYn141xWdCgQybsggfui0xoSAx+ZeogXOp7xJeA3jUz6Bnm4irsJgvGCWI+dPJtuF1Po 6lVfaNKR8/bKdqgz5HXs= X-Received: by 2002:a05:6512:3f8c:b0:45d:cb2a:8779 with SMTP id x12-20020a0565123f8c00b0045dcb2a8779mr1922579lfa.499.1651828431550; Fri, 06 May 2022 02:13:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz56VHoD1Y1B0O+N65Ia86/OZ+RZgxoUKKxuCl7fCCpCNP/LG38sFmenwe9LEBi+t5hSPRG1O3FFLkLMMcDSUY= X-Received: by 2002:a05:6512:3f8c:b0:45d:cb2a:8779 with SMTP id x12-20020a0565123f8c00b0045dcb2a8779mr1922562lfa.499.1651828431241; Fri, 06 May 2022 02:13:51 -0700 (PDT) MIME-Version: 1.0 References: <20220505173003.3242618-1-kda@semihalf.com> In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> From: David Marchand Date: Fri, 6 May 2022 11:13:40 +0200 Message-ID: Subject: Re: [PATCH 00/11] Introduce support for RISC-V architecture To: Stanislaw Kardach Cc: dev , Frank Zhao , Sam Grove , Marcin Wojtas , upstream@semihalf.com, Thomas Monjalon , Stephen Hemminger Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dmarchan@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, May 5, 2022 at 7:30 PM Stanislaw Kardach wrote: > > This patchset adds support for building and running DPDK on 64bit RISC-V > architecture. The initial support targets rv64gc (rv64imafdc) ISA and > was tested on SiFive Unmatched development board with the Freedom U740 > SoC running Linux (freedom-u-sdk based kernel). > I have tested this codebase using DPDK unit and perf tests as well as > test-pmd, l2fwd and l3fwd examples. > The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD. > On the UIO side, since U740 does not have an IOMMU, I've used igb_uio, > uio_pci_generic and vfio-pci noiommu drivers. > > Commits 1-2 fix small issues which are encountered if a given platform > does not support any vector operations (which is the case with U740). > Commit 3 introduces EAL and build system support for RISC-V architecture > as well as documentation updates. > Commits 4-7 add missing defines and stubs to enable RISC-V operation in > non-EAL parts. > Commit 8 adds RISC-V specific cpuflags test. > Commit 9 works around a bug in the current GCC in test_ring compiled > with -O0 or -Og. > Commit 10 adds RISC-V testing to test-meson-builds.sh automatically > iterating over cross-compile config files (currently present for > generic rv64gc and SiFive U740). > Commit 11 extends hash r/w perf test by displaying both HTM and non-HTM > measurements. This is an extraneous commit which is not directly > needed for RISC-V support but was noticed when we have started > gathering test results. If needed, I can submit it separately. > > I appreciate Your comments and feedback. Thanks for working on this! Please add a cross compilation job to GHA, something like: https://github.com/david-marchand/dpdk/commit/4023e28f9050b85fb138eba14068bfe882036f01 Which looks to run fine: https://github.com/david-marchand/dpdk/runs/6319625002?check_suite_focus=true Testing all riscv configs in test-meson-buils.sh seems too much to me. Is there a real value to test both current targets? About the new "Sponsored-by" tag, it should not raise warnings in the CI if we agree on its addition. devtools/check-meson.py caught coding style issues. In general, please avoid letting arch specific headers leak internal/non rte_ prefixed helpers out of them. For example, I noticed a RV64_CSRR macro that can be undefined after usage. Patch 3 is huge, not sure it is easy to split, did you consider doing so? The release notes update is verbose and some parts could be dropped, like the list of verifications that are fine in a series cover letter. Please resubmit fixes separately from this series so that we can merge them sooner than this series. -- David Marchand