From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 443D4A057C; Fri, 27 Mar 2020 13:24:31 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EC7781C117; Fri, 27 Mar 2020 13:24:29 +0100 (CET) Received: from us-smtp-delivery-74.mimecast.com (us-smtp-delivery-74.mimecast.com [216.205.24.74]) by dpdk.org (Postfix) with ESMTP id 8D7E11C10E for ; Fri, 27 Mar 2020 13:24:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1585311867; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lUqiv/SPsFssLF+4IbOJ4JZy9XxcDLDKeJmKd6T+4kg=; b=IvV1IyVq/sO2j8Up4vvqD6/uXRBx8uY64KtugphtnjWE+nRcB2bRjQG4v0ZzmRY7SUDVPl GJSXxuqT97d/MRhopKXcL/M32Q1Nh2mu0yI1T/Ve+/2g4BLzhyd/s7r8knzUBZa/2wZVx1 /8TpVqksyeC9YOwHIp6lztPERxHxwpA= Received: from mail-vk1-f197.google.com (mail-vk1-f197.google.com [209.85.221.197]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-443-NRBCRbO6OuyvXAXumuR08g-1; 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Fri, 27 Mar 2020 05:24:23 -0700 (PDT) X-Google-Smtp-Source: ADFU+vvjsGfejyo2uj3edc5IMzeqobLNz61VlGTtupON9E83wirawWWhOjx/RAND44S1zyr6otJPhA9yOgh8Po+Xf7w= X-Received: by 2002:a67:2c81:: with SMTP id s123mr10315158vss.198.1585311863340; Fri, 27 Mar 2020 05:24:23 -0700 (PDT) MIME-Version: 1.0 References: <20200324114921.7184-1-kevin.laatz@intel.com> <20200325111016.29163-1-kevin.laatz@intel.com> In-Reply-To: <20200325111016.29163-1-kevin.laatz@intel.com> From: David Marchand Date: Fri, 27 Mar 2020 13:24:12 +0100 Message-ID: To: Kevin Laatz Cc: dev , Bruce Richardson , Van Haaren Harry , Neil Horman , Thomas Monjalon , Honnappa Nagarahalli , Dodji Seketeli X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Mar 25, 2020 at 12:11 PM Kevin Laatz wrote: > > This patch adds CPU flags which will enable the detection of ISA > features available on more recent x86 based CPUs. > > The CPUID leaf information can be found in Section 1.7 of this > document: > https://software.intel.com/sites/default/files/managed/c5/15/architecture= -instruction-set-extensions-programming-reference.pdf > > The following CPU flags are added in this patch: > - AVX-512 doubleword and quadword instructions. > - AVX-512 integer fused multiply-add instructions. > - AVX-512 conflict detection instructions. > - AVX-512 byte and word instructions. > - AVX-512 vector length instructions. > - AVX-512 vector bit manipulation instructions. > - AVX-512 vector bit manipulation 2 instructions. > - Galois field new instructions. > - Vector AES instructions. > - Vector carry-less multiply instructions. > - AVX-512 vector neural network instructions. > - AVX-512 for bit algorithm instructions. > - AVX-512 vector popcount instructions. > - Cache line demote instructions. > - Direct store instructions. > - Direct store 64B instructions. > - AVX-512 two register intersection instructions. > > Signed-off-by: Kevin Laatz > --- > lib/librte_eal/common/arch/x86/rte_cpuflags.c | 18 ++++++++++++++++++ > .../common/include/arch/x86/rte_cpuflags.h | 18 ++++++++++++++++++ > 2 files changed, 36 insertions(+) > > diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_e= al/common/arch/x86/rte_cpuflags.c > index 6492df556..30439e795 100644 > --- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c > +++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c > @@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = =3D { > FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29) > > FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX, 8) > + > + FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17) > + FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21) > + FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28) > + FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30) > + FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31) > + FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1) > + FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6) > + FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8) > + FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9) > + FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10) > + FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11) > + FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12) > + FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX, 14) > + FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25) > + FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27) > + FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28) > + FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8) > }; > > int > diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/= librte_eal/common/include/arch/x86/rte_cpuflags.h > index 25ba47b96..f8f73b19f 100644 > --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h > +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h > @@ -113,6 +113,24 @@ enum rte_cpu_flag_t { > /* (EAX 80000007h) EDX features */ > RTE_CPUFLAG_INVTSC, /**< INVTSC */ > > + RTE_CPUFLAG_AVX512DQ, /**< AVX512 Doubleword and Qu= adword */ > + RTE_CPUFLAG_AVX512IFMA, /**< AVX512 Integer Fused Mul= tiply-Add */ > + RTE_CPUFLAG_AVX512CD, /**< AVX512 Conflict Detectio= n*/ > + RTE_CPUFLAG_AVX512BW, /**< AVX512 Byte and Word */ > + RTE_CPUFLAG_AVX512VL, /**< AVX512 Vector Length */ > + RTE_CPUFLAG_AVX512VBMI, /**< AVX512 Vector Bit Manipu= lation */ > + RTE_CPUFLAG_AVX512VBMI2, /**< AVX512 Vector Bit Manipu= lation 2 */ > + RTE_CPUFLAG_GFNI, /**< Galois Field New Instruc= tions */ > + RTE_CPUFLAG_VAES, /**< Vector AES */ > + RTE_CPUFLAG_VPCLMULQDQ, /**< Vector Carry-less Multip= ly */ > + RTE_CPUFLAG_AVX512VNNI, /**< AVX512 Vector Neural Net= work Instructions */ > + RTE_CPUFLAG_AVX512BITALG, /**< AVX512 Bit Algorithms */ > + RTE_CPUFLAG_AVX512VPOPCNTDQ, /**< AVX512 Vector Popcount *= / > + RTE_CPUFLAG_CLDEMOTE, /**< Cache Line Demote */ > + RTE_CPUFLAG_MOVDIRI, /**< Direct Store Instruction= s */ > + RTE_CPUFLAG_MOVDIR64B, /**< Direct Store Instruction= s 64B */ > + RTE_CPUFLAG_AVX512VP2INTERSECT, /**< AVX512 Two Register Inte= rsection */ > + > /* The last item */ > RTE_CPUFLAG_NUMFLAGS, /**< This should always be th= e last! */ This is seen as an ABI break because of the change on _NUMFLAGS: https://travis-ci.com/github/ovsrobot/dpdk/jobs/302524264#L2351 --=20 David Marchand