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Tue, 12 Aug 2025 02:21:41 -0700 (PDT) MIME-Version: 1.0 References: <20250701182033.642384-1-uk7b@foxmail.com> In-Reply-To: From: =?UTF-8?Q?Stanis=C5=82aw_Kardach?= Date: Tue, 12 Aug 2025 11:21:32 +0200 X-Gm-Features: Ac12FXw38QLOt4-rpo4ZWb4MCsXfXDco3LilKNwsj-3EHGgOC-cE2KtUwrrLQz8 Message-ID: Subject: Re: [PATCH v2 3/5] lib/lpm: R-V V rte_lpm_lookupx4 To: uk7b@foxmail.com Cc: dev@dpdk.org, Sun Yuechi , Thomas Monjalon , Bruce Richardson , Vladimir Medvedkin Content-Type: multipart/alternative; boundary="0000000000006f0f92063c27917f" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --0000000000006f0f92063c27917f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 1 Jul 2025, 20:20 , wrote: > From: Sun Yuechi > > Implement LPM lookupx4 function for RISC-V architecture using RISC-V > Vector Extension instruction set > > Signed-off-by: Sun Yuechi > Reviewed-by: Stanis=C5=82aw Kardach > --- > MAINTAINERS | 2 ++ > lib/lpm/meson.build | 1 + > lib/lpm/rte_lpm.h | 2 ++ > lib/lpm/rte_lpm_rvv.h | 59 +++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 64 insertions(+) > create mode 100644 lib/lpm/rte_lpm_rvv.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 0e9357f3a3..9bd97879b6 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -341,6 +341,8 @@ M: Stanislaw Kardach > F: config/riscv/ > F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst > F: lib/eal/riscv/ > +M: sunyuechi > +F: lib/**/*rvv* > > Intel x86 > M: Bruce Richardson > diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build > index cff8fed473..c4522eaf0c 100644 > --- a/lib/lpm/meson.build > +++ b/lib/lpm/meson.build > @@ -11,6 +11,7 @@ indirect_headers +=3D files( > 'rte_lpm_scalar.h', > 'rte_lpm_sse.h', > 'rte_lpm_sve.h', > + 'rte_lpm_rvv.h', > ) > deps +=3D ['hash'] > deps +=3D ['rcu'] > diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h > index 6bf8d9d883..edfe77b458 100644 > --- a/lib/lpm/rte_lpm.h > +++ b/lib/lpm/rte_lpm.h > @@ -420,6 +420,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, > uint32_t hop[4], > #include "rte_lpm_altivec.h" > #elif defined(RTE_ARCH_X86) > #include "rte_lpm_sse.h" > +#elif defined(RTE_ARCH_RISCV) && defined(RTE_RISCV_FEATURE_V) > +#include "rte_lpm_rvv.h" > #else > #include "rte_lpm_scalar.h" > #endif > diff --git a/lib/lpm/rte_lpm_rvv.h b/lib/lpm/rte_lpm_rvv.h > new file mode 100644 > index 0000000000..0d3dc91055 > --- /dev/null > +++ b/lib/lpm/rte_lpm_rvv.h > @@ -0,0 +1,59 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences > (ISCAS). > + */ > + > +#ifndef _RTE_LPM_RVV_H_ > +#define _RTE_LPM_RVV_H_ > + > +#include > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +#define RTE_LPM_LOOKUP_SUCCESS 0x01000000 > +#define RTE_LPM_VALID_EXT_ENTRY_BITMASK 0x03000000 > + > +static inline void rte_lpm_lookupx4( > + const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t > defv) > +{ > + size_t vl =3D 4; > + > + const uint32_t *tbl24_p =3D (const uint32_t *)lpm->tbl24; > + uint32_t tbl_entries[4] =3D { > + tbl24_p[((uint32_t)ip[0]) >> 8], > + tbl24_p[((uint32_t)ip[1]) >> 8], > + tbl24_p[((uint32_t)ip[2]) >> 8], > + tbl24_p[((uint32_t)ip[3]) >> 8], > + }; > + vuint32m1_t vtbl_entry =3D __riscv_vle32_v_u32m1(tbl_entries, vl)= ; > + > + vbool32_t mask =3D __riscv_vmseq_vx_u32m1_b32( > + __riscv_vand_vx_u32m1(vtbl_entry, > RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl), > + RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl); > + > + vuint32m1_t vtbl8_index =3D __riscv_vsll_vx_u32m1( > + __riscv_vadd_vv_u32m1( > + __riscv_vsll_vx_u32m1(__riscv_vand_vx_u32m1(vtbl_entry, > 0x00FFFFFF, vl), 8, vl), > + __riscv_vand_vx_u32m1( > + __riscv_vle32_v_u32m1((const uint32_t *)&ip, vl), > 0x000000FF, vl), > + vl), > + 2, vl); > + > + vtbl_entry =3D __riscv_vluxei32_v_u32m1_mu( > + mask, vtbl_entry, (const uint32_t *)(lpm->tbl8), vtbl8_index, > vl); > + > + vuint32m1_t vnext_hop =3D __riscv_vand_vx_u32m1(vtbl_entry, > 0x00FFFFFF, vl); > + mask =3D __riscv_vmseq_vx_u32m1_b32( > + __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_LOOKUP_SUCCESS, vl)= , > 0, vl); > + > + vnext_hop =3D __riscv_vmerge_vxm_u32m1(vnext_hop, defv, mask, vl)= ; > + > + __riscv_vse32_v_u32m1(hop, vnext_hop, vl); > +} > + > +#ifdef __cplusplus > +} > +#endif > + > +#endif /* _RTE_LPM_RVV_H_ */ > -- > 2.50.0 > > --0000000000006f0f92063c27917f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Tue, 1 Jul 2025, 20:20 , <= uk7b@foxmail.com> wrote:
From: Sun Yuechi <sunyuechi@iscas.ac.cn>

Implement LPM lookupx4 function for RISC-V architecture using RISC-V
Vector Extension instruction set

Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
Reviewed-by: Stanis=C5=82aw Kardach <<= a href=3D"mailto:stanislaw.kardach@gmail.com">stanislaw.kardach@gmail.com>
---
=C2=A0MAINTAINERS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 2 ++
=C2=A0lib/lpm/meson.build=C2=A0 =C2=A0|=C2=A0 1 +
=C2=A0lib/lpm/rte_lpm.h=C2=A0 =C2=A0 =C2=A0|=C2=A0 2 ++
=C2=A0lib/lpm/rte_lpm_rvv.h | 59 ++++++++++++++++++++++++++++++++++++++++++= +
=C2=A04 files changed, 64 insertions(+)
=C2=A0create mode 100644 lib/lpm/rte_lpm_rvv.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 0e9357f3a3..9bd97879b6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -341,6 +341,8 @@ M: Stanislaw Kardach <stanislaw.kardach@gma= il.com>
=C2=A0F: config/riscv/
=C2=A0F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
=C2=A0F: lib/eal/riscv/
+M: sunyuechi <sunyuechi@iscas.ac.cn>
+F: lib/**/*rvv*

=C2=A0Intel x86
=C2=A0M: Bruce Richardson <bruce.richardson@intel.com> diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index cff8fed473..c4522eaf0c 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -11,6 +11,7 @@ indirect_headers +=3D files(
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'rte_lpm_scalar.h',
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'rte_lpm_sse.h',
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0'rte_lpm_sve.h',
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 'rte_lpm_rvv.h',
=C2=A0)
=C2=A0deps +=3D ['hash']
=C2=A0deps +=3D ['rcu']
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 6bf8d9d883..edfe77b458 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -420,6 +420,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, u= int32_t hop[4],
=C2=A0#include "rte_lpm_altivec.h"
=C2=A0#elif defined(RTE_ARCH_X86)
=C2=A0#include "rte_lpm_sse.h"
+#elif defined(RTE_ARCH_RISCV) && defined(RTE_RISCV_FEATURE_V)
+#include "rte_lpm_rvv.h"
=C2=A0#else
=C2=A0#include "rte_lpm_scalar.h"
=C2=A0#endif
diff --git a/lib/lpm/rte_lpm_rvv.h b/lib/lpm/rte_lpm_rvv.h
new file mode 100644
index 0000000000..0d3dc91055
--- /dev/null
+++ b/lib/lpm/rte_lpm_rvv.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (I= SCAS).
+ */
+
+#ifndef _RTE_LPM_RVV_H_
+#define _RTE_LPM_RVV_H_
+
+#include <rte_vect.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_LPM_LOOKUP_SUCCESS 0x01000000
+#define RTE_LPM_VALID_EXT_ENTRY_BITMASK 0x03000000
+
+static inline void rte_lpm_lookupx4(
+=C2=A0 =C2=A0 =C2=A0 =C2=A0const struct rte_lpm *lpm, xmm_t ip, uint32_t h= op[4], uint32_t defv)
+{
+=C2=A0 =C2=A0 =C2=A0 =C2=A0size_t vl =3D 4;
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0const uint32_t *tbl24_p =3D (const uint32_t *)l= pm->tbl24;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t tbl_entries[4] =3D {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tbl24_p[((uint32_t)= ip[0]) >> 8],
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tbl24_p[((uint32_t)= ip[1]) >> 8],
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tbl24_p[((uint32_t)= ip[2]) >> 8],
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tbl24_p[((uint32_t)= ip[3]) >> 8],
+=C2=A0 =C2=A0 =C2=A0 =C2=A0};
+=C2=A0 =C2=A0 =C2=A0 =C2=A0vuint32m1_t vtbl_entry =3D __riscv_vle32_v_u32m= 1(tbl_entries, vl);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0vbool32_t mask =3D __riscv_vmseq_vx_u32m1_b32(<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0__riscv_vand_vx_u32m1(vtbl_entry,= RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0RTE_LPM_VALID_EXT_ENTRY_BITMASK, = vl);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0vuint32m1_t vtbl8_index =3D __riscv_vsll_vx_u32= m1(
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0__riscv_vadd_vv_u32m1(
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0__riscv_vsll_vx_u32= m1(__riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl), 8, vl),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0__riscv_vand_vx_u32= m1(
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0__ris= cv_vle32_v_u32m1((const uint32_t *)&ip, vl), 0x000000FF, vl),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0vl),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A02, vl);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0vtbl_entry =3D __riscv_vluxei32_v_u32m1_mu(
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mask, vtbl_entry, (const uint32_t= *)(lpm->tbl8), vtbl8_index, vl);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0vuint32m1_t vnext_hop =3D __riscv_vand_vx_u32m1= (vtbl_entry, 0x00FFFFFF, vl);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0mask =3D __riscv_vmseq_vx_u32m1_b32(
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0__riscv_vand_vx_u32m1(vtbl_entry,= RTE_LPM_LOOKUP_SUCCESS, vl), 0, vl);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0vnext_hop =3D __riscv_vmerge_vxm_u32m1(vnext_ho= p, defv, mask, vl);
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0__riscv_vse32_v_u32m1(hop, vnext_hop, vl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_RVV_H_ */
--
2.50.0

--0000000000006f0f92063c27917f--