[PATCH v2 1/5] config/riscv: detect V extension

[PATCH v2 1/5] config/riscv: detect V extension

[uk7b]

From: Sun Yuechi <sunyuechi@iscas.ac.cn>

This patch is derived from "config/riscv: detect presence of Zbc
extension with modifications".

The RISC-V C api defines architecture extension test macros
These let us detect whether the V extension is supported on the
compiler and -march we're building with. The C api also defines V
intrinsics we can use rather than inline assembly on newer versions of
GCC (14.1.0+) and Clang (18.1.0+).

If the V extension and intrinsics are both present and we can detect
the V extension at runtime, we define a flag, RTE_RISCV_FEATURE_V.

Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
---
 .mailmap                         |  1 +
 config/riscv/meson.build         | 25 +++++++++++++++++++++++++
 lib/eal/riscv/include/rte_vect.h |  4 ++++
 3 files changed, 30 insertions(+)

diff --git a/.mailmap b/.mailmap
index 8483d96ec5..21f5d7fb5e 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1513,6 +1513,7 @@ Sunil Kumar Kori <skori@marvell.com> <skori@mavell.com> <sunil.kori@nxp.com>
 Sunil Pai G <sunil.pai.g@intel.com>
 Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>
 Sun Jiajia <sunx.jiajia@intel.com>
+Sun Yuechi <sunyuechi@iscas.ac.cn> <uk7b@foxmail.com>
 Sunyang Wu <sunyang.wu@jaguarmicro.com>
 Surabhi Boob <surabhi.boob@intel.com>
 Suyang Ju <sju@paloaltonetworks.com>
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 7562c6cb99..e3694cf2e6 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -119,6 +119,31 @@ foreach flag: arch_config['machine_args']
     endif
 endforeach
 
+# check if we can do buildtime detection of extensions supported by the target
+riscv_extension_macros = false
+if (cc.get_define('__riscv_arch_test', args: machine_args) == '1')
+  message('Detected architecture extension test macros')
+  riscv_extension_macros = true
+else
+  warning('RISC-V architecture extension test macros not available. Build-time detection of extensions not possible')
+endif
+
+# detect extensions
+# Requires intrinsics available in GCC 14.1.0+ and Clang 18.1.0+
+if (riscv_extension_macros and
+    (cc.get_define('__riscv_vector', args: machine_args) != ''))
+  if ((cc.get_id() == 'gcc' and cc.version().version_compare('>=14.1.0'))
+      or (cc.get_id() == 'clang' and cc.version().version_compare('>=18.1.0')))
+    if (cc.compiles('''#include <riscv_vector.h>
+        int main(void) { size_t vl = __riscv_vsetvl_e32m1(1); }''', args: machine_args))
+      message('Compiling with the V extension')
+      machine_args += ['-DRTE_RISCV_FEATURE_V']
+    endif
+  else
+    warning('Detected V extension but cannot use because intrinsics are not available (present in GCC 14.1.0+ and Clang 18.1.0+)')
+  endif
+endif
+
 # apply flags
 foreach flag: dpdk_flags
     if flag.length() > 0
diff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h
index 6df10fa8ee..a4357e266a 100644
--- a/lib/eal/riscv/include/rte_vect.h
+++ b/lib/eal/riscv/include/rte_vect.h
@@ -11,6 +11,10 @@
 #include "generic/rte_vect.h"
 #include "rte_common.h"
 
+#ifdef RTE_RISCV_FEATURE_V
+#include <riscv_vector.h>
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
-- 
2.50.0

Re: [PATCH v2 1/5] config/riscv: detect V extension

[Stanisław Kardach]

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On Tue, 1 Jul 2025, 20:21 , <uk7b@foxmail.com> wrote:

> From: Sun Yuechi <sunyuechi@iscas.ac.cn>
>
> This patch is derived from "config/riscv: detect presence of Zbc
> extension with modifications".
>
> The RISC-V C api defines architecture extension test macros
> These let us detect whether the V extension is supported on the
> compiler and -march we're building with. The C api also defines V
> intrinsics we can use rather than inline assembly on newer versions of
> GCC (14.1.0+) and Clang (18.1.0+).
>
> If the V extension and intrinsics are both present and we can detect
> the V extension at runtime, we define a flag, RTE_RISCV_FEATURE_V.
>
> Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
>
Reviewed-by: Stanisław Kardach <stanislaw.kardach@gmail.com>

> ---
>  .mailmap                         |  1 +
>  config/riscv/meson.build         | 25 +++++++++++++++++++++++++
>  lib/eal/riscv/include/rte_vect.h |  4 ++++
>  3 files changed, 30 insertions(+)
>
> diff --git a/.mailmap b/.mailmap
> index 8483d96ec5..21f5d7fb5e 100644
> --- a/.mailmap
> +++ b/.mailmap
> @@ -1513,6 +1513,7 @@ Sunil Kumar Kori <skori@marvell.com> <
> skori@mavell.com> <sunil.kori@nxp.com>
>  Sunil Pai G <sunil.pai.g@intel.com>
>  Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>
>  Sun Jiajia <sunx.jiajia@intel.com>
> +Sun Yuechi <sunyuechi@iscas.ac.cn> <uk7b@foxmail.com>
>  Sunyang Wu <sunyang.wu@jaguarmicro.com>
>  Surabhi Boob <surabhi.boob@intel.com>
>  Suyang Ju <sju@paloaltonetworks.com>
> diff --git a/config/riscv/meson.build b/config/riscv/meson.build
> index 7562c6cb99..e3694cf2e6 100644
> --- a/config/riscv/meson.build
> +++ b/config/riscv/meson.build
> @@ -119,6 +119,31 @@ foreach flag: arch_config['machine_args']
>      endif
>  endforeach
>
> +# check if we can do buildtime detection of extensions supported by the
> target
> +riscv_extension_macros = false
> +if (cc.get_define('__riscv_arch_test', args: machine_args) == '1')
> +  message('Detected architecture extension test macros')
> +  riscv_extension_macros = true
> +else
> +  warning('RISC-V architecture extension test macros not available.
> Build-time detection of extensions not possible')
> +endif
> +
> +# detect extensions
> +# Requires intrinsics available in GCC 14.1.0+ and Clang 18.1.0+
> +if (riscv_extension_macros and
> +    (cc.get_define('__riscv_vector', args: machine_args) != ''))
> +  if ((cc.get_id() == 'gcc' and cc.version().version_compare('>=14.1.0'))
> +      or (cc.get_id() == 'clang' and
> cc.version().version_compare('>=18.1.0')))
> +    if (cc.compiles('''#include <riscv_vector.h>
> +        int main(void) { size_t vl = __riscv_vsetvl_e32m1(1); }''', args:
> machine_args))
> +      message('Compiling with the V extension')
> +      machine_args += ['-DRTE_RISCV_FEATURE_V']
> +    endif
> +  else
> +    warning('Detected V extension but cannot use because intrinsics are
> not available (present in GCC 14.1.0+ and Clang 18.1.0+)')
> +  endif
> +endif
> +
>  # apply flags
>  foreach flag: dpdk_flags
>      if flag.length() > 0
> diff --git a/lib/eal/riscv/include/rte_vect.h
> b/lib/eal/riscv/include/rte_vect.h
> index 6df10fa8ee..a4357e266a 100644
> --- a/lib/eal/riscv/include/rte_vect.h
> +++ b/lib/eal/riscv/include/rte_vect.h
> @@ -11,6 +11,10 @@
>  #include "generic/rte_vect.h"
>  #include "rte_common.h"
>
> +#ifdef RTE_RISCV_FEATURE_V
> +#include <riscv_vector.h>
> +#endif
> +
>  #ifdef __cplusplus
>  extern "C" {
>  #endif
> --
> 2.50.0
>
>

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[PATCH v2 2/5] eal/riscv/spinlock: add rte_cpuflag.h

[uk7b]

From: Sun Yuechi <sunyuechi@iscas.ac.cn>

Same as the x86 style, include "rte_cpuflags.h" in rte_spinlock.h
so that files like lib/fib/dir24_8.c don’t need to include it.

Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
---
 lib/eal/riscv/include/rte_spinlock.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/lib/eal/riscv/include/rte_spinlock.h b/lib/eal/riscv/include/rte_spinlock.h
index 5fe4980e44..afbe83a061 100644
--- a/lib/eal/riscv/include/rte_spinlock.h
+++ b/lib/eal/riscv/include/rte_spinlock.h
@@ -14,6 +14,7 @@
 
 #include <rte_common.h>
 #include "generic/rte_spinlock.h"
+#include "rte_cpuflags.h"
 
 #ifdef __cplusplus
 extern "C" {
-- 
2.50.0

Re: [PATCH v2 2/5] eal/riscv/spinlock: add rte_cpuflag.h

[Stanisław Kardach]

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On Tue, 1 Jul 2025, 20:20 , <uk7b@foxmail.com> wrote:

> From: Sun Yuechi <sunyuechi@iscas.ac.cn>
>
> Same as the x86 style, include "rte_cpuflags.h" in rte_spinlock.h
> so that files like lib/fib/dir24_8.c don’t need to include it.
>
> Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
>
Reviewed-by: Stanisław Kardach <stanislaw.kardach@gmail.com>

> ---
>  lib/eal/riscv/include/rte_spinlock.h | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/lib/eal/riscv/include/rte_spinlock.h
> b/lib/eal/riscv/include/rte_spinlock.h
> index 5fe4980e44..afbe83a061 100644
> --- a/lib/eal/riscv/include/rte_spinlock.h
> +++ b/lib/eal/riscv/include/rte_spinlock.h
> @@ -14,6 +14,7 @@
>
>  #include <rte_common.h>
>  #include "generic/rte_spinlock.h"
> +#include "rte_cpuflags.h"
>
>  #ifdef __cplusplus
>  extern "C" {
> --
> 2.50.0
>
>

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[PATCH v2 3/5] lib/lpm: R-V V rte_lpm_lookupx4

[uk7b]

From: Sun Yuechi <sunyuechi@iscas.ac.cn>

Implement LPM lookupx4 function for RISC-V architecture using RISC-V
Vector Extension instruction set

Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
---
 MAINTAINERS           |  2 ++
 lib/lpm/meson.build   |  1 +
 lib/lpm/rte_lpm.h     |  2 ++
 lib/lpm/rte_lpm_rvv.h | 59 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 64 insertions(+)
 create mode 100644 lib/lpm/rte_lpm_rvv.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 0e9357f3a3..9bd97879b6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -341,6 +341,8 @@ M: Stanislaw Kardach <stanislaw.kardach@gmail.com>
 F: config/riscv/
 F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
 F: lib/eal/riscv/
+M: sunyuechi <sunyuechi@iscas.ac.cn>
+F: lib/**/*rvv*
 
 Intel x86
 M: Bruce Richardson <bruce.richardson@intel.com>
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index cff8fed473..c4522eaf0c 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -11,6 +11,7 @@ indirect_headers += files(
         'rte_lpm_scalar.h',
         'rte_lpm_sse.h',
         'rte_lpm_sve.h',
+        'rte_lpm_rvv.h',
 )
 deps += ['hash']
 deps += ['rcu']
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 6bf8d9d883..edfe77b458 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -420,6 +420,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
 #include "rte_lpm_altivec.h"
 #elif defined(RTE_ARCH_X86)
 #include "rte_lpm_sse.h"
+#elif defined(RTE_ARCH_RISCV) && defined(RTE_RISCV_FEATURE_V)
+#include "rte_lpm_rvv.h"
 #else
 #include "rte_lpm_scalar.h"
 #endif
diff --git a/lib/lpm/rte_lpm_rvv.h b/lib/lpm/rte_lpm_rvv.h
new file mode 100644
index 0000000000..0d3dc91055
--- /dev/null
+++ b/lib/lpm/rte_lpm_rvv.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+ */
+
+#ifndef _RTE_LPM_RVV_H_
+#define _RTE_LPM_RVV_H_
+
+#include <rte_vect.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_LPM_LOOKUP_SUCCESS 0x01000000
+#define RTE_LPM_VALID_EXT_ENTRY_BITMASK 0x03000000
+
+static inline void rte_lpm_lookupx4(
+	const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t defv)
+{
+	size_t vl = 4;
+
+	const uint32_t *tbl24_p = (const uint32_t *)lpm->tbl24;
+	uint32_t tbl_entries[4] = {
+		tbl24_p[((uint32_t)ip[0]) >> 8],
+		tbl24_p[((uint32_t)ip[1]) >> 8],
+		tbl24_p[((uint32_t)ip[2]) >> 8],
+		tbl24_p[((uint32_t)ip[3]) >> 8],
+	};
+	vuint32m1_t vtbl_entry = __riscv_vle32_v_u32m1(tbl_entries, vl);
+
+	vbool32_t mask = __riscv_vmseq_vx_u32m1_b32(
+	    __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl),
+	    RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl);
+
+	vuint32m1_t vtbl8_index = __riscv_vsll_vx_u32m1(
+	    __riscv_vadd_vv_u32m1(
+		__riscv_vsll_vx_u32m1(__riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl), 8, vl),
+		__riscv_vand_vx_u32m1(
+		    __riscv_vle32_v_u32m1((const uint32_t *)&ip, vl), 0x000000FF, vl),
+		vl),
+	    2, vl);
+
+	vtbl_entry = __riscv_vluxei32_v_u32m1_mu(
+	    mask, vtbl_entry, (const uint32_t *)(lpm->tbl8), vtbl8_index, vl);
+
+	vuint32m1_t vnext_hop = __riscv_vand_vx_u32m1(vtbl_entry, 0x00FFFFFF, vl);
+	mask = __riscv_vmseq_vx_u32m1_b32(
+	    __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_LOOKUP_SUCCESS, vl), 0, vl);
+
+	vnext_hop = __riscv_vmerge_vxm_u32m1(vnext_hop, defv, mask, vl);
+
+	__riscv_vse32_v_u32m1(hop, vnext_hop, vl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_RVV_H_ */
-- 
2.50.0

Re: [PATCH v2 3/5] lib/lpm: R-V V rte_lpm_lookupx4

[Stanisław Kardach]

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On Tue, 1 Jul 2025, 20:20 , <uk7b@foxmail.com> wrote:

> From: Sun Yuechi <sunyuechi@iscas.ac.cn>
>
> Implement LPM lookupx4 function for RISC-V architecture using RISC-V
> Vector Extension instruction set
>
> Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
>
Reviewed-by: Stanisław Kardach <stanislaw.kardach@gmail.com>

> ---
>  MAINTAINERS           |  2 ++
>  lib/lpm/meson.build   |  1 +
>  lib/lpm/rte_lpm.h     |  2 ++
>  lib/lpm/rte_lpm_rvv.h | 59 +++++++++++++++++++++++++++++++++++++++++++
>  4 files changed, 64 insertions(+)
>  create mode 100644 lib/lpm/rte_lpm_rvv.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 0e9357f3a3..9bd97879b6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -341,6 +341,8 @@ M: Stanislaw Kardach <stanislaw.kardach@gmail.com>
>  F: config/riscv/
>  F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
>  F: lib/eal/riscv/
> +M: sunyuechi <sunyuechi@iscas.ac.cn>
> +F: lib/**/*rvv*
>
>  Intel x86
>  M: Bruce Richardson <bruce.richardson@intel.com>
> diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
> index cff8fed473..c4522eaf0c 100644
> --- a/lib/lpm/meson.build
> +++ b/lib/lpm/meson.build
> @@ -11,6 +11,7 @@ indirect_headers += files(
>          'rte_lpm_scalar.h',
>          'rte_lpm_sse.h',
>          'rte_lpm_sve.h',
> +        'rte_lpm_rvv.h',
>  )
>  deps += ['hash']
>  deps += ['rcu']
> diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
> index 6bf8d9d883..edfe77b458 100644
> --- a/lib/lpm/rte_lpm.h
> +++ b/lib/lpm/rte_lpm.h
> @@ -420,6 +420,8 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip,
> uint32_t hop[4],
>  #include "rte_lpm_altivec.h"
>  #elif defined(RTE_ARCH_X86)
>  #include "rte_lpm_sse.h"
> +#elif defined(RTE_ARCH_RISCV) && defined(RTE_RISCV_FEATURE_V)
> +#include "rte_lpm_rvv.h"
>  #else
>  #include "rte_lpm_scalar.h"
>  #endif
> diff --git a/lib/lpm/rte_lpm_rvv.h b/lib/lpm/rte_lpm_rvv.h
> new file mode 100644
> index 0000000000..0d3dc91055
> --- /dev/null
> +++ b/lib/lpm/rte_lpm_rvv.h
> @@ -0,0 +1,59 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences
> (ISCAS).
> + */
> +
> +#ifndef _RTE_LPM_RVV_H_
> +#define _RTE_LPM_RVV_H_
> +
> +#include <rte_vect.h>
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#define RTE_LPM_LOOKUP_SUCCESS 0x01000000
> +#define RTE_LPM_VALID_EXT_ENTRY_BITMASK 0x03000000
> +
> +static inline void rte_lpm_lookupx4(
> +       const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4], uint32_t
> defv)
> +{
> +       size_t vl = 4;
> +
> +       const uint32_t *tbl24_p = (const uint32_t *)lpm->tbl24;
> +       uint32_t tbl_entries[4] = {
> +               tbl24_p[((uint32_t)ip[0]) >> 8],
> +               tbl24_p[((uint32_t)ip[1]) >> 8],
> +               tbl24_p[((uint32_t)ip[2]) >> 8],
> +               tbl24_p[((uint32_t)ip[3]) >> 8],
> +       };
> +       vuint32m1_t vtbl_entry = __riscv_vle32_v_u32m1(tbl_entries, vl);
> +
> +       vbool32_t mask = __riscv_vmseq_vx_u32m1_b32(
> +           __riscv_vand_vx_u32m1(vtbl_entry,
> RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl),
> +           RTE_LPM_VALID_EXT_ENTRY_BITMASK, vl);
> +
> +       vuint32m1_t vtbl8_index = __riscv_vsll_vx_u32m1(
> +           __riscv_vadd_vv_u32m1(
> +               __riscv_vsll_vx_u32m1(__riscv_vand_vx_u32m1(vtbl_entry,
> 0x00FFFFFF, vl), 8, vl),
> +               __riscv_vand_vx_u32m1(
> +                   __riscv_vle32_v_u32m1((const uint32_t *)&ip, vl),
> 0x000000FF, vl),
> +               vl),
> +           2, vl);
> +
> +       vtbl_entry = __riscv_vluxei32_v_u32m1_mu(
> +           mask, vtbl_entry, (const uint32_t *)(lpm->tbl8), vtbl8_index,
> vl);
> +
> +       vuint32m1_t vnext_hop = __riscv_vand_vx_u32m1(vtbl_entry,
> 0x00FFFFFF, vl);
> +       mask = __riscv_vmseq_vx_u32m1_b32(
> +           __riscv_vand_vx_u32m1(vtbl_entry, RTE_LPM_LOOKUP_SUCCESS, vl),
> 0, vl);
> +
> +       vnext_hop = __riscv_vmerge_vxm_u32m1(vnext_hop, defv, mask, vl);
> +
> +       __riscv_vse32_v_u32m1(hop, vnext_hop, vl);
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* _RTE_LPM_RVV_H_ */
> --
> 2.50.0
>
>

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[PATCH v2 4/5] lib/fib: R-V V rte_fib_lookup_bulk

[uk7b]

From: Sun Yuechi <sunyuechi@iscas.ac.cn>

Implement rte_fib_lookup_bulk function for RISC-V architecture using RISC-V
Vector Extension instruction set

Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
---
 lib/fib/dir24_8.c     | 20 ++++++++++++++
 lib/fib/dir24_8_rvv.c | 64 +++++++++++++++++++++++++++++++++++++++++++
 lib/fib/dir24_8_rvv.h | 24 ++++++++++++++++
 lib/fib/meson.build   |  2 ++
 4 files changed, 110 insertions(+)
 create mode 100644 lib/fib/dir24_8_rvv.c
 create mode 100644 lib/fib/dir24_8_rvv.h

diff --git a/lib/fib/dir24_8.c b/lib/fib/dir24_8.c
index 2ba7e93511..c652d3ca98 100644
--- a/lib/fib/dir24_8.c
+++ b/lib/fib/dir24_8.c
@@ -20,6 +20,10 @@
 
 #include "dir24_8_avx512.h"
 
+#elif defined(RTE_RISCV_FEATURE_V)
+
+#include "dir24_8_rvv.h"
+
 #endif /* CC_AVX512_SUPPORT */
 
 #define DIR24_8_NAMESIZE	64
@@ -88,6 +92,22 @@ get_vector_fn(enum rte_fib_dir24_8_nh_sz nh_sz, bool be_addr)
 	default:
 		return NULL;
 	}
+#elif defined(RTE_RISCV_FEATURE_V)
+	RTE_SET_USED(be_addr);
+	if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_RISCV_ISA_V) <= 0)
+		return NULL;
+	switch (nh_sz) {
+	case RTE_FIB_DIR24_8_1B:
+		return rte_dir24_8_vec_lookup_bulk_1b;
+	case RTE_FIB_DIR24_8_2B:
+		return rte_dir24_8_vec_lookup_bulk_2b;
+	case RTE_FIB_DIR24_8_4B:
+		return rte_dir24_8_vec_lookup_bulk_4b;
+	case RTE_FIB_DIR24_8_8B:
+		return rte_dir24_8_vec_lookup_bulk_8b;
+	default:
+		return NULL;
+	}
 #else
 	RTE_SET_USED(nh_sz);
 	RTE_SET_USED(be_addr);
diff --git a/lib/fib/dir24_8_rvv.c b/lib/fib/dir24_8_rvv.c
new file mode 100644
index 0000000000..9c14ca0481
--- /dev/null
+++ b/lib/fib/dir24_8_rvv.c
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+ */
+
+#if defined(RTE_RISCV_FEATURE_V)
+
+#include <rte_vect.h>
+#include <rte_fib.h>
+
+#include "dir24_8.h"
+#include "dir24_8_rvv.h"
+
+#define DECLARE_VECTOR_FN(SFX, NH_SZ) \
+void \
+rte_dir24_8_vec_lookup_bulk_##SFX(void *p, \
+		const uint32_t *ips, uint64_t *next_hops, unsigned int n) \
+{ \
+	const uint8_t  idx_bits = 3 - NH_SZ; \
+	const uint32_t idx_mask = (1u << (3 - NH_SZ)) - 1u; \
+	const uint64_t e_mask   = ~0ULL >> (64 - (8u << NH_SZ)); \
+	struct dir24_8_tbl *tbl = (struct dir24_8_tbl *)p; \
+	const uint64_t *tbl24   = tbl->tbl24; \
+	size_t vl; \
+	for (unsigned int i = 0; i < n; i += vl) { \
+		vl = __riscv_vsetvl_e32m4(n - i); \
+		vuint32m4_t v_ips = __riscv_vle32_v_u32m4(&ips[i], vl); \
+		vuint64m8_t vtbl_word = __riscv_vluxei32_v_u64m8(tbl24, \
+				__riscv_vsll_vx_u32m4( \
+				__riscv_vsrl_vx_u32m4(v_ips, idx_bits + 8, vl), 3, vl), vl); \
+		vuint32m4_t v_tbl_index = __riscv_vsrl_vx_u32m4(v_ips, 8, vl); \
+		vuint32m4_t v_entry_idx = __riscv_vand_vx_u32m4(v_tbl_index, idx_mask, vl); \
+		vuint32m4_t v_shift     = __riscv_vsll_vx_u32m4(v_entry_idx, 3 + NH_SZ, vl); \
+		vuint64m8_t vtbl_entry  = __riscv_vand_vx_u64m8( \
+				__riscv_vsrl_vv_u64m8(vtbl_word, \
+					__riscv_vwcvtu_x_x_v_u64m8(v_shift, vl), vl), e_mask, vl); \
+		vbool8_t mask = __riscv_vmseq_vx_u64m8_b8( \
+				__riscv_vand_vx_u64m8(vtbl_entry, 1, vl), 1, vl); \
+		if (__riscv_vcpop_m_b8(mask, vl)) { \
+			const uint64_t *tbl8 = tbl->tbl8; \
+			v_tbl_index = __riscv_vadd_vv_u32m4_mu(mask, v_tbl_index, \
+					__riscv_vsll_vx_u32m4( \
+						__riscv_vnsrl_wx_u32m4(vtbl_entry, 1, vl), 8, vl), \
+						__riscv_vand_vx_u32m4(v_ips, 0xFF, vl), vl); \
+			vtbl_word = __riscv_vluxei32_v_u64m8_mu(mask, vtbl_word, tbl8, \
+					__riscv_vsll_vx_u32m4( \
+					__riscv_vsrl_vx_u32m4(v_tbl_index, idx_bits, vl), 3, vl), \
+						vl); \
+			v_entry_idx = __riscv_vand_vx_u32m4(v_tbl_index, idx_mask, vl); \
+			v_shift     = __riscv_vsll_vx_u32m4(v_entry_idx, 3 + NH_SZ, vl); \
+			vtbl_entry  = __riscv_vand_vx_u64m8( \
+					__riscv_vsrl_vv_u64m8(vtbl_word, \
+					__riscv_vwcvtu_x_x_v_u64m8(v_shift, vl), vl), e_mask, vl); \
+		} \
+		__riscv_vse64_v_u64m8(&next_hops[i], \
+				__riscv_vsrl_vx_u64m8(vtbl_entry, 1, vl), vl); \
+	} \
+}
+
+DECLARE_VECTOR_FN(1b, 0)
+DECLARE_VECTOR_FN(2b, 1)
+DECLARE_VECTOR_FN(4b, 2)
+DECLARE_VECTOR_FN(8b, 3)
+
+#endif
diff --git a/lib/fib/dir24_8_rvv.h b/lib/fib/dir24_8_rvv.h
new file mode 100644
index 0000000000..7be99f7882
--- /dev/null
+++ b/lib/fib/dir24_8_rvv.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences (ISCAS).
+ */
+
+#ifndef _DIR248_RVV_H_
+#define _DIR248_RVV_H_
+
+void
+rte_dir24_8_vec_lookup_bulk_1b(void *p, const uint32_t *ips,
+	uint64_t *next_hops, const unsigned int n);
+
+void
+rte_dir24_8_vec_lookup_bulk_2b(void *p, const uint32_t *ips,
+	uint64_t *next_hops, const unsigned int n);
+
+void
+rte_dir24_8_vec_lookup_bulk_4b(void *p, const uint32_t *ips,
+	uint64_t *next_hops, const unsigned int n);
+
+void
+rte_dir24_8_vec_lookup_bulk_8b(void *p, const uint32_t *ips,
+	uint64_t *next_hops, const unsigned int n);
+
+#endif /* _DIR248_RVV_H_ */
diff --git a/lib/fib/meson.build b/lib/fib/meson.build
index 6992ccc040..573fc50ff1 100644
--- a/lib/fib/meson.build
+++ b/lib/fib/meson.build
@@ -10,4 +10,6 @@ deps += ['net']
 
 if dpdk_conf.has('RTE_ARCH_X86_64')
     sources_avx512 += files('dir24_8_avx512.c', 'trie_avx512.c')
+elif dpdk_conf.has('RTE_ARCH_RISCV')
+    sources += files('dir24_8_rvv.c')
 endif
-- 
2.50.0

Re: [PATCH v2 4/5] lib/fib: R-V V rte_fib_lookup_bulk

[Stanisław Kardach]

[-- Attachment #1: Type: text/plain, Size: 6863 bytes --]

On Tue, 1 Jul 2025, 20:21 , <uk7b@foxmail.com> wrote:

> From: Sun Yuechi <sunyuechi@iscas.ac.cn>
>
> Implement rte_fib_lookup_bulk function for RISC-V architecture using RISC-V
> Vector Extension instruction set
>
> Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
>
From RISC-V perspective:

Reviewed-by: Stanisław Kardach <stanislaw.kardach@gmail.com>

> ---
>  lib/fib/dir24_8.c     | 20 ++++++++++++++
>  lib/fib/dir24_8_rvv.c | 64 +++++++++++++++++++++++++++++++++++++++++++
>  lib/fib/dir24_8_rvv.h | 24 ++++++++++++++++
>  lib/fib/meson.build   |  2 ++
>  4 files changed, 110 insertions(+)
>  create mode 100644 lib/fib/dir24_8_rvv.c
>  create mode 100644 lib/fib/dir24_8_rvv.h
>
> diff --git a/lib/fib/dir24_8.c b/lib/fib/dir24_8.c
> index 2ba7e93511..c652d3ca98 100644
> --- a/lib/fib/dir24_8.c
> +++ b/lib/fib/dir24_8.c
> @@ -20,6 +20,10 @@
>
>  #include "dir24_8_avx512.h"
>
> +#elif defined(RTE_RISCV_FEATURE_V)
> +
> +#include "dir24_8_rvv.h"
> +
>  #endif /* CC_AVX512_SUPPORT */
>
>  #define DIR24_8_NAMESIZE       64
> @@ -88,6 +92,22 @@ get_vector_fn(enum rte_fib_dir24_8_nh_sz nh_sz, bool
> be_addr)
>         default:
>                 return NULL;
>         }
> +#elif defined(RTE_RISCV_FEATURE_V)
> +       RTE_SET_USED(be_addr);
> +       if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_RISCV_ISA_V) <= 0)
> +               return NULL;
> +       switch (nh_sz) {
> +       case RTE_FIB_DIR24_8_1B:
> +               return rte_dir24_8_vec_lookup_bulk_1b;
> +       case RTE_FIB_DIR24_8_2B:
> +               return rte_dir24_8_vec_lookup_bulk_2b;
> +       case RTE_FIB_DIR24_8_4B:
> +               return rte_dir24_8_vec_lookup_bulk_4b;
> +       case RTE_FIB_DIR24_8_8B:
> +               return rte_dir24_8_vec_lookup_bulk_8b;
> +       default:
> +               return NULL;
> +       }
>  #else
>         RTE_SET_USED(nh_sz);
>         RTE_SET_USED(be_addr);
> diff --git a/lib/fib/dir24_8_rvv.c b/lib/fib/dir24_8_rvv.c
> new file mode 100644
> index 0000000000..9c14ca0481
> --- /dev/null
> +++ b/lib/fib/dir24_8_rvv.c
> @@ -0,0 +1,64 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences
> (ISCAS).
> + */
> +
> +#if defined(RTE_RISCV_FEATURE_V)
> +
> +#include <rte_vect.h>
> +#include <rte_fib.h>
> +
> +#include "dir24_8.h"
> +#include "dir24_8_rvv.h"
> +
> +#define DECLARE_VECTOR_FN(SFX, NH_SZ) \
> +void \
> +rte_dir24_8_vec_lookup_bulk_##SFX(void *p, \
> +               const uint32_t *ips, uint64_t *next_hops, unsigned int n) \
> +{ \
> +       const uint8_t  idx_bits = 3 - NH_SZ; \
> +       const uint32_t idx_mask = (1u << (3 - NH_SZ)) - 1u; \
> +       const uint64_t e_mask   = ~0ULL >> (64 - (8u << NH_SZ)); \
> +       struct dir24_8_tbl *tbl = (struct dir24_8_tbl *)p; \
> +       const uint64_t *tbl24   = tbl->tbl24; \
> +       size_t vl; \
> +       for (unsigned int i = 0; i < n; i += vl) { \
> +               vl = __riscv_vsetvl_e32m4(n - i); \
> +               vuint32m4_t v_ips = __riscv_vle32_v_u32m4(&ips[i], vl); \
> +               vuint64m8_t vtbl_word = __riscv_vluxei32_v_u64m8(tbl24, \
> +                               __riscv_vsll_vx_u32m4( \
> +                               __riscv_vsrl_vx_u32m4(v_ips, idx_bits + 8,
> vl), 3, vl), vl); \
> +               vuint32m4_t v_tbl_index = __riscv_vsrl_vx_u32m4(v_ips, 8,
> vl); \
> +               vuint32m4_t v_entry_idx =
> __riscv_vand_vx_u32m4(v_tbl_index, idx_mask, vl); \
> +               vuint32m4_t v_shift     =
> __riscv_vsll_vx_u32m4(v_entry_idx, 3 + NH_SZ, vl); \
> +               vuint64m8_t vtbl_entry  = __riscv_vand_vx_u64m8( \
> +                               __riscv_vsrl_vv_u64m8(vtbl_word, \
> +
>  __riscv_vwcvtu_x_x_v_u64m8(v_shift, vl), vl), e_mask, vl); \
> +               vbool8_t mask = __riscv_vmseq_vx_u64m8_b8( \
> +                               __riscv_vand_vx_u64m8(vtbl_entry, 1, vl),
> 1, vl); \
> +               if (__riscv_vcpop_m_b8(mask, vl)) { \
> +                       const uint64_t *tbl8 = tbl->tbl8; \
> +                       v_tbl_index = __riscv_vadd_vv_u32m4_mu(mask,
> v_tbl_index, \
> +                                       __riscv_vsll_vx_u32m4( \
> +
>  __riscv_vnsrl_wx_u32m4(vtbl_entry, 1, vl), 8, vl), \
> +
>  __riscv_vand_vx_u32m4(v_ips, 0xFF, vl), vl); \
> +                       vtbl_word = __riscv_vluxei32_v_u64m8_mu(mask,
> vtbl_word, tbl8, \
> +                                       __riscv_vsll_vx_u32m4( \
> +                                       __riscv_vsrl_vx_u32m4(v_tbl_index,
> idx_bits, vl), 3, vl), \
> +                                               vl); \
> +                       v_entry_idx = __riscv_vand_vx_u32m4(v_tbl_index,
> idx_mask, vl); \
> +                       v_shift     = __riscv_vsll_vx_u32m4(v_entry_idx, 3
> + NH_SZ, vl); \
> +                       vtbl_entry  = __riscv_vand_vx_u64m8( \
> +                                       __riscv_vsrl_vv_u64m8(vtbl_word, \
> +
>  __riscv_vwcvtu_x_x_v_u64m8(v_shift, vl), vl), e_mask, vl); \
> +               } \
> +               __riscv_vse64_v_u64m8(&next_hops[i], \
> +                               __riscv_vsrl_vx_u64m8(vtbl_entry, 1, vl),
> vl); \
> +       } \
> +}
> +
> +DECLARE_VECTOR_FN(1b, 0)
> +DECLARE_VECTOR_FN(2b, 1)
> +DECLARE_VECTOR_FN(4b, 2)
> +DECLARE_VECTOR_FN(8b, 3)
> +
> +#endif
> diff --git a/lib/fib/dir24_8_rvv.h b/lib/fib/dir24_8_rvv.h
> new file mode 100644
> index 0000000000..7be99f7882
> --- /dev/null
> +++ b/lib/fib/dir24_8_rvv.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright (c) 2025 Institute of Software Chinese Academy of Sciences
> (ISCAS).
> + */
> +
> +#ifndef _DIR248_RVV_H_
> +#define _DIR248_RVV_H_
> +
> +void
> +rte_dir24_8_vec_lookup_bulk_1b(void *p, const uint32_t *ips,
> +       uint64_t *next_hops, const unsigned int n);
> +
> +void
> +rte_dir24_8_vec_lookup_bulk_2b(void *p, const uint32_t *ips,
> +       uint64_t *next_hops, const unsigned int n);
> +
> +void
> +rte_dir24_8_vec_lookup_bulk_4b(void *p, const uint32_t *ips,
> +       uint64_t *next_hops, const unsigned int n);
> +
> +void
> +rte_dir24_8_vec_lookup_bulk_8b(void *p, const uint32_t *ips,
> +       uint64_t *next_hops, const unsigned int n);
> +
> +#endif /* _DIR248_RVV_H_ */
> diff --git a/lib/fib/meson.build b/lib/fib/meson.build
> index 6992ccc040..573fc50ff1 100644
> --- a/lib/fib/meson.build
> +++ b/lib/fib/meson.build
> @@ -10,4 +10,6 @@ deps += ['net']
>
>  if dpdk_conf.has('RTE_ARCH_X86_64')
>      sources_avx512 += files('dir24_8_avx512.c', 'trie_avx512.c')
> +elif dpdk_conf.has('RTE_ARCH_RISCV')
> +    sources += files('dir24_8_rvv.c')
>  endif
> --
> 2.50.0
>
>

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[PATCH v2 5/5] riscv: override machine_args only when default

[uk7b]

From: Sun Yuechi <sunyuechi@iscas.ac.cn>

Support using -Dcpu_instruction_set=rv64gcv to enable V extension.

Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
---
 config/riscv/meson.build | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index e3694cf2e6..f93ea3e145 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -111,13 +111,15 @@ arch_config = arch_config[arch_id]
 # Concatenate flags respecting priorities.
 dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])
 
-# apply supported machine args
-machine_args = [] # Clear previous machine args
-foreach flag: arch_config['machine_args']
-    if cc.has_argument(flag)
-        machine_args += flag
-    endif
-endforeach
+if (cpu_instruction_set == 'rv64gc')
+    # apply supported machine args
+    machine_args = [] # Clear previous machine args
+    foreach flag: arch_config['machine_args']
+        if cc.has_argument(flag)
+            machine_args += flag
+        endif
+    endforeach
+endif
 
 # check if we can do buildtime detection of extensions supported by the target
 riscv_extension_macros = false
-- 
2.50.0

Re: [PATCH v2 5/5] riscv: override machine_args only when default

[Stanisław Kardach]

[-- Attachment #1: Type: text/plain, Size: 1466 bytes --]

On Tue, 1 Jul 2025, 20:21 , <uk7b@foxmail.com> wrote:

> From: Sun Yuechi <sunyuechi@iscas.ac.cn>
>
> Support using -Dcpu_instruction_set=rv64gcv to enable V extension.
>
> Signed-off-by: Sun Yuechi <sunyuechi@iscas.ac.cn>
>
Reviewed-by: Stanisław Kardach <stanislaw.kardach@gmail.com>

> ---
>  config/riscv/meson.build | 16 +++++++++-------
>  1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/config/riscv/meson.build b/config/riscv/meson.build
> index e3694cf2e6..f93ea3e145 100644
> --- a/config/riscv/meson.build
> +++ b/config/riscv/meson.build
> @@ -111,13 +111,15 @@ arch_config = arch_config[arch_id]
>  # Concatenate flags respecting priorities.
>  dpdk_flags = flags_common + vendor_config['flags'] +
> arch_config.get('flags', [])
>
> -# apply supported machine args
> -machine_args = [] # Clear previous machine args
> -foreach flag: arch_config['machine_args']
> -    if cc.has_argument(flag)
> -        machine_args += flag
> -    endif
> -endforeach
> +if (cpu_instruction_set == 'rv64gc')
> +    # apply supported machine args
> +    machine_args = [] # Clear previous machine args
> +    foreach flag: arch_config['machine_args']
> +        if cc.has_argument(flag)
> +            machine_args += flag
> +        endif
> +    endforeach
> +endif
>
>  # check if we can do buildtime detection of extensions supported by the
> target
>  riscv_extension_macros = false
> --
> 2.50.0
>
>

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