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References: <20240812073209.1924286-1-zhang.yong25@zte.com.cn>
<20241014081117.1704528-10-zhang.yong25@zte.com.cn>
In-Reply-To: <20241014081117.1704528-10-zhang.yong25@zte.com.cn>
From: Patrick Robb <probb@iol.unh.edu>
Date: Tue, 15 Oct 2024 12:50:22 -0400
Message-ID: <CAJvnSUC-Shm=T7_5TZYHe-yQH_ZZCygXzRAkaFDJf-4vZjHCBw@mail.gmail.com>
Subject: Re: [v3 5/5] raw/gdtc: add support for dequeue operation
To: Yong Zhang <zhang.yong25@zte.com.cn>
Cc: thomas@monjalon.net, techboard@dpdk.org, dev@dpdk.org,
wang.yong19@zte.com.cn, li.min10@zte.com.cn, ran.ming@zte.com.cn
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It looks like this did not get processed correctly by patchwork, or there
is an issue with the patchfiles.
https://patchwork.dpdk.org/project/dpdk/list/?series=3D&submitter=3D&state=
=3D&q=3Dgdtc&archive=3D&delegate=3D
Can you resubmit? It was not picked up by 3/4 of the CI labs.
On Mon, Oct 14, 2024 at 4:16=E2=80=AFAM Yong Zhang <zhang.yong25@zte.com.cn=
> wrote:
> Add rawdev dequeue operation for gdtc devices.
>
> Signed-off-by: Yong Zhang <zhang.yong25@zte.com.cn>
> ---
> drivers/raw/gdtc/gdtc_rawdev.c | 113 +++++++++++++++++++++++++++++++++
> 1 file changed, 113 insertions(+)
>
>
> diff --git a/drivers/raw/gdtc/gdtc_rawdev.c b/drivers/raw/gdtc/gdtc_rawde=
v.c
> index 03f7cc1a8e..8e9543f402 100644
> --- a/drivers/raw/gdtc/gdtc_rawdev.c
> +++ b/drivers/raw/gdtc/gdtc_rawdev.c
> @@ -88,6 +88,8 @@
> #define LOW32_MASK 0xffffffff
> #define LOW16_MASK 0xffff
>
> +#define ZXDH_GDMA_TC_CNT_MAX 0x10000
> +
> #define IDX_TO_ADDR(addr, idx, t) \
> ((t)((uintptr_t)(addr) + (idx) * sizeof(struct zxdh_gdma_buff_desc))=
)
>
> @@ -526,6 +528,116 @@ zxdh_gdma_rawdev_enqueue_bufs(struct rte_rawdev *de=
v,
>
> return count;
> }
> +
> +static inline void
>
> +zxdh_gdma_used_idx_update(struct zxdh_gdma_queue *queue, uint16_t cnt, u=
int8_t data_bd_err)
> +{
> + uint16_t idx =3D 0;
> +
> + if (queue->sw_ring.used_idx + cnt < queue->queue_size)
> + queue->sw_ring.used_idx +=3D cnt;
> + else
>
> + queue->sw_ring.used_idx =3D queue->sw_ring.used_idx + cnt - queu=
e->queue_size;
> +
> + if (data_bd_err =3D=3D 1) {
> + /* Update job status, the last job status is error */
> + if (queue->sw_ring.used_idx =3D=3D 0)
> + idx =3D queue->queue_size - 1;
> + else
> + idx =3D queue->sw_ring.used_idx - 1;
> +
> + queue->sw_ring.job[idx]->status =3D 1;
> + }
> +}
> +
> +static int
> +zxdh_gdma_rawdev_dequeue_bufs(struct rte_rawdev *dev,
> + __rte_unused struct rte_rawdev_buf **buffers,
> + uint32_t count,
> + rte_rawdev_obj_t context)
> +{
> + struct zxdh_gdma_queue *queue =3D NULL;
> + struct zxdh_gdma_enqdeq *e_context =3D NULL;
> + uint16_t queue_id =3D 0;
> + uint32_t val =3D 0;
> + uint16_t tc_cnt =3D 0;
> + uint16_t diff_cnt =3D 0;
> + uint16_t i =3D 0;
> + uint16_t bd_idx =3D 0;
> + uint64_t next_bd_addr =3D 0;
> + uint8_t data_bd_err =3D 0;
> +
> + if ((dev =3D=3D NULL) || (context =3D=3D NULL))
> + return -EINVAL;
> +
> + e_context =3D (struct zxdh_gdma_enqdeq *)context;
> + queue_id =3D e_context->vq_id;
> + queue =3D zxdh_gdma_get_queue(dev, queue_id);
> + if ((queue =3D=3D NULL) || (queue->enable =3D=3D 0))
> + return -EINVAL;
> +
> + if (queue->sw_ring.pend_cnt =3D=3D 0)
> + goto deq_job;
> +
> + /* Get data transmit count */
> + val =3D zxdh_gdma_read_reg(dev, queue_id, ZXDH_GDMA_TC_CNT_OFFSET);
> + tc_cnt =3D val & LOW16_MASK;
> + if (tc_cnt >=3D queue->tc_cnt)
> + diff_cnt =3D tc_cnt - queue->tc_cnt;
> + else
> + diff_cnt =3D tc_cnt + ZXDH_GDMA_TC_CNT_MAX - queue->tc_cnt;
> +
> + queue->tc_cnt =3D tc_cnt;
> +
> + /* Data transmit error, channel stopped */
> + if ((val & ZXDH_GDMA_ERR_STATUS) !=3D 0) {
>
> + next_bd_addr =3D zxdh_gdma_read_reg(dev, queue_id, ZXDH_GDMA_LL=
I_L_OFFSET);
> + next_bd_addr |=3D ((uint64_t)zxdh_gdma_read_reg(dev, queue_id,
> + ZXDH_GDMA_LLI_H_OFFSET) << 32);
> + next_bd_addr =3D next_bd_addr << 6;
>
> + bd_idx =3D (next_bd_addr - queue->ring.ring_mem) / sizeof(struct=
zxdh_gdma_buff_desc);
>
> + if ((val & ZXDH_GDMA_SRC_DATA_ERR) || (val & ZXDH_GDMA_DST_ADDR_=
ERR)) {
> + diff_cnt++;
> + data_bd_err =3D 1;
> + }
>
> + ZXDH_PMD_LOG(INFO, "queue%d is err(0x%x) next_bd_idx:%u ll_addr:=
0x%"PRIx64" def user:0x%x",
> + queue_id, val, bd_idx, next_bd_addr, queue->user);
> +
> + ZXDH_PMD_LOG(INFO, "Clean up error status");
> + val =3D ZXDH_GDMA_ERR_STATUS | ZXDH_GDMA_ERR_INTR_ENABLE;
> + zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_TC_CNT_OFFSET, val)=
;
> +
> + ZXDH_PMD_LOG(INFO, "Restart channel");
> + zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_XFERSIZE_OFFSET, 0)=
;
> + zxdh_gdma_control_cal(&val, 0);
> + zxdh_gdma_write_reg(dev, queue_id, ZXDH_GDMA_CONTROL_OFFSET, val=
);
> + }
> +
> + if (diff_cnt !=3D 0) {
> + zxdh_gdma_used_idx_update(queue, diff_cnt, data_bd_err);
> + queue->sw_ring.deq_cnt +=3D diff_cnt;
> + queue->sw_ring.pend_cnt -=3D diff_cnt;
> + }
> +
> +deq_job:
> + if (queue->sw_ring.deq_cnt =3D=3D 0)
> + return 0;
> + else if (queue->sw_ring.deq_cnt < count)
> + count =3D queue->sw_ring.deq_cnt;
> +
> + queue->sw_ring.deq_cnt -=3D count;
> +
> + for (i =3D 0; i < count; i++) {
> + e_context->job[i] =3D queue->sw_ring.job[queue->sw_ring.deq_idx]=
;
> + queue->sw_ring.job[queue->sw_ring.deq_idx] =3D NULL;
> + if (++queue->sw_ring.deq_idx >=3D queue->queue_size)
> + queue->sw_ring.deq_idx -=3D queue->queue_size;
> + }
> + queue->sw_ring.free_cnt +=3D count;
> +
> + return count;
> +}
> +
> static const struct rte_rawdev_ops zxdh_gdma_rawdev_ops =3D {
> .dev_info_get =3D zxdh_gdma_rawdev_info_get,
> .dev_configure =3D zxdh_gdma_rawdev_configure,
>
> @@ -540,6 +652,7 @@ static const struct rte_rawdev_ops zxdh_gdma_rawdev_o=
ps =3D {
> .attr_get =3D zxdh_gdma_rawdev_get_attr,
>
> .enqueue_bufs =3D zxdh_gdma_rawdev_enqueue_bufs,
> + .dequeue_bufs =3D zxdh_gdma_rawdev_dequeue_bufs,
> };
>
> static int
> --
> 2.43.0
>
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