From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7E37143C0C; Fri, 1 Mar 2024 17:09:26 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 68C24402EA; Fri, 1 Mar 2024 17:09:26 +0100 (CET) Received: from mail-ot1-f45.google.com (mail-ot1-f45.google.com [209.85.210.45]) by mails.dpdk.org (Postfix) with ESMTP id 30EEB402E0 for ; Fri, 1 Mar 2024 17:09:24 +0100 (CET) Received: by mail-ot1-f45.google.com with SMTP id 46e09a7af769-6e4d1448d31so115801a34.0 for ; Fri, 01 Mar 2024 08:09:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iol.unh.edu; s=unh-iol; t=1709309363; x=1709914163; darn=dpdk.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=DgBdCKzz6GRvUgzwVi30WjpkZ2iQ2bBKHyOD5ybKVrQ=; b=HDUOqJUCWRAiUVOcZDLlGPqgyO/OUyovdmiY+vFBgxquqVLHa4AXbPJGdqxriq/2xM 1b8E7dMh8n14qZ1JIkADa6rQGv8YZOWD+wXYqqPP6fXEvHvE5fdZf7uAh7JdHV2CHmSk hNL1UUUAxgEtx+9vj/ybn7RsXw4Jh2frMILfk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709309363; x=1709914163; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=DgBdCKzz6GRvUgzwVi30WjpkZ2iQ2bBKHyOD5ybKVrQ=; b=brlszlYUwx/L3MwkXh89vc+uf27MmfwEJiCcZfj+pTdqprdrKnEinhDM5BacKapSbH b4bi5b/6xlGeT6s0Gd1J7pJqa/XZokvv3zSwhn13fPj3ITxiAEmDSczcYHb+6tdz2SKI iP7V2HMoquDI2G4AG3J/ZQrTdFsEEssFzXIQLBrymsbxisEl2exS6daBoWkl/huz40iM PbZ1/hLu6cHjg49MDKIwDYYDn2XI55pnnh6TfVCIp2yl608EOkEbVY96sfahfkoY6mbb 7n7aLYvbJKmRjB4QhNnWBdTrm80usm4mg1j3LL7zEBo4XHfXcl1DlViXZh3aMtt+g3Aq KneQ== X-Forwarded-Encrypted: i=1; AJvYcCXG6h2lzunTykQ+9nEMlpifbGzEqgOun08dZ7C1ZQIEr5hDTzm/8s3UqTQ4Y5R4f4L/YStQ/29H9IQUSOA= X-Gm-Message-State: AOJu0Yxcb3Y+GuOZVRqRAE6JBbxB/OAr3D4VfTZmc+jN4PbBxfnlnXkZ C02g6XCtr7qsgIcBeJwIvZ6yZeJW/gqhEFZRRdtnyMTji1TCPAYME78/cLNLmbj47cwr8S6ZWl2 jOijL/6X/MfylpxJpiYxyG7caAfDP7OB8nzD1Fw== X-Google-Smtp-Source: AGHT+IFLnS4+EYkoLgF1vsADrj6xQg2ZM7NQUsx+LkGhg/FDE9UHTPwqXTskoBjnmq67d19PK5YNedqV2dGpeYMv2Vs= X-Received: by 2002:a4a:3059:0:b0:5a0:d409:35b9 with SMTP id z25-20020a4a3059000000b005a0d40935b9mr1856786ooz.1.1709309363512; Fri, 01 Mar 2024 08:09:23 -0800 (PST) MIME-Version: 1.0 References: <20240301124246.1216467-1-suanmingm@nvidia.com> In-Reply-To: <20240301124246.1216467-1-suanmingm@nvidia.com> From: Patrick Robb Date: Fri, 1 Mar 2024 11:09:12 -0500 Message-ID: Subject: Re: [PATCH] crypto/mlx5: add max segment assert To: Suanming Mou Cc: Matan Azrad , dev@dpdk.org Content-Type: multipart/alternative; boundary="0000000000006c7d9506129b99fa" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --0000000000006c7d9506129b99fa Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable The Community Lab had an infra failure this morning and some patches including yours were affected with false failures. The issue is now resolved and we are rerunning the tests in question for all patches submitted today. On Fri, Mar 1, 2024 at 7:43=E2=80=AFAM Suanming Mou = wrote: > Currently, for multi-segment mbuf, before crypto WQE an extra > UMR WQE will be introduced to build the contiguous memory space. > Crypto WQE uses that contiguous memory space key as input. > > This commit adds assert for maximum supported segments in debug > mode in case the segments exceed UMR's limitation. > > Signed-off-by: Suanming Mou > Acked-by: Matan Azrad > --- > drivers/crypto/mlx5/mlx5_crypto_gcm.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c > b/drivers/crypto/mlx5/mlx5_crypto_gcm.c > index 8b9953b46d..fc6ade6711 100644 > --- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c > +++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c > @@ -441,6 +441,9 @@ mlx5_crypto_gcm_get_op_info(struct mlx5_crypto_qp *qp= , > op_info->digest =3D NULL; > op_info->src_addr =3D aad_addr; > if (op->sym->m_dst && op->sym->m_dst !=3D m_src) { > + /* Add 2 for AAD and digest. */ > + MLX5_ASSERT((uint32_t)(m_dst->nb_segs + m_src->nb_segs + > 2) < > + qp->priv->max_klm_num); > op_info->is_oop =3D true; > m_dst =3D op->sym->m_dst; > dst_addr =3D rte_pktmbuf_mtod_offset(m_dst, void *, > op->sym->aead.data.offset); > @@ -457,6 +460,9 @@ mlx5_crypto_gcm_get_op_info(struct mlx5_crypto_qp *qp= , > op_info->need_umr =3D true; > return; > } > + } else { > + /* Add 2 for AAD and digest. */ > + MLX5_ASSERT((uint32_t)(m_src->nb_segs) + 2 < > qp->priv->max_klm_num); > } > if (m_src->nb_segs > 1) { > op_info->need_umr =3D true; > -- > 2.34.1 > > --0000000000006c7d9506129b99fa Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
The Community Lab had an infra failure th= is morning and some patches including yours were affected with false failur= es. The issue is now resolved and we are rerunning the tests in question fo= r all patches submitted today.=C2=A0

On Fri, Mar 1, 2024 at 7:43=E2=80=AFAM = Suanming Mou <suanmingm@nvidia.c= om> wrote:
suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
=C2=A0drivers/crypto/mlx5/mlx5_crypto_gcm.c | 6 ++++++
=C2=A01 file changed, 6 insertions(+)

diff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/ml= x5_crypto_gcm.c
index 8b9953b46d..fc6ade6711 100644
--- a/drivers/crypto/mlx5/mlx5_crypto_gcm.c
+++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c
@@ -441,6 +441,9 @@ mlx5_crypto_gcm_get_op_info(struct mlx5_crypto_qp *qp,<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 op_info->digest =3D NULL;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 op_info->src_addr =3D aad_addr;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (op->sym->m_dst && op->sym-= >m_dst !=3D m_src) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Add 2 for AAD an= d digest. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MLX5_ASSERT((uint32= _t)(m_dst->nb_segs + m_src->nb_segs + 2) <
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0qp->priv->max_klm_num);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 op_info->is_oop = =3D true;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 m_dst =3D op->sy= m->m_dst;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dst_addr =3D rte_pk= tmbuf_mtod_offset(m_dst, void *, op->sym->aead.data.offset);
@@ -457,6 +460,9 @@ mlx5_crypto_gcm_get_op_info(struct mlx5_crypto_qp *qp,<= br> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 op_info->need_umr =3D true;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 return;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0} else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Add 2 for AAD an= d digest. */
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MLX5_ASSERT((uint32= _t)(m_src->nb_segs) + 2 < qp->priv->max_klm_num);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (m_src->nb_segs > 1) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 op_info->need_um= r =3D true;
--
2.34.1


--0000000000006c7d9506129b99fa--