From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8BFC3A00BE; Thu, 16 Jun 2022 10:51:20 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 76CBB42BCB; Thu, 16 Jun 2022 10:51:20 +0200 (CEST) Received: from mail-qk1-f171.google.com (mail-qk1-f171.google.com [209.85.222.171]) by mails.dpdk.org (Postfix) with ESMTP id E27D14281E for ; Thu, 16 Jun 2022 10:51:18 +0200 (CEST) Received: by mail-qk1-f171.google.com with SMTP id d23so565042qke.0 for ; Thu, 16 Jun 2022 01:51:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=BTD0h3RV7/DruUGS/rrrwMi+p70wzg2n0Mph9sV4hr4=; b=eJaOdfR4IakEBJwczw+c4N584g0rJeVLFmHOrS8JM5Qv/50PTj8P3w9RYcFXhDuxqz 3DPOX301pS0ZBoMM6snGu04VnVxCPDQhv6hypEnANtPSNrNX0uP/5+jJVYHVMrNaYkXc aZ5wiypHcLAKh7QnsioMDAEz/Yeui2LI6maFVii64fYIUboiHlqCDaFmk97DjARbwogo ZNXYr1Wiw+JhnjH+tgyiuITb8vszM8Yhf6tJZoEDYhr2TqEBzflZdQxd/W2LTC80oANd +m1vWwR8Jeprw27+rAjHOokpTht3GDB/TCXnBe/hqr+MUw62LuXBEQBwseJ7+FYay0eC V+ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=BTD0h3RV7/DruUGS/rrrwMi+p70wzg2n0Mph9sV4hr4=; b=5/ckBmDSuXgzhADSVJaPg30kWMXYEiJTgZO7woRiAEZOrWJEN7IfD1EFV9UAnE1jlY nMgXNqDs812QYgpnmG1tOpqF0E3ZvY5c+buPbOj7SGDWiXpFCDMfIxWRcYg+STkjJDPa TGs+h2aXdbsxoNUStVvDJCcA39+VEQeCXSMWdsYkfp6Llmc2POJzFNa3UzkPW4p2bRGT dTA0z2GzTzYEkeZK4aCISR5zmbToj+HTXLp+1e3j2QMlI54pDj9lRHqYg5rgyu4kPaOQ UeCXiPRwCFED+xRUu8eINivHMlqhgq0qQGquuBy4BUhAPWjV31bveeO/ZxBe59/Vg31p GIaQ== X-Gm-Message-State: AJIora+WS/I80fsBG5f0+QKmaigZ+nvgUtuJdt/toxbBY1O5OyA4nh4j sHXXguY5T3shWjPvxuhS8nytdyDEwsxy2U/kHQlQnUuvAyM= X-Google-Smtp-Source: AGRyM1soUcaMLbgoub56fxg9TDEb58zCJ5qCMmMCu+8UiQDkHkxxK7GIbW8SHs1LkammFW7/C9QDH0djlkB7cKo4Cno= X-Received: by 2002:ae9:e851:0:b0:6a7:5a0f:f7b9 with SMTP id a78-20020ae9e851000000b006a75a0ff7b9mr2747324qkg.316.1655369478310; Thu, 16 Jun 2022 01:51:18 -0700 (PDT) MIME-Version: 1.0 References: <20220616070743.30658-1-ndabilpuram@marvell.com> <20220616070743.30658-10-ndabilpuram@marvell.com> In-Reply-To: <20220616070743.30658-10-ndabilpuram@marvell.com> From: Jerin Jacob Date: Thu, 16 Jun 2022 14:20:52 +0530 Message-ID: Subject: Re: [PATCH 10/12] net/cnxk: resize CQ for Rx security for errata To: Nithin Dabilpuram Cc: Jerin Jacob , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , dpdk-dev Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Thu, Jun 16, 2022 at 12:40 PM Nithin Dabilpuram wrote: > > Resize CQ for Rx security offload in case of HW errata. > > ci: skip_checkpatch skip_klocwork Remove this. Please fix any ./devtools/checkpatches.sh ./devtools/check-git-log.sh in issues in the series. > > Signed-off-by: Nithin Dabilpuram > --- > drivers/net/cnxk/cnxk_ethdev.c | 43 +++++++++++++++++++++++++++++++++++++++++- > drivers/net/cnxk/cnxk_ethdev.h | 2 +- > 2 files changed, 43 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c > index 4ea1617..2418290 100644 > --- a/drivers/net/cnxk/cnxk_ethdev.c > +++ b/drivers/net/cnxk/cnxk_ethdev.c > @@ -5,6 +5,8 @@ > > #include > > +#define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL) > + > static inline uint64_t > nix_get_rx_offload_capa(struct cnxk_eth_dev *dev) > { > @@ -40,6 +42,39 @@ nix_get_speed_capa(struct cnxk_eth_dev *dev) > return speed_capa; > } > > +static uint32_t > +nix_inl_cq_sz_clamp_up(struct roc_nix *nix, struct rte_mempool *mp, > + uint32_t nb_desc) > +{ > + struct roc_nix_rq *inl_rq; > + uint64_t limit; > + > + if (!roc_errata_cpt_hang_on_x2p_bp()) > + return nb_desc; > + > + /* CQ should be able to hold all buffers in first pass RQ's aura > + * this RQ's aura. > + */ > + inl_rq = roc_nix_inl_dev_rq(nix); > + if (!inl_rq) { > + /* This itself is going to be inline RQ's aura */ > + limit = roc_npa_aura_op_limit_get(mp->pool_id); > + } else { > + limit = roc_npa_aura_op_limit_get(inl_rq->aura_handle); > + /* Also add this RQ's aura if it is different */ > + if (inl_rq->aura_handle != mp->pool_id) > + limit += roc_npa_aura_op_limit_get(mp->pool_id); > + } > + nb_desc = PLT_MAX(limit + 1, nb_desc); > + if (nb_desc > CNXK_NIX_CQ_INL_CLAMP_MAX) { > + plt_warn("Could not setup CQ size to accommodate" > + " all buffers in related auras (%" PRIu64 ")", > + limit); > + nb_desc = CNXK_NIX_CQ_INL_CLAMP_MAX; > + } > + return nb_desc; > +} > + > int > cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev) > { > @@ -504,7 +539,7 @@ cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid) > > int > cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, > - uint16_t nb_desc, uint16_t fp_rx_q_sz, > + uint32_t nb_desc, uint16_t fp_rx_q_sz, > const struct rte_eth_rxconf *rx_conf, > struct rte_mempool *mp) > { > @@ -552,6 +587,12 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, > dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) > roc_nix_inl_dev_xaq_realloc(mp->pool_id); > > + /* Increase CQ size to Aura size to avoid CQ overflow and > + * then CPT buffer leak. > + */ > + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) > + nb_desc = nix_inl_cq_sz_clamp_up(nix, mp, nb_desc); > + > /* Setup ROC CQ */ > cq = &dev->cqs[qid]; > cq->qid = qid; > diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h > index a4e96f0..4cb7c9e 100644 > --- a/drivers/net/cnxk/cnxk_ethdev.h > +++ b/drivers/net/cnxk/cnxk_ethdev.h > @@ -530,7 +530,7 @@ int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, > uint16_t nb_desc, uint16_t fp_tx_q_sz, > const struct rte_eth_txconf *tx_conf); > int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, > - uint16_t nb_desc, uint16_t fp_rx_q_sz, > + uint32_t nb_desc, uint16_t fp_rx_q_sz, > const struct rte_eth_rxconf *rx_conf, > struct rte_mempool *mp); > int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid); > -- > 2.8.4 >