From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D80DDA04A2; Thu, 3 Mar 2022 10:25:48 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9615040687; Thu, 3 Mar 2022 10:25:47 +0100 (CET) Received: from mail-io1-f50.google.com (mail-io1-f50.google.com [209.85.166.50]) by mails.dpdk.org (Postfix) with ESMTP id 3E2B740141 for ; Thu, 3 Mar 2022 10:25:46 +0100 (CET) Received: by mail-io1-f50.google.com with SMTP id d19so5079931ioc.8 for ; Thu, 03 Mar 2022 01:25:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=txdKCZUdCI68EQkmQJ0FuQ68XHOrpH75wC1BcokXaQk=; b=KonzUAt3m07kp11geDxyOtj7Yi3/oQEwq2Rac3snRh/uEv/nksV5Mj86WmLGyrVIkN nzFMZiIwAXn/Ng009k/JSApOM473Mu8CM8d4bP9jEexhKcIp/Qbu/O13QKyVG8DfM5Gk Yg4yIGpWwy6xPYXhvesBb13a5nyhUCyG6DYQCv8bGtz1FhTv7vIFMlUyZwW1JiulP/hK MClpPIBbS1DqDEL+b64J7NFF/xwiVlzPsVLaWpe6342/qwuV7JHQdxESkmx8NXQmjscK mtDZtpAzn8+IwIAL8L+9fKGMlAQRKSyb3EUUSFrH/ZAAwAtaruarTODAKI3HjGyCt11Y E6GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=txdKCZUdCI68EQkmQJ0FuQ68XHOrpH75wC1BcokXaQk=; b=zTVY3/YPT5hCGGaiYhvX5ytJCe+7jKywh2rk9djOP+WTA/2JlP6RTkv55MZ6ok5Gcs +z4ikgv2EBGeWBpXhrdbLF/HNRC2kvb8QAa7SrE+XypVsRFBYRYk5L5iAPKCLkeJOIgq 27hQ4Y8SPAwJXqMgBPKV45C6qU5fmu/x33f+i9oNftIjXAWdboxJikudEmkXSpMIfZEp HwTgnsorQmcuk3tv/XTm9tvZ+2aQKRnKst7Rxfb2kVICljgTNQrP0v88LMFGvb0s/oQ8 IBZNNposcGzTXCOYPfqFJAGgD6yNLfILb7E8JZF4CKGOtDFcxktvZ4HoE3x7d7kgeivZ qf/A== X-Gm-Message-State: AOAM530dsOMX+2hb1PMnFr8r+XVD9SrTg5eA9jKJJ52UqktZ4Eu6zqcg cyIyHXuIbL1m8L79TXED0UYBlBkML6NFue+ta6zafobXizvLIQ== X-Google-Smtp-Source: ABdhPJxf4ZZevi6w5ZDJ+7AJruRLq4cHSDVTIWUMPsI0fDX/w7NCBGVLX0Ekmx2ANlACCniwy1h4WdmxLyXVjmYWOG0= X-Received: by 2002:a02:aca:0:b0:314:9da8:7be0 with SMTP id 193-20020a020aca000000b003149da87be0mr29315262jaw.280.1646299545616; Thu, 03 Mar 2022 01:25:45 -0800 (PST) MIME-Version: 1.0 References: <1646233928-4124603-1-git-send-email-timothy.mcdaniel@intel.com> In-Reply-To: <1646233928-4124603-1-git-send-email-timothy.mcdaniel@intel.com> From: Jerin Jacob Date: Thu, 3 Mar 2022 14:55:19 +0530 Message-ID: Subject: Re: [PATCH] event/dlb2: fix invalid shift value To: Timothy McDaniel Cc: Jerin Jacob , John McNamara , dpdk-dev Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Wed, Mar 2, 2022 at 8:42 PM Timothy McDaniel wrote: > > Add a check to ensure that all shift counts are valid. > Shifting by more than 63 bits may result in undefined behavior, as > noted during coverity scan. > > Fixes: e697f35dbdd1 ("event/dlb2: update rolling mask used for dequeue") > Coverity issue: 376527 Applied to dpdk-next-net-eventdev/for-main. Thanks > Signed-off-by: Timothy McDaniel > --- > drivers/event/dlb2/dlb2.c | 18 ++++++++++-------- > 1 file changed, 10 insertions(+), 8 deletions(-) > > diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c > index 09abdd1660..7789dd74e0 100644 > --- a/drivers/event/dlb2/dlb2.c > +++ b/drivers/event/dlb2/dlb2.c > @@ -3916,15 +3916,17 @@ dlb2_hw_dequeue_sparse(struct dlb2_eventdev *dlb2, > &events[num], > &qes[0], > num_avail); > - num += n_iter; > - /* update rolling_mask for vector code support */ > - m_rshift = qm_port->cq_rolling_mask >> n_iter; > - m_lshift = qm_port->cq_rolling_mask << (64 - n_iter); > - m2_rshift = qm_port->cq_rolling_mask_2 >> n_iter; > - m2_lshift = qm_port->cq_rolling_mask_2 << > + if (n_iter != 0) { > + num += n_iter; > + /* update rolling_mask for vector code support */ > + m_rshift = qm_port->cq_rolling_mask >> n_iter; > + m_lshift = qm_port->cq_rolling_mask << (64 - n_iter); > + m2_rshift = qm_port->cq_rolling_mask_2 >> n_iter; > + m2_lshift = qm_port->cq_rolling_mask_2 << > (64 - n_iter); > - qm_port->cq_rolling_mask = (m_rshift | m2_lshift); > - qm_port->cq_rolling_mask_2 = (m2_rshift | m_lshift); > + qm_port->cq_rolling_mask = (m_rshift | m2_lshift); > + qm_port->cq_rolling_mask_2 = (m2_rshift | m_lshift); > + } > } else { /* !use_scalar */ > num_avail = dlb2_recv_qe_sparse_vec(qm_port, > &events[num], > -- > 2.25.1 >