[PATCH 1/6] net/cnxk: stale offload flag reset

[PATCH 1/6] net/cnxk: stale offload flag reset

[Harman Kalra]

From: Amit Prakash Shukla <amitprakashs@marvell.com>

mbuf buffer is not reset on tx and hence few fields has stale data from
previous packets. Due to stale offload flags, in one of the scenarios
with OVS, VxLAN offload flag was set while packet did not have the VxLAN
header. In the OVS packet path, the flag was read and accordingly VxLAN
processing was done but as packet did not have VxLAN header it caused
segfault.

This patch resets mbuf offload flags in rx burst function.

Signed-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>
---
 drivers/net/cnxk/cnxk_eswitch_rxtx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cnxk_eswitch_rxtx.c b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
index d57e32b091..0200392f2d 100644
--- a/drivers/net/cnxk/cnxk_eswitch_rxtx.c
+++ b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
@@ -194,7 +194,7 @@ cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			mbuf->vlan_tci = rx->vtag0_tci;
 		/* Populate RSS hash */
 		mbuf->hash.rss = cqe->tag;
-		mbuf->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
+		mbuf->ol_flags = RTE_MBUF_F_RX_RSS_HASH;
 		pkts[pkt] = mbuf;
 		roc_prefetch_store_keep(mbuf);
 		plt_esw_dbg("Packet %d rec on queue %d esw qid %d hash %x mbuf %p vlan tci %d",
-- 
2.18.0

[PATCH 2/6] net/cnxk: add MTU set ops

[Harman Kalra]

From: Ankur Dwivedi <adwivedi@marvell.com>

Implement mtu set ops for representor ports

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
---
 drivers/net/cnxk/cnxk_rep.h     |  1 +
 drivers/net/cnxk/cnxk_rep_ops.c | 34 ++++++++++++++++++++++++++++++++-
 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cnxk_rep.h b/drivers/net/cnxk/cnxk_rep.h
index 9bdea47bd4..ad89649702 100644
--- a/drivers/net/cnxk/cnxk_rep.h
+++ b/drivers/net/cnxk/cnxk_rep.h
@@ -146,5 +146,6 @@ int cnxk_rep_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 			      unsigned int n);
 int cnxk_rep_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 				    struct rte_eth_xstat_name *xstats_names, unsigned int n);
+int cnxk_rep_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
 
 #endif /* __CNXK_REP_H__ */
diff --git a/drivers/net/cnxk/cnxk_rep_ops.c b/drivers/net/cnxk/cnxk_rep_ops.c
index 8bcb689468..888842fa90 100644
--- a/drivers/net/cnxk/cnxk_rep_ops.c
+++ b/drivers/net/cnxk/cnxk_rep_ops.c
@@ -821,6 +821,37 @@ cnxk_rep_xstats_get_names_by_id(__rte_unused struct rte_eth_dev *eth_dev, const
 	return n;
 }
 
+int
+cnxk_rep_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
+{
+	struct cnxk_rep_dev *rep_dev = cnxk_rep_pmd_priv(eth_dev);
+	uint32_t frame_size = mtu + CNXK_NIX_L2_OVERHEAD;
+	int rc = -EINVAL;
+
+	/* Check if MTU is within the allowed range */
+	if ((frame_size - RTE_ETHER_CRC_LEN) < NIX_MIN_HW_FRS) {
+		plt_err("MTU is lesser than minimum");
+		goto exit;
+	}
+
+	if ((frame_size - RTE_ETHER_CRC_LEN) >
+	    ((uint32_t)roc_nix_max_pkt_len(&rep_dev->parent_dev->nix))) {
+		plt_err("MTU is greater than maximum");
+		goto exit;
+	}
+
+	frame_size -= RTE_ETHER_CRC_LEN;
+
+	/* Set frame size on Rx */
+	rc = roc_nix_mac_max_rx_len_set(&rep_dev->parent_dev->nix, frame_size);
+	if (rc) {
+		plt_err("Failed to max Rx frame length, rc=%d", rc);
+		goto exit;
+	}
+exit:
+	return rc;
+}
+
 /* CNXK platform representor dev ops */
 struct eth_dev_ops cnxk_rep_dev_ops = {
 	.dev_infos_get = cnxk_rep_dev_info_get,
@@ -844,5 +875,6 @@ struct eth_dev_ops cnxk_rep_dev_ops = {
 	.xstats_reset = cnxk_rep_xstats_reset,
 	.xstats_get_names = cnxk_rep_xstats_get_names,
 	.xstats_get_by_id = cnxk_rep_xstats_get_by_id,
-	.xstats_get_names_by_id = cnxk_rep_xstats_get_names_by_id
+	.xstats_get_names_by_id = cnxk_rep_xstats_get_names_by_id,
+	.mtu_set = cnxk_rep_mtu_set
 };
-- 
2.18.0

[PATCH 3/6] net/cnxk: add multi seg support in eswitch

[Harman Kalra]

From: Ankur Dwivedi <adwivedi@marvell.com>

Introducing multi segment support in eswitch driver to handle
packets of varying sizes.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
---
 drivers/net/cnxk/cnxk_eswitch.c      |   2 +-
 drivers/net/cnxk/cnxk_eswitch_rxtx.c | 167 ++++++++++++++++++++++++---
 2 files changed, 149 insertions(+), 20 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_eswitch.c b/drivers/net/cnxk/cnxk_eswitch.c
index f420d01ef8..6b1bfdd476 100644
--- a/drivers/net/cnxk/cnxk_eswitch.c
+++ b/drivers/net/cnxk/cnxk_eswitch.c
@@ -455,7 +455,7 @@ cnxk_eswitch_txq_setup(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid, uint1
 	memset(sq, 0, sizeof(struct roc_nix_sq));
 	sq->qid = qid;
 	sq->nb_desc = nb_desc;
-	sq->max_sqe_sz = NIX_MAXSQESZ_W8;
+	sq->max_sqe_sz = NIX_MAXSQESZ_W16;
 	if (sq->nb_desc >= CNXK_NIX_DEF_SQ_COUNT)
 		sq->fc_hyst_bits = 0x1;
 
diff --git a/drivers/net/cnxk/cnxk_eswitch_rxtx.c b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
index 0200392f2d..83a9c68a34 100644
--- a/drivers/net/cnxk/cnxk_eswitch_rxtx.c
+++ b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
@@ -39,31 +39,105 @@ eswitch_nix_rx_nb_pkts(struct roc_nix_cq *cq, const uint64_t wdata, const uint32
 }
 
 static inline void
-nix_cn9k_xmit_one(uint64_t *cmd, void *lmt_addr, const plt_iova_t io_addr)
+nix_cn9k_xmit_one(uint64_t *cmd, void *lmt_addr, const plt_iova_t io_addr, uint16_t segdw)
 {
 	uint64_t lmt_status;
 
 	do {
-		roc_lmt_mov(lmt_addr, cmd, 0);
+		roc_lmt_mov_seg(lmt_addr, (const void *)cmd, segdw);
 		lmt_status = roc_lmt_submit_ldeor(io_addr);
 	} while (lmt_status == 0);
 }
 
+static __rte_always_inline uint16_t
+cnxk_eswitch_prepare_mseg(struct rte_mbuf *m, union nix_send_sg_s *sg, uint64_t *cmd, uint64_t len,
+			  uint8_t off)
+{
+	union nix_send_sg_s l_sg;
+	struct rte_mbuf *m_next;
+	uint64_t nb_segs;
+	uint64_t *slist;
+	uint16_t segdw;
+	uint64_t dlen;
+
+	l_sg.u = 0;
+	l_sg.ld_type = NIX_SENDLDTYPE_LDD;
+	l_sg.subdc = NIX_SUBDC_SG;
+
+	dlen = m->data_len;
+	l_sg.u |= dlen;
+	len -= dlen;
+	nb_segs = m->nb_segs - 1;
+	m_next = m->next;
+	m->next = NULL;
+	slist = &cmd[off + 1];
+	l_sg.segs = 1;
+	*slist = rte_mbuf_data_iova(m);
+	slist++;
+	m = m_next;
+	if (!m)
+		goto done;
+
+	do {
+		uint64_t iova;
+
+		m_next = m->next;
+		iova = rte_mbuf_data_iova(m);
+		dlen = m->data_len;
+		len -= dlen;
+
+		nb_segs--;
+		m->next = NULL;
+
+		*slist = iova;
+		/* Set the segment length */
+		l_sg.u |= ((uint64_t)dlen << (l_sg.segs << 4));
+		l_sg.segs += 1;
+		slist++;
+		if (l_sg.segs > 2 && nb_segs) {
+			sg->u = l_sg.u;
+			/* Next SG subdesc */
+			sg = (union nix_send_sg_s *)slist;
+			l_sg.u = 0;
+			l_sg.ld_type = NIX_SENDLDTYPE_LDD;
+			l_sg.subdc = NIX_SUBDC_SG;
+			slist++;
+		}
+		m = m_next;
+	} while (nb_segs);
+done:
+	/* Write the last subdc out */
+	sg->u = l_sg.u;
+	segdw = (uint64_t *)slist - (uint64_t *)&cmd[off];
+	/* Roundup extra dwords to multiple of 2 */
+	segdw = (segdw >> 1) + (segdw & 0x1);
+	/* Default dwords */
+	segdw += (off >> 1);
+
+	return segdw;
+}
+
 uint16_t
 cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			  struct rte_mbuf **pkts, uint16_t nb_xmit, const uint16_t flags)
 {
 	struct roc_nix_sq *sq = &eswitch_dev->txq[qid].sqs;
 	struct roc_nix_rq *rq = &eswitch_dev->rxq[qid].rqs;
-	uint64_t aura_handle, cmd[6], data = 0;
 	uint16_t lmt_id, pkt = 0, nb_tx = 0;
 	struct nix_send_ext_s *send_hdr_ext;
 	struct nix_send_hdr_s *send_hdr;
+	uint64_t aura_handle, data = 0;
 	uint16_t vlan_tci = qid;
 	union nix_send_sg_s *sg;
 	uintptr_t lmt_base, pa;
 	int64_t fc_pkts, dw_m1;
+	uint64_t cmd_cn9k[16];
+	struct rte_mbuf *m;
 	rte_iova_t io_addr;
+	uint16_t segdw;
+	uint64_t *cmd;
+	uint64_t len;
+	uint8_t off;
 
 	if (unlikely(eswitch_dev->txq[qid].state != CNXK_ESWITCH_QUEUE_STATE_STARTED))
 		return 0;
@@ -78,9 +152,14 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 	/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
 	dw_m1 = cn10k_nix_tx_ext_subs(flags) + 1;
 
-	memset(cmd, 0, sizeof(cmd));
+	if (roc_model_is_cn9k()) {
+		memset(cmd_cn9k, 0, sizeof(cmd_cn9k));
+		cmd = &cmd_cn9k[0];
+	} else {
+		cmd = (uint64_t *)lmt_base;
+	}
+
 	send_hdr = (struct nix_send_hdr_s *)&cmd[0];
-	send_hdr->w0.sizem1 = dw_m1;
 	send_hdr->w0.sq = sq->qid;
 
 	if (dw_m1 >= 2) {
@@ -90,15 +169,15 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			send_hdr_ext->w1.vlan0_ins_ena = true;
 			/* 2B before end of l2 header */
 			send_hdr_ext->w1.vlan0_ins_ptr = 12;
-			send_hdr_ext->w1.vlan0_ins_tci = 0;
+			send_hdr_ext->w1.vlan0_ins_tci = vlan_tci;
 		}
-		sg = (union nix_send_sg_s *)&cmd[4];
+		off = 4;
 	} else {
-		sg = (union nix_send_sg_s *)&cmd[2];
+		off = 2;
 	}
 
+	sg = (union nix_send_sg_s *)&cmd[off];
 	sg->subdc = NIX_SUBDC_SG;
-	sg->segs = 1;
 	sg->ld_type = NIX_SENDLDTYPE_LDD;
 
 	/* Tx */
@@ -110,28 +189,28 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 		nb_tx = PLT_MIN(nb_xmit, (uint64_t)fc_pkts);
 
 	for (pkt = 0; pkt < nb_tx; pkt++) {
-		send_hdr->w0.total = pkts[pkt]->pkt_len;
-		if (pkts[pkt]->pool) {
-			aura_handle = pkts[pkt]->pool->pool_id;
+		m = pkts[pkt];
+		len = m->pkt_len;
+		send_hdr->w0.total = len;
+		if (m->pool) {
+			aura_handle = m->pool->pool_id;
 			send_hdr->w0.aura = roc_npa_aura_handle_to_aura(aura_handle);
 		} else {
 			send_hdr->w0.df = 1;
 		}
-		if (dw_m1 >= 2 && flags & NIX_TX_OFFLOAD_VLAN_QINQ_F)
-			send_hdr_ext->w1.vlan0_ins_tci = vlan_tci;
-		sg->seg1_size = pkts[pkt]->pkt_len;
-		*(plt_iova_t *)(sg + 1) = rte_mbuf_data_iova(pkts[pkt]);
+
+		segdw = cnxk_eswitch_prepare_mseg(m, sg, cmd, len, off);
+		send_hdr->w0.sizem1 = segdw - 1;
 
 		plt_esw_dbg("Transmitting pkt %d (%p) vlan tci %x on sq %d esw qid %d", pkt,
 			    pkts[pkt], vlan_tci, sq->qid, qid);
 		if (roc_model_is_cn9k()) {
-			nix_cn9k_xmit_one(cmd, sq->lmt_addr, sq->io_addr);
+			nix_cn9k_xmit_one(cmd, sq->lmt_addr, sq->io_addr, segdw);
 		} else {
-			cn10k_nix_xmit_mv_lmt_base(lmt_base, cmd, flags);
 			/* PA<6:4> = LMTST size-1 in units of 128 bits. Size of the first LMTST in
 			 * burst.
 			 */
-			pa = io_addr | (dw_m1 << 4);
+			pa = io_addr | ((segdw - 1) << 4);
 			data &= ~0x7ULL;
 			/*<15:12> = CNTM1: Count minus one of LMTSTs in the burst */
 			data = (0ULL << 12);
@@ -148,6 +227,54 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 	return nb_tx;
 }
 
+static __rte_always_inline void
+cnxk_eswitch_xtract_mseg(struct rte_mbuf *mbuf, const union nix_rx_parse_u *rx)
+{
+	const rte_iova_t *iova_list;
+	uint16_t later_skip = 0;
+	const rte_iova_t *eol;
+	struct rte_mbuf *head;
+	uint8_t nb_segs;
+	uint16_t sg_len;
+	uint64_t sg;
+
+	sg = *(const uint64_t *)(rx + 1);
+	nb_segs = (sg >> 48) & 0x3;
+	if (nb_segs == 1)
+		return;
+
+	mbuf->nb_segs = nb_segs;
+	mbuf->data_len = sg & 0xFFFF;
+	head = mbuf;
+	eol = ((const rte_iova_t *)(rx + 1) + ((rx->desc_sizem1 + 1) << 1));
+	sg = sg >> 16;
+	/* Skip SG_S and first IOVA*/
+	iova_list = ((const rte_iova_t *)(rx + 1)) + 2;
+	nb_segs--;
+	later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf;
+
+	while (nb_segs) {
+		mbuf->next = (struct rte_mbuf *)(*iova_list - later_skip);
+		mbuf = mbuf->next;
+
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
+
+		sg_len = sg & 0XFFFF;
+
+		mbuf->data_len = sg_len;
+		sg = sg >> 16;
+		nb_segs--;
+		iova_list++;
+
+		if (!nb_segs && (iova_list + 1 < eol)) {
+			sg = *(const uint64_t *)(iova_list);
+			nb_segs = (sg >> 48) & 0x3;
+			head->nb_segs += nb_segs;
+			iova_list = (const rte_iova_t *)(iova_list + 1);
+		}
+	}
+}
+
 uint16_t
 cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			  struct rte_mbuf **pkts, uint16_t nb_pkts)
@@ -195,6 +322,8 @@ cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 		/* Populate RSS hash */
 		mbuf->hash.rss = cqe->tag;
 		mbuf->ol_flags = RTE_MBUF_F_RX_RSS_HASH;
+
+		cnxk_eswitch_xtract_mseg(mbuf, rx);
 		pkts[pkt] = mbuf;
 		roc_prefetch_store_keep(mbuf);
 		plt_esw_dbg("Packet %d rec on queue %d esw qid %d hash %x mbuf %p vlan tci %d",
-- 
2.18.0

[PATCH 4/6] net/cnxk: increment number of flow pattern

[Harman Kalra]

From: Amit Prakash Shukla <amitprakashs@marvell.com>

Increment nb_pattern count to include RTE_FLOW_ITEM_TYPE_END.

Signed-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>
---
 drivers/net/cnxk/cnxk_rep_flow.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_rep_flow.c b/drivers/net/cnxk/cnxk_rep_flow.c
index d26f5aa12c..f1cf81a90c 100644
--- a/drivers/net/cnxk/cnxk_rep_flow.c
+++ b/drivers/net/cnxk/cnxk_rep_flow.c
@@ -171,6 +171,9 @@ populate_vxlan_encap_action_conf(const struct rte_flow_action_vxlan_encap *vxlan
 	for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++)
 		nb_patterns++;
 
+	/* +1 for RTE_FLOW_ITEM_TYPE_END */
+	nb_patterns++;
+
 	len = sizeof(uint64_t);
 	rte_memcpy(vxlan_encap_action_data, &nb_patterns, len);
 	pattern = vxlan_conf->definition;
-- 
2.18.0

Re: [PATCH 4/6] net/cnxk: increment number of flow pattern

[Jerin Jacob]

On Mon, Jun 24, 2024 at 1:20 PM Harman Kalra <hkalra@marvell.com> wrote:
>
> From: Amit Prakash Shukla <amitprakashs@marvell.com>
>
> Increment nb_pattern count to include RTE_FLOW_ITEM_TYPE_END.

Is n't fix? If so, Fixes tag

> Signed-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>
> ---
>  drivers/net/cnxk/cnxk_rep_flow.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/net/cnxk/cnxk_rep_flow.c b/drivers/net/cnxk/cnxk_rep_flow.c
> index d26f5aa12c..f1cf81a90c 100644
> --- a/drivers/net/cnxk/cnxk_rep_flow.c
> +++ b/drivers/net/cnxk/cnxk_rep_flow.c
> @@ -171,6 +171,9 @@ populate_vxlan_encap_action_conf(const struct rte_flow_action_vxlan_encap *vxlan
>         for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++)
>                 nb_patterns++;
>
> +       /* +1 for RTE_FLOW_ITEM_TYPE_END */
> +       nb_patterns++;
> +
>         len = sizeof(uint64_t);
>         rte_memcpy(vxlan_encap_action_data, &nb_patterns, len);
>         pattern = vxlan_conf->definition;
> --
> 2.18.0
>

[PATCH 5/6] net/cnxk: update processing ready message

[Harman Kalra]

From: Hanumanth Pothula <hpothula@marvell.com>

Now, dpu offload application sends READY measage with only MAC port's
hw_funcs. Hence, process the READY message accordingly.

Signed-off-by: Hanumanth Pothula <hpothula@marvell.com>
---
 drivers/net/cnxk/cnxk_rep_msg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cnxk_rep_msg.c b/drivers/net/cnxk/cnxk_rep_msg.c
index f3a62a805e..53c94fbb0d 100644
--- a/drivers/net/cnxk/cnxk_rep_msg.c
+++ b/drivers/net/cnxk/cnxk_rep_msg.c
@@ -374,7 +374,7 @@ notify_rep_dev_ready(cnxk_rep_msg_ready_data_t *rdata, void *data,
 		goto fail;
 	}
 
-	for (i = 0; i < rdata->nb_ports / 2; i++) {
+	for (i = 0; i < rdata->nb_ports; i++) {
 		rep_id = UINT16_MAX;
 		rc = cnxk_rep_state_update(eswitch_dev, rdata->data[i], &rep_id);
 		if (rc) {
-- 
2.18.0

[PATCH 6/6] common/cnxk: flow aginig delaying app shutdown

[Harman Kalra]

If flow aging is enabled application termination may take time
equivalent to aging timeout. This is because on termination flow
thread uses a sleep call which is uninterruptible.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
 drivers/common/cnxk/roc_npc_aging.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_npc_aging.c b/drivers/common/cnxk/roc_npc_aging.c
index 15f6e61d76..66c953135a 100644
--- a/drivers/common/cnxk/roc_npc_aging.c
+++ b/drivers/common/cnxk/roc_npc_aging.c
@@ -133,6 +133,21 @@ npc_mcam_get_hit_status(struct npc *npc, uint64_t *mcam_ids, uint16_t start_id,
 	return rc;
 }
 
+static void
+npc_age_wait_until(struct roc_npc_flow_age *flow_age)
+{
+#define NPC_AGE_WAIT_TIMEOUT_MS 1000
+#define NPC_AGE_WAIT_TIMEOUT_US (NPC_AGE_WAIT_TIMEOUT_MS * NPC_AGE_WAIT_TIMEOUT_MS)
+	uint64_t timeout = 0;
+	uint64_t sleep = 10 * NPC_AGE_WAIT_TIMEOUT_MS;
+
+	do {
+		plt_delay_us(sleep);
+		timeout += sleep;
+	} while (!flow_age->aged_flows_get_thread_exit &&
+		 (timeout < (flow_age->aging_poll_freq * NPC_AGE_WAIT_TIMEOUT_US)));
+}
+
 uint32_t
 npc_aged_flows_get(void *args)
 {
@@ -197,7 +212,7 @@ npc_aged_flows_get(void *args)
 		plt_seqcount_write_end(&flow_age->seq_cnt);
 
 lbl_sleep:
-		sleep(flow_age->aging_poll_freq);
+	npc_age_wait_until(flow_age);
 	}
 
 	return 0;
-- 
2.18.0

Re: [PATCH 1/6] net/cnxk: stale offload flag reset

[Jerin Jacob]

On Mon, Jun 24, 2024 at 1:19 PM Harman Kalra <hkalra@marvell.com> wrote:
>
> From: Amit Prakash Shukla <amitprakashs@marvell.com>
>
> mbuf buffer is not reset on tx and hence few fields has stale data from
> previous packets. Due to stale offload flags, in one of the scenarios
> with OVS, VxLAN offload flag was set while packet did not have the VxLAN
> header. In the OVS packet path, the flag was read and accordingly VxLAN
> processing was done but as packet did not have VxLAN header it caused
> segfault.
>
> This patch resets mbuf offload flags in rx burst function.


Update the git commit in fix in nature and add Fixes: tag


>
> Signed-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>
> ---
>  drivers/net/cnxk/cnxk_eswitch_rxtx.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/cnxk/cnxk_eswitch_rxtx.c b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
> index d57e32b091..0200392f2d 100644
> --- a/drivers/net/cnxk/cnxk_eswitch_rxtx.c
> +++ b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
> @@ -194,7 +194,7 @@ cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
>                         mbuf->vlan_tci = rx->vtag0_tci;
>                 /* Populate RSS hash */
>                 mbuf->hash.rss = cqe->tag;
> -               mbuf->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
> +               mbuf->ol_flags = RTE_MBUF_F_RX_RSS_HASH;
>                 pkts[pkt] = mbuf;
>                 roc_prefetch_store_keep(mbuf);
>                 plt_esw_dbg("Packet %d rec on queue %d esw qid %d hash %x mbuf %p vlan tci %d",
> --
> 2.18.0
>

[PATCH v2 1/5] net/cnxk: fix stale offload flag reset

[Harman Kalra]

From: Amit Prakash Shukla <amitprakashs@marvell.com>

mbuf buffer is not reset on tx and hence few fields has stale data from
previous packets. Due to stale offload flags, in one of the scenarios
with OVS, VxLAN offload flag was set while packet did not have the VxLAN
header. In the OVS packet path, the flag was read and accordingly VxLAN
processing was done but as packet did not have VxLAN header it caused
segfault.

This patch resets mbuf offload flags in rx burst function.

Fixes: 46ebc0323151 ("net/cnxk: add eswitch Rx/Tx")

Signed-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>
---
V2:
 * Added fixes tag
       
drivers/net/cnxk/cnxk_eswitch_rxtx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cnxk_eswitch_rxtx.c b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
index d57e32b091..0200392f2d 100644
--- a/drivers/net/cnxk/cnxk_eswitch_rxtx.c
+++ b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
@@ -194,7 +194,7 @@ cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			mbuf->vlan_tci = rx->vtag0_tci;
 		/* Populate RSS hash */
 		mbuf->hash.rss = cqe->tag;
-		mbuf->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
+		mbuf->ol_flags = RTE_MBUF_F_RX_RSS_HASH;
 		pkts[pkt] = mbuf;
 		roc_prefetch_store_keep(mbuf);
 		plt_esw_dbg("Packet %d rec on queue %d esw qid %d hash %x mbuf %p vlan tci %d",
-- 
2.18.0

[PATCH v2 2/5] net/cnxk: add MTU set ops

[Harman Kalra]

From: Ankur Dwivedi <adwivedi@marvell.com>

Adding support for changing MTU of a representor port. This is required
to allow processing jumbo packets.
Using this operation, MTU of representor port is only changed, no MTU
change shall be propagated to the respective represented port.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
---
V2:
 * Better commit message
 * Added to release notes

 doc/guides/rel_notes/release_24_07.rst |  2 ++
 drivers/net/cnxk/cnxk_rep.h            |  1 +
 drivers/net/cnxk/cnxk_rep_ops.c        | 34 +++++++++++++++++++++++++-
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst
index 7c88de381b..72ee6a812c 100644
--- a/doc/guides/rel_notes/release_24_07.rst
+++ b/doc/guides/rel_notes/release_24_07.rst
@@ -92,6 +92,8 @@ New Features
   * Added support disabling custom meta aura
     and separately use custom SA action support.
 
+  * Added MTU update for port representors.
+
 * **Updated NVIDIA mlx5 driver.**
 
   * Added match with Tx queue.
diff --git a/drivers/net/cnxk/cnxk_rep.h b/drivers/net/cnxk/cnxk_rep.h
index 9bdea47bd4..ad89649702 100644
--- a/drivers/net/cnxk/cnxk_rep.h
+++ b/drivers/net/cnxk/cnxk_rep.h
@@ -146,5 +146,6 @@ int cnxk_rep_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 			      unsigned int n);
 int cnxk_rep_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 				    struct rte_eth_xstat_name *xstats_names, unsigned int n);
+int cnxk_rep_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
 
 #endif /* __CNXK_REP_H__ */
diff --git a/drivers/net/cnxk/cnxk_rep_ops.c b/drivers/net/cnxk/cnxk_rep_ops.c
index 8bcb689468..888842fa90 100644
--- a/drivers/net/cnxk/cnxk_rep_ops.c
+++ b/drivers/net/cnxk/cnxk_rep_ops.c
@@ -821,6 +821,37 @@ cnxk_rep_xstats_get_names_by_id(__rte_unused struct rte_eth_dev *eth_dev, const
 	return n;
 }
 
+int
+cnxk_rep_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
+{
+	struct cnxk_rep_dev *rep_dev = cnxk_rep_pmd_priv(eth_dev);
+	uint32_t frame_size = mtu + CNXK_NIX_L2_OVERHEAD;
+	int rc = -EINVAL;
+
+	/* Check if MTU is within the allowed range */
+	if ((frame_size - RTE_ETHER_CRC_LEN) < NIX_MIN_HW_FRS) {
+		plt_err("MTU is lesser than minimum");
+		goto exit;
+	}
+
+	if ((frame_size - RTE_ETHER_CRC_LEN) >
+	    ((uint32_t)roc_nix_max_pkt_len(&rep_dev->parent_dev->nix))) {
+		plt_err("MTU is greater than maximum");
+		goto exit;
+	}
+
+	frame_size -= RTE_ETHER_CRC_LEN;
+
+	/* Set frame size on Rx */
+	rc = roc_nix_mac_max_rx_len_set(&rep_dev->parent_dev->nix, frame_size);
+	if (rc) {
+		plt_err("Failed to max Rx frame length, rc=%d", rc);
+		goto exit;
+	}
+exit:
+	return rc;
+}
+
 /* CNXK platform representor dev ops */
 struct eth_dev_ops cnxk_rep_dev_ops = {
 	.dev_infos_get = cnxk_rep_dev_info_get,
@@ -844,5 +875,6 @@ struct eth_dev_ops cnxk_rep_dev_ops = {
 	.xstats_reset = cnxk_rep_xstats_reset,
 	.xstats_get_names = cnxk_rep_xstats_get_names,
 	.xstats_get_by_id = cnxk_rep_xstats_get_by_id,
-	.xstats_get_names_by_id = cnxk_rep_xstats_get_names_by_id
+	.xstats_get_names_by_id = cnxk_rep_xstats_get_names_by_id,
+	.mtu_set = cnxk_rep_mtu_set
 };
-- 
2.18.0

[PATCH v2 3/5] net/cnxk: add multi seg support in eswitch

[Harman Kalra]

From: Ankur Dwivedi <adwivedi@marvell.com>

Introducing multi segment support in eswitch driver to handle
packets of varying sizes which cannot be accommodated to a mbuf.
Instead, the packet data is split across numerous mbufs, each
carrying a portion, or 'segment', of the packet data.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
---
V2:
 * Fixed clang-static compilation issue
 * Added to release notes
 * Better commit message

 doc/guides/rel_notes/release_24_07.rst |   2 +
 drivers/net/cnxk/cnxk_eswitch.c        |   2 +-
 drivers/net/cnxk/cnxk_eswitch_rxtx.c   | 164 ++++++++++++++++++++++---
 3 files changed, 148 insertions(+), 20 deletions(-)

diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst
index 72ee6a812c..16c4222e68 100644
--- a/doc/guides/rel_notes/release_24_07.rst
+++ b/doc/guides/rel_notes/release_24_07.rst
@@ -94,6 +94,8 @@ New Features
 
   * Added MTU update for port representors.
 
+  * Added multi segment support to eswitch device.
+
 * **Updated NVIDIA mlx5 driver.**
 
   * Added match with Tx queue.
diff --git a/drivers/net/cnxk/cnxk_eswitch.c b/drivers/net/cnxk/cnxk_eswitch.c
index f420d01ef8..6b1bfdd476 100644
--- a/drivers/net/cnxk/cnxk_eswitch.c
+++ b/drivers/net/cnxk/cnxk_eswitch.c
@@ -455,7 +455,7 @@ cnxk_eswitch_txq_setup(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid, uint1
 	memset(sq, 0, sizeof(struct roc_nix_sq));
 	sq->qid = qid;
 	sq->nb_desc = nb_desc;
-	sq->max_sqe_sz = NIX_MAXSQESZ_W8;
+	sq->max_sqe_sz = NIX_MAXSQESZ_W16;
 	if (sq->nb_desc >= CNXK_NIX_DEF_SQ_COUNT)
 		sq->fc_hyst_bits = 0x1;
 
diff --git a/drivers/net/cnxk/cnxk_eswitch_rxtx.c b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
index 0200392f2d..6df4ecd762 100644
--- a/drivers/net/cnxk/cnxk_eswitch_rxtx.c
+++ b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
@@ -39,31 +39,102 @@ eswitch_nix_rx_nb_pkts(struct roc_nix_cq *cq, const uint64_t wdata, const uint32
 }
 
 static inline void
-nix_cn9k_xmit_one(uint64_t *cmd, void *lmt_addr, const plt_iova_t io_addr)
+nix_cn9k_xmit_one(uint64_t *cmd, void *lmt_addr, const plt_iova_t io_addr, uint16_t segdw)
 {
 	uint64_t lmt_status;
 
 	do {
-		roc_lmt_mov(lmt_addr, cmd, 0);
+		roc_lmt_mov_seg(lmt_addr, (const void *)cmd, segdw);
 		lmt_status = roc_lmt_submit_ldeor(io_addr);
 	} while (lmt_status == 0);
 }
 
+static __rte_always_inline uint16_t
+cnxk_eswitch_prepare_mseg(struct rte_mbuf *m, union nix_send_sg_s *sg, uint64_t *cmd, uint8_t off)
+{
+	union nix_send_sg_s l_sg;
+	struct rte_mbuf *m_next;
+	uint64_t nb_segs;
+	uint64_t *slist;
+	uint16_t segdw;
+	uint64_t dlen;
+
+	l_sg.u = 0;
+	l_sg.ld_type = NIX_SENDLDTYPE_LDD;
+	l_sg.subdc = NIX_SUBDC_SG;
+
+	dlen = m->data_len;
+	l_sg.u |= dlen;
+	nb_segs = m->nb_segs - 1;
+	m_next = m->next;
+	m->next = NULL;
+	slist = &cmd[off + 1];
+	l_sg.segs = 1;
+	*slist = rte_mbuf_data_iova(m);
+	slist++;
+	m = m_next;
+	if (!m)
+		goto done;
+
+	do {
+		uint64_t iova;
+
+		m_next = m->next;
+		iova = rte_mbuf_data_iova(m);
+		dlen = m->data_len;
+
+		nb_segs--;
+		m->next = NULL;
+
+		*slist = iova;
+		/* Set the segment length */
+		l_sg.u |= ((uint64_t)dlen << (l_sg.segs << 4));
+		l_sg.segs += 1;
+		slist++;
+		if (l_sg.segs > 2 && nb_segs) {
+			sg->u = l_sg.u;
+			/* Next SG subdesc */
+			sg = (union nix_send_sg_s *)slist;
+			l_sg.u = 0;
+			l_sg.ld_type = NIX_SENDLDTYPE_LDD;
+			l_sg.subdc = NIX_SUBDC_SG;
+			slist++;
+		}
+		m = m_next;
+	} while (nb_segs);
+done:
+	/* Write the last subdc out */
+	sg->u = l_sg.u;
+	segdw = (uint64_t *)slist - (uint64_t *)&cmd[off];
+	/* Roundup extra dwords to multiple of 2 */
+	segdw = (segdw >> 1) + (segdw & 0x1);
+	/* Default dwords */
+	segdw += (off >> 1);
+
+	return segdw;
+}
+
 uint16_t
 cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			  struct rte_mbuf **pkts, uint16_t nb_xmit, const uint16_t flags)
 {
 	struct roc_nix_sq *sq = &eswitch_dev->txq[qid].sqs;
 	struct roc_nix_rq *rq = &eswitch_dev->rxq[qid].rqs;
-	uint64_t aura_handle, cmd[6], data = 0;
 	uint16_t lmt_id, pkt = 0, nb_tx = 0;
 	struct nix_send_ext_s *send_hdr_ext;
 	struct nix_send_hdr_s *send_hdr;
+	uint64_t aura_handle, data = 0;
 	uint16_t vlan_tci = qid;
 	union nix_send_sg_s *sg;
 	uintptr_t lmt_base, pa;
 	int64_t fc_pkts, dw_m1;
+	uint64_t cmd_cn9k[16];
+	struct rte_mbuf *m;
 	rte_iova_t io_addr;
+	uint16_t segdw;
+	uint64_t *cmd;
+	uint64_t len;
+	uint8_t off;
 
 	if (unlikely(eswitch_dev->txq[qid].state != CNXK_ESWITCH_QUEUE_STATE_STARTED))
 		return 0;
@@ -78,9 +149,14 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 	/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
 	dw_m1 = cn10k_nix_tx_ext_subs(flags) + 1;
 
-	memset(cmd, 0, sizeof(cmd));
+	if (roc_model_is_cn9k()) {
+		memset(cmd_cn9k, 0, sizeof(cmd_cn9k));
+		cmd = &cmd_cn9k[0];
+	} else {
+		cmd = (uint64_t *)lmt_base;
+	}
+
 	send_hdr = (struct nix_send_hdr_s *)&cmd[0];
-	send_hdr->w0.sizem1 = dw_m1;
 	send_hdr->w0.sq = sq->qid;
 
 	if (dw_m1 >= 2) {
@@ -90,15 +166,15 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			send_hdr_ext->w1.vlan0_ins_ena = true;
 			/* 2B before end of l2 header */
 			send_hdr_ext->w1.vlan0_ins_ptr = 12;
-			send_hdr_ext->w1.vlan0_ins_tci = 0;
+			send_hdr_ext->w1.vlan0_ins_tci = vlan_tci;
 		}
-		sg = (union nix_send_sg_s *)&cmd[4];
+		off = 4;
 	} else {
-		sg = (union nix_send_sg_s *)&cmd[2];
+		off = 2;
 	}
 
+	sg = (union nix_send_sg_s *)&cmd[off];
 	sg->subdc = NIX_SUBDC_SG;
-	sg->segs = 1;
 	sg->ld_type = NIX_SENDLDTYPE_LDD;
 
 	/* Tx */
@@ -110,28 +186,28 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 		nb_tx = PLT_MIN(nb_xmit, (uint64_t)fc_pkts);
 
 	for (pkt = 0; pkt < nb_tx; pkt++) {
-		send_hdr->w0.total = pkts[pkt]->pkt_len;
-		if (pkts[pkt]->pool) {
-			aura_handle = pkts[pkt]->pool->pool_id;
+		m = pkts[pkt];
+		len = m->pkt_len;
+		send_hdr->w0.total = len;
+		if (m->pool) {
+			aura_handle = m->pool->pool_id;
 			send_hdr->w0.aura = roc_npa_aura_handle_to_aura(aura_handle);
 		} else {
 			send_hdr->w0.df = 1;
 		}
-		if (dw_m1 >= 2 && flags & NIX_TX_OFFLOAD_VLAN_QINQ_F)
-			send_hdr_ext->w1.vlan0_ins_tci = vlan_tci;
-		sg->seg1_size = pkts[pkt]->pkt_len;
-		*(plt_iova_t *)(sg + 1) = rte_mbuf_data_iova(pkts[pkt]);
+
+		segdw = cnxk_eswitch_prepare_mseg(m, sg, cmd, off);
+		send_hdr->w0.sizem1 = segdw - 1;
 
 		plt_esw_dbg("Transmitting pkt %d (%p) vlan tci %x on sq %d esw qid %d", pkt,
 			    pkts[pkt], vlan_tci, sq->qid, qid);
 		if (roc_model_is_cn9k()) {
-			nix_cn9k_xmit_one(cmd, sq->lmt_addr, sq->io_addr);
+			nix_cn9k_xmit_one(cmd, sq->lmt_addr, sq->io_addr, segdw);
 		} else {
-			cn10k_nix_xmit_mv_lmt_base(lmt_base, cmd, flags);
 			/* PA<6:4> = LMTST size-1 in units of 128 bits. Size of the first LMTST in
 			 * burst.
 			 */
-			pa = io_addr | (dw_m1 << 4);
+			pa = io_addr | ((segdw - 1) << 4);
 			data &= ~0x7ULL;
 			/*<15:12> = CNTM1: Count minus one of LMTSTs in the burst */
 			data = (0ULL << 12);
@@ -148,6 +224,54 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 	return nb_tx;
 }
 
+static __rte_always_inline void
+cnxk_eswitch_xtract_mseg(struct rte_mbuf *mbuf, const union nix_rx_parse_u *rx)
+{
+	const rte_iova_t *iova_list;
+	uint16_t later_skip = 0;
+	const rte_iova_t *eol;
+	struct rte_mbuf *head;
+	uint8_t nb_segs;
+	uint16_t sg_len;
+	uint64_t sg;
+
+	sg = *(const uint64_t *)(rx + 1);
+	nb_segs = (sg >> 48) & 0x3;
+	if (nb_segs == 1)
+		return;
+
+	mbuf->nb_segs = nb_segs;
+	mbuf->data_len = sg & 0xFFFF;
+	head = mbuf;
+	eol = ((const rte_iova_t *)(rx + 1) + ((rx->desc_sizem1 + 1) << 1));
+	sg = sg >> 16;
+	/* Skip SG_S and first IOVA*/
+	iova_list = ((const rte_iova_t *)(rx + 1)) + 2;
+	nb_segs--;
+	later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf;
+
+	while (nb_segs) {
+		mbuf->next = (struct rte_mbuf *)(*iova_list - later_skip);
+		mbuf = mbuf->next;
+
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
+
+		sg_len = sg & 0XFFFF;
+
+		mbuf->data_len = sg_len;
+		sg = sg >> 16;
+		nb_segs--;
+		iova_list++;
+
+		if (!nb_segs && (iova_list + 1 < eol)) {
+			sg = *(const uint64_t *)(iova_list);
+			nb_segs = (sg >> 48) & 0x3;
+			head->nb_segs += nb_segs;
+			iova_list = (const rte_iova_t *)(iova_list + 1);
+		}
+	}
+}
+
 uint16_t
 cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			  struct rte_mbuf **pkts, uint16_t nb_pkts)
@@ -195,6 +319,8 @@ cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 		/* Populate RSS hash */
 		mbuf->hash.rss = cqe->tag;
 		mbuf->ol_flags = RTE_MBUF_F_RX_RSS_HASH;
+
+		cnxk_eswitch_xtract_mseg(mbuf, rx);
 		pkts[pkt] = mbuf;
 		roc_prefetch_store_keep(mbuf);
 		plt_esw_dbg("Packet %d rec on queue %d esw qid %d hash %x mbuf %p vlan tci %d",
-- 
2.18.0

[PATCH v2 4/5] net/cnxk: fix invalid pattern count

[Harman Kalra]

From: Amit Prakash Shukla <amitprakashs@marvell.com>

Increment nb_pattern count to include RTE_FLOW_ITEM_TYPE_END.

Fixes: aebe8cf310cc ("net/cnxk: create flow on representor ports")

Signed-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>
---
V2:
 * Added fixes tag

 drivers/net/cnxk/cnxk_rep_flow.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_rep_flow.c b/drivers/net/cnxk/cnxk_rep_flow.c
index d26f5aa12c..f1cf81a90c 100644
--- a/drivers/net/cnxk/cnxk_rep_flow.c
+++ b/drivers/net/cnxk/cnxk_rep_flow.c
@@ -171,6 +171,9 @@ populate_vxlan_encap_action_conf(const struct rte_flow_action_vxlan_encap *vxlan
 	for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++)
 		nb_patterns++;
 
+	/* +1 for RTE_FLOW_ITEM_TYPE_END */
+	nb_patterns++;
+
 	len = sizeof(uint64_t);
 	rte_memcpy(vxlan_encap_action_data, &nb_patterns, len);
 	pattern = vxlan_conf->definition;
-- 
2.18.0

[PATCH v2 5/5] net/cnxk: fix representor port mapping

[Harman Kalra]

From: Hanumanth Pothula <hpothula@marvell.com>

As part of ready and exit messages only first half of the ports
were processed, i.e. represented to representor port mapping was
setup and released. While later half of the ports were not
processed.

Fixes: 804c585658ea ("net/cnxk: add representor control plane")

Signed-off-by: Hanumanth Pothula <hpothula@marvell.com>
---
V2:
 * Added fixes tag
 * Better commit message

 drivers/net/cnxk/cnxk_rep_msg.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_rep_msg.c b/drivers/net/cnxk/cnxk_rep_msg.c
index f3a62a805e..29ce94e5c6 100644
--- a/drivers/net/cnxk/cnxk_rep_msg.c
+++ b/drivers/net/cnxk/cnxk_rep_msg.c
@@ -369,12 +369,12 @@ notify_rep_dev_ready(cnxk_rep_msg_ready_data_t *rdata, void *data,
 
 	memset(rep_id_arr, 0, RTE_MAX_ETHPORTS * sizeof(uint64_t));
 	/* For ready state */
-	if ((rdata->nb_ports / 2) > eswitch_dev->repr_cnt.nb_repr_probed) {
+	if (rdata->nb_ports > eswitch_dev->repr_cnt.nb_repr_probed) {
 		rc = CNXK_REP_CTRL_MSG_NACK_INV_REP_CNT;
 		goto fail;
 	}
 
-	for (i = 0; i < rdata->nb_ports / 2; i++) {
+	for (i = 0; i < rdata->nb_ports; i++) {
 		rep_id = UINT16_MAX;
 		rc = cnxk_rep_state_update(eswitch_dev, rdata->data[i], &rep_id);
 		if (rc) {
@@ -475,7 +475,7 @@ notify_rep_dev_exit(cnxk_rep_msg_exit_data_t *edata, void *data)
 		rc = -EINVAL;
 		goto fail;
 	}
-	if ((edata->nb_ports / 2) > eswitch_dev->repr_cnt.nb_repr_probed) {
+	if (edata->nb_ports > eswitch_dev->repr_cnt.nb_repr_probed) {
 		rc = CNXK_REP_CTRL_MSG_NACK_INV_REP_CNT;
 		goto fail;
 	}
-- 
2.18.0

[PATCH v3 1/5] net/cnxk: fix stale offload flag reset

[Harman Kalra]

From: Amit Prakash Shukla <amitprakashs@marvell.com>

mbuf buffer is not reset on tx and hence few fields has stale data from
previous packets. Due to stale offload flags, in one of the scenarios
with OVS, VxLAN offload flag was set while packet did not have the VxLAN
header. In the OVS packet path, the flag was read and accordingly VxLAN
processing was done but as packet did not have VxLAN header it caused
segfault.

This patch resets mbuf offload flags in rx burst function.

Fixes: 46ebc0323151 ("net/cnxk: add eswitch Rx/Tx")

Signed-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>
---
V2:
 * Added fixes tag

drivers/net/cnxk/cnxk_eswitch_rxtx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/cnxk/cnxk_eswitch_rxtx.c b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
index d57e32b091..0200392f2d 100644
--- a/drivers/net/cnxk/cnxk_eswitch_rxtx.c
+++ b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
@@ -194,7 +194,7 @@ cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			mbuf->vlan_tci = rx->vtag0_tci;
 		/* Populate RSS hash */
 		mbuf->hash.rss = cqe->tag;
-		mbuf->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
+		mbuf->ol_flags = RTE_MBUF_F_RX_RSS_HASH;
 		pkts[pkt] = mbuf;
 		roc_prefetch_store_keep(mbuf);
 		plt_esw_dbg("Packet %d rec on queue %d esw qid %d hash %x mbuf %p vlan tci %d",
-- 
2.18.0

[PATCH v3 2/5] net/cnxk: add MTU set ops

[Harman Kalra]

From: Ankur Dwivedi <adwivedi@marvell.com>

Adding support for changing MTU of a representor port. This is required
to allow processing jumbo packets.
Using this operation, MTU of representor port is only changed, no MTU
change shall be propagated to the respective represented port.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
---
V2:
 * Better commit message
 * Added to release notes

V3:
 * Minor correction in release notes

 doc/guides/rel_notes/release_24_07.rst |  2 ++
 drivers/net/cnxk/cnxk_rep.h            |  1 +
 drivers/net/cnxk/cnxk_rep_ops.c        | 34 +++++++++++++++++++++++++-
 3 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst
index 7c88de381b..adf772f488 100644
--- a/doc/guides/rel_notes/release_24_07.rst
+++ b/doc/guides/rel_notes/release_24_07.rst
@@ -92,6 +92,8 @@ New Features
   * Added support disabling custom meta aura
     and separately use custom SA action support.
 
+  * Added MTU update for port representor.
+
 * **Updated NVIDIA mlx5 driver.**
 
   * Added match with Tx queue.
diff --git a/drivers/net/cnxk/cnxk_rep.h b/drivers/net/cnxk/cnxk_rep.h
index 9bdea47bd4..ad89649702 100644
--- a/drivers/net/cnxk/cnxk_rep.h
+++ b/drivers/net/cnxk/cnxk_rep.h
@@ -146,5 +146,6 @@ int cnxk_rep_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 			      unsigned int n);
 int cnxk_rep_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
 				    struct rte_eth_xstat_name *xstats_names, unsigned int n);
+int cnxk_rep_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
 
 #endif /* __CNXK_REP_H__ */
diff --git a/drivers/net/cnxk/cnxk_rep_ops.c b/drivers/net/cnxk/cnxk_rep_ops.c
index 8bcb689468..888842fa90 100644
--- a/drivers/net/cnxk/cnxk_rep_ops.c
+++ b/drivers/net/cnxk/cnxk_rep_ops.c
@@ -821,6 +821,37 @@ cnxk_rep_xstats_get_names_by_id(__rte_unused struct rte_eth_dev *eth_dev, const
 	return n;
 }
 
+int
+cnxk_rep_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
+{
+	struct cnxk_rep_dev *rep_dev = cnxk_rep_pmd_priv(eth_dev);
+	uint32_t frame_size = mtu + CNXK_NIX_L2_OVERHEAD;
+	int rc = -EINVAL;
+
+	/* Check if MTU is within the allowed range */
+	if ((frame_size - RTE_ETHER_CRC_LEN) < NIX_MIN_HW_FRS) {
+		plt_err("MTU is lesser than minimum");
+		goto exit;
+	}
+
+	if ((frame_size - RTE_ETHER_CRC_LEN) >
+	    ((uint32_t)roc_nix_max_pkt_len(&rep_dev->parent_dev->nix))) {
+		plt_err("MTU is greater than maximum");
+		goto exit;
+	}
+
+	frame_size -= RTE_ETHER_CRC_LEN;
+
+	/* Set frame size on Rx */
+	rc = roc_nix_mac_max_rx_len_set(&rep_dev->parent_dev->nix, frame_size);
+	if (rc) {
+		plt_err("Failed to max Rx frame length, rc=%d", rc);
+		goto exit;
+	}
+exit:
+	return rc;
+}
+
 /* CNXK platform representor dev ops */
 struct eth_dev_ops cnxk_rep_dev_ops = {
 	.dev_infos_get = cnxk_rep_dev_info_get,
@@ -844,5 +875,6 @@ struct eth_dev_ops cnxk_rep_dev_ops = {
 	.xstats_reset = cnxk_rep_xstats_reset,
 	.xstats_get_names = cnxk_rep_xstats_get_names,
 	.xstats_get_by_id = cnxk_rep_xstats_get_by_id,
-	.xstats_get_names_by_id = cnxk_rep_xstats_get_names_by_id
+	.xstats_get_names_by_id = cnxk_rep_xstats_get_names_by_id,
+	.mtu_set = cnxk_rep_mtu_set
 };
-- 
2.18.0

[PATCH v3 3/5] net/cnxk: add multi seg support in eswitch

[Harman Kalra]

From: Ankur Dwivedi <adwivedi@marvell.com>

Introducing multi segment support in eswitch driver to handle
packets of varying sizes which cannot be accommodated to a mbuf.
Instead, the packet data is split across numerous mbufs, each
carrying a portion, or 'segment', of the packet data.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
---
V2:
 * Fixed clang-static compilation issue
 * Added to release notes
 * Better commit message

V3:
 * Minor correction in release notes

 doc/guides/rel_notes/release_24_07.rst |   2 +
 drivers/net/cnxk/cnxk_eswitch.c        |   2 +-
 drivers/net/cnxk/cnxk_eswitch_rxtx.c   | 164 ++++++++++++++++++++++---
 3 files changed, 148 insertions(+), 20 deletions(-)

diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst
index adf772f488..48c6d8fa64 100644
--- a/doc/guides/rel_notes/release_24_07.rst
+++ b/doc/guides/rel_notes/release_24_07.rst
@@ -94,6 +94,8 @@ New Features
 
   * Added MTU update for port representor.
 
+  * Added multi segment support for port representor.
+
 * **Updated NVIDIA mlx5 driver.**
 
   * Added match with Tx queue.
diff --git a/drivers/net/cnxk/cnxk_eswitch.c b/drivers/net/cnxk/cnxk_eswitch.c
index f420d01ef8..6b1bfdd476 100644
--- a/drivers/net/cnxk/cnxk_eswitch.c
+++ b/drivers/net/cnxk/cnxk_eswitch.c
@@ -455,7 +455,7 @@ cnxk_eswitch_txq_setup(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid, uint1
 	memset(sq, 0, sizeof(struct roc_nix_sq));
 	sq->qid = qid;
 	sq->nb_desc = nb_desc;
-	sq->max_sqe_sz = NIX_MAXSQESZ_W8;
+	sq->max_sqe_sz = NIX_MAXSQESZ_W16;
 	if (sq->nb_desc >= CNXK_NIX_DEF_SQ_COUNT)
 		sq->fc_hyst_bits = 0x1;
 
diff --git a/drivers/net/cnxk/cnxk_eswitch_rxtx.c b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
index 0200392f2d..6df4ecd762 100644
--- a/drivers/net/cnxk/cnxk_eswitch_rxtx.c
+++ b/drivers/net/cnxk/cnxk_eswitch_rxtx.c
@@ -39,31 +39,102 @@ eswitch_nix_rx_nb_pkts(struct roc_nix_cq *cq, const uint64_t wdata, const uint32
 }
 
 static inline void
-nix_cn9k_xmit_one(uint64_t *cmd, void *lmt_addr, const plt_iova_t io_addr)
+nix_cn9k_xmit_one(uint64_t *cmd, void *lmt_addr, const plt_iova_t io_addr, uint16_t segdw)
 {
 	uint64_t lmt_status;
 
 	do {
-		roc_lmt_mov(lmt_addr, cmd, 0);
+		roc_lmt_mov_seg(lmt_addr, (const void *)cmd, segdw);
 		lmt_status = roc_lmt_submit_ldeor(io_addr);
 	} while (lmt_status == 0);
 }
 
+static __rte_always_inline uint16_t
+cnxk_eswitch_prepare_mseg(struct rte_mbuf *m, union nix_send_sg_s *sg, uint64_t *cmd, uint8_t off)
+{
+	union nix_send_sg_s l_sg;
+	struct rte_mbuf *m_next;
+	uint64_t nb_segs;
+	uint64_t *slist;
+	uint16_t segdw;
+	uint64_t dlen;
+
+	l_sg.u = 0;
+	l_sg.ld_type = NIX_SENDLDTYPE_LDD;
+	l_sg.subdc = NIX_SUBDC_SG;
+
+	dlen = m->data_len;
+	l_sg.u |= dlen;
+	nb_segs = m->nb_segs - 1;
+	m_next = m->next;
+	m->next = NULL;
+	slist = &cmd[off + 1];
+	l_sg.segs = 1;
+	*slist = rte_mbuf_data_iova(m);
+	slist++;
+	m = m_next;
+	if (!m)
+		goto done;
+
+	do {
+		uint64_t iova;
+
+		m_next = m->next;
+		iova = rte_mbuf_data_iova(m);
+		dlen = m->data_len;
+
+		nb_segs--;
+		m->next = NULL;
+
+		*slist = iova;
+		/* Set the segment length */
+		l_sg.u |= ((uint64_t)dlen << (l_sg.segs << 4));
+		l_sg.segs += 1;
+		slist++;
+		if (l_sg.segs > 2 && nb_segs) {
+			sg->u = l_sg.u;
+			/* Next SG subdesc */
+			sg = (union nix_send_sg_s *)slist;
+			l_sg.u = 0;
+			l_sg.ld_type = NIX_SENDLDTYPE_LDD;
+			l_sg.subdc = NIX_SUBDC_SG;
+			slist++;
+		}
+		m = m_next;
+	} while (nb_segs);
+done:
+	/* Write the last subdc out */
+	sg->u = l_sg.u;
+	segdw = (uint64_t *)slist - (uint64_t *)&cmd[off];
+	/* Roundup extra dwords to multiple of 2 */
+	segdw = (segdw >> 1) + (segdw & 0x1);
+	/* Default dwords */
+	segdw += (off >> 1);
+
+	return segdw;
+}
+
 uint16_t
 cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			  struct rte_mbuf **pkts, uint16_t nb_xmit, const uint16_t flags)
 {
 	struct roc_nix_sq *sq = &eswitch_dev->txq[qid].sqs;
 	struct roc_nix_rq *rq = &eswitch_dev->rxq[qid].rqs;
-	uint64_t aura_handle, cmd[6], data = 0;
 	uint16_t lmt_id, pkt = 0, nb_tx = 0;
 	struct nix_send_ext_s *send_hdr_ext;
 	struct nix_send_hdr_s *send_hdr;
+	uint64_t aura_handle, data = 0;
 	uint16_t vlan_tci = qid;
 	union nix_send_sg_s *sg;
 	uintptr_t lmt_base, pa;
 	int64_t fc_pkts, dw_m1;
+	uint64_t cmd_cn9k[16];
+	struct rte_mbuf *m;
 	rte_iova_t io_addr;
+	uint16_t segdw;
+	uint64_t *cmd;
+	uint64_t len;
+	uint8_t off;
 
 	if (unlikely(eswitch_dev->txq[qid].state != CNXK_ESWITCH_QUEUE_STATE_STARTED))
 		return 0;
@@ -78,9 +149,14 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 	/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
 	dw_m1 = cn10k_nix_tx_ext_subs(flags) + 1;
 
-	memset(cmd, 0, sizeof(cmd));
+	if (roc_model_is_cn9k()) {
+		memset(cmd_cn9k, 0, sizeof(cmd_cn9k));
+		cmd = &cmd_cn9k[0];
+	} else {
+		cmd = (uint64_t *)lmt_base;
+	}
+
 	send_hdr = (struct nix_send_hdr_s *)&cmd[0];
-	send_hdr->w0.sizem1 = dw_m1;
 	send_hdr->w0.sq = sq->qid;
 
 	if (dw_m1 >= 2) {
@@ -90,15 +166,15 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			send_hdr_ext->w1.vlan0_ins_ena = true;
 			/* 2B before end of l2 header */
 			send_hdr_ext->w1.vlan0_ins_ptr = 12;
-			send_hdr_ext->w1.vlan0_ins_tci = 0;
+			send_hdr_ext->w1.vlan0_ins_tci = vlan_tci;
 		}
-		sg = (union nix_send_sg_s *)&cmd[4];
+		off = 4;
 	} else {
-		sg = (union nix_send_sg_s *)&cmd[2];
+		off = 2;
 	}
 
+	sg = (union nix_send_sg_s *)&cmd[off];
 	sg->subdc = NIX_SUBDC_SG;
-	sg->segs = 1;
 	sg->ld_type = NIX_SENDLDTYPE_LDD;
 
 	/* Tx */
@@ -110,28 +186,28 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 		nb_tx = PLT_MIN(nb_xmit, (uint64_t)fc_pkts);
 
 	for (pkt = 0; pkt < nb_tx; pkt++) {
-		send_hdr->w0.total = pkts[pkt]->pkt_len;
-		if (pkts[pkt]->pool) {
-			aura_handle = pkts[pkt]->pool->pool_id;
+		m = pkts[pkt];
+		len = m->pkt_len;
+		send_hdr->w0.total = len;
+		if (m->pool) {
+			aura_handle = m->pool->pool_id;
 			send_hdr->w0.aura = roc_npa_aura_handle_to_aura(aura_handle);
 		} else {
 			send_hdr->w0.df = 1;
 		}
-		if (dw_m1 >= 2 && flags & NIX_TX_OFFLOAD_VLAN_QINQ_F)
-			send_hdr_ext->w1.vlan0_ins_tci = vlan_tci;
-		sg->seg1_size = pkts[pkt]->pkt_len;
-		*(plt_iova_t *)(sg + 1) = rte_mbuf_data_iova(pkts[pkt]);
+
+		segdw = cnxk_eswitch_prepare_mseg(m, sg, cmd, off);
+		send_hdr->w0.sizem1 = segdw - 1;
 
 		plt_esw_dbg("Transmitting pkt %d (%p) vlan tci %x on sq %d esw qid %d", pkt,
 			    pkts[pkt], vlan_tci, sq->qid, qid);
 		if (roc_model_is_cn9k()) {
-			nix_cn9k_xmit_one(cmd, sq->lmt_addr, sq->io_addr);
+			nix_cn9k_xmit_one(cmd, sq->lmt_addr, sq->io_addr, segdw);
 		} else {
-			cn10k_nix_xmit_mv_lmt_base(lmt_base, cmd, flags);
 			/* PA<6:4> = LMTST size-1 in units of 128 bits. Size of the first LMTST in
 			 * burst.
 			 */
-			pa = io_addr | (dw_m1 << 4);
+			pa = io_addr | ((segdw - 1) << 4);
 			data &= ~0x7ULL;
 			/*<15:12> = CNTM1: Count minus one of LMTSTs in the burst */
 			data = (0ULL << 12);
@@ -148,6 +224,54 @@ cnxk_eswitch_dev_tx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 	return nb_tx;
 }
 
+static __rte_always_inline void
+cnxk_eswitch_xtract_mseg(struct rte_mbuf *mbuf, const union nix_rx_parse_u *rx)
+{
+	const rte_iova_t *iova_list;
+	uint16_t later_skip = 0;
+	const rte_iova_t *eol;
+	struct rte_mbuf *head;
+	uint8_t nb_segs;
+	uint16_t sg_len;
+	uint64_t sg;
+
+	sg = *(const uint64_t *)(rx + 1);
+	nb_segs = (sg >> 48) & 0x3;
+	if (nb_segs == 1)
+		return;
+
+	mbuf->nb_segs = nb_segs;
+	mbuf->data_len = sg & 0xFFFF;
+	head = mbuf;
+	eol = ((const rte_iova_t *)(rx + 1) + ((rx->desc_sizem1 + 1) << 1));
+	sg = sg >> 16;
+	/* Skip SG_S and first IOVA*/
+	iova_list = ((const rte_iova_t *)(rx + 1)) + 2;
+	nb_segs--;
+	later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf;
+
+	while (nb_segs) {
+		mbuf->next = (struct rte_mbuf *)(*iova_list - later_skip);
+		mbuf = mbuf->next;
+
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
+
+		sg_len = sg & 0XFFFF;
+
+		mbuf->data_len = sg_len;
+		sg = sg >> 16;
+		nb_segs--;
+		iova_list++;
+
+		if (!nb_segs && (iova_list + 1 < eol)) {
+			sg = *(const uint64_t *)(iova_list);
+			nb_segs = (sg >> 48) & 0x3;
+			head->nb_segs += nb_segs;
+			iova_list = (const rte_iova_t *)(iova_list + 1);
+		}
+	}
+}
+
 uint16_t
 cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 			  struct rte_mbuf **pkts, uint16_t nb_pkts)
@@ -195,6 +319,8 @@ cnxk_eswitch_dev_rx_burst(struct cnxk_eswitch_dev *eswitch_dev, uint16_t qid,
 		/* Populate RSS hash */
 		mbuf->hash.rss = cqe->tag;
 		mbuf->ol_flags = RTE_MBUF_F_RX_RSS_HASH;
+
+		cnxk_eswitch_xtract_mseg(mbuf, rx);
 		pkts[pkt] = mbuf;
 		roc_prefetch_store_keep(mbuf);
 		plt_esw_dbg("Packet %d rec on queue %d esw qid %d hash %x mbuf %p vlan tci %d",
-- 
2.18.0

[PATCH v3 4/5] net/cnxk: fix invalid pattern count

[Harman Kalra]

From: Amit Prakash Shukla <amitprakashs@marvell.com>

Increment nb_pattern count to include RTE_FLOW_ITEM_TYPE_END.

Fixes: aebe8cf310cc ("net/cnxk: create flow on representor ports")

Signed-off-by: Amit Prakash Shukla <amitprakashs@marvell.com>
---
V2:
 * Added fixes tag

 drivers/net/cnxk/cnxk_rep_flow.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_rep_flow.c b/drivers/net/cnxk/cnxk_rep_flow.c
index d26f5aa12c..f1cf81a90c 100644
--- a/drivers/net/cnxk/cnxk_rep_flow.c
+++ b/drivers/net/cnxk/cnxk_rep_flow.c
@@ -171,6 +171,9 @@ populate_vxlan_encap_action_conf(const struct rte_flow_action_vxlan_encap *vxlan
 	for (; pattern->type != RTE_FLOW_ITEM_TYPE_END; pattern++)
 		nb_patterns++;
 
+	/* +1 for RTE_FLOW_ITEM_TYPE_END */
+	nb_patterns++;
+
 	len = sizeof(uint64_t);
 	rte_memcpy(vxlan_encap_action_data, &nb_patterns, len);
 	pattern = vxlan_conf->definition;
-- 
2.18.0

[PATCH v3 5/5] net/cnxk: fix representor port mapping

[Harman Kalra]

From: Hanumanth Pothula <hpothula@marvell.com>

As part of ready and exit messages only first half of the ports
were processed, i.e. represented to representor port mapping was
setup and released. While later half of the ports were not
processed.

Fixes: 804c585658ea ("net/cnxk: add representor control plane")

Signed-off-by: Hanumanth Pothula <hpothula@marvell.com>
---
V2:
 * Added fixes tag
 * Better commit message

 drivers/net/cnxk/cnxk_rep_msg.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_rep_msg.c b/drivers/net/cnxk/cnxk_rep_msg.c
index f3a62a805e..29ce94e5c6 100644
--- a/drivers/net/cnxk/cnxk_rep_msg.c
+++ b/drivers/net/cnxk/cnxk_rep_msg.c
@@ -369,12 +369,12 @@ notify_rep_dev_ready(cnxk_rep_msg_ready_data_t *rdata, void *data,
 
 	memset(rep_id_arr, 0, RTE_MAX_ETHPORTS * sizeof(uint64_t));
 	/* For ready state */
-	if ((rdata->nb_ports / 2) > eswitch_dev->repr_cnt.nb_repr_probed) {
+	if (rdata->nb_ports > eswitch_dev->repr_cnt.nb_repr_probed) {
 		rc = CNXK_REP_CTRL_MSG_NACK_INV_REP_CNT;
 		goto fail;
 	}
 
-	for (i = 0; i < rdata->nb_ports / 2; i++) {
+	for (i = 0; i < rdata->nb_ports; i++) {
 		rep_id = UINT16_MAX;
 		rc = cnxk_rep_state_update(eswitch_dev, rdata->data[i], &rep_id);
 		if (rc) {
@@ -475,7 +475,7 @@ notify_rep_dev_exit(cnxk_rep_msg_exit_data_t *edata, void *data)
 		rc = -EINVAL;
 		goto fail;
 	}
-	if ((edata->nb_ports / 2) > eswitch_dev->repr_cnt.nb_repr_probed) {
+	if (edata->nb_ports > eswitch_dev->repr_cnt.nb_repr_probed) {
 		rc = CNXK_REP_CTRL_MSG_NACK_INV_REP_CNT;
 		goto fail;
 	}
-- 
2.18.0

Re: [PATCH v3 5/5] net/cnxk: fix representor port mapping

[Jerin Jacob]

On Mon, Jun 24, 2024 at 6:54 PM Harman Kalra <hkalra@marvell.com> wrote:
>
> From: Hanumanth Pothula <hpothula@marvell.com>
>
> As part of ready and exit messages only first half of the ports
> were processed, i.e. represented to representor port mapping was
> setup and released. While later half of the ports were not
> processed.
>
> Fixes: 804c585658ea ("net/cnxk: add representor control plane")
>
> Signed-off-by: Hanumanth Pothula <hpothula@marvell.com>

Series applied to dpdk-next-net-mrvl/for-main. Thanks