From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 23EF4A0350; Fri, 26 Jun 2020 06:53:52 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1E3141B3BB; Fri, 26 Jun 2020 06:53:51 +0200 (CEST) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by dpdk.org (Postfix) with ESMTP id 2B4CE25B3 for ; Fri, 26 Jun 2020 06:53:50 +0200 (CEST) Received: by mail-io1-f67.google.com with SMTP id e64so3563637iof.12 for ; Thu, 25 Jun 2020 21:53:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=gQOyQb4KgnebXwtpAGko10wzSNoBHplBaJQNElg+/cI=; b=VFfKKNxKiy5FlnrseupBF106e7mx0yg2tu8SFpZQYua6U211Mvrq45Q34ebJFq8/pv UXYi8LaSBiYxsyilKZTzLWVwBuOzAh48Ngbks5G5Ffh4kgg8CDhxELrq3a+sNjxfm90V 2Klcgel3SXLVSjIdvrA14eYmX5MJAsL9mIw1LhZo6OTspsbuArdHvLDql9wFQmj8+gnZ eIPqpdjO5xsH7aPqgP/TGiRjw+TTI00Qg9/AODT5eSxmT2eCgjTfMUC9ZmtmtblLyXWW XMdxlVnUgpgax5iZm8l63sqTJoRZXy0VnYUrNOwjbuohkfO2cxsk7U2RSZh0vCQOo90a esNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=gQOyQb4KgnebXwtpAGko10wzSNoBHplBaJQNElg+/cI=; b=UMp1HzkkszGnjRoB+XKJa6lrAobcBFJk27xU0n+fXOIoGfG5CP8fBdSw2GTsQ2Lo7y VuoaIXnu8OPnk8Y6zE8bymvPtMI+U56tuWtKtSMHGQkQT4MCMroXI0gpQH0ytMcET0Ar ab7ej+hvJMVa0PTmjcAQzURMS9h4zsWYuhCLIGGEmao7/G3pQMCAGZT4EbTC0ttoIySz aQUXzkGCsvoh+koBneAN0oLxIw+GGwPss2sOdvMcAR/Ad7EQtCexpNd72WipD9oDWktJ cu54pX5p57D5yB+d15owSADd4BLu0ip6z+k2VNuOkGD4X3r0B/UnJcZ9lel4JqH7l2Hn IzGA== X-Gm-Message-State: AOAM533bdol1Y1xfK6hISWSzfyd/4G9yTANJE9CDQZMvy2Stx2uNoaoE fXGmP689MuGV8AV+m/A1dFZweRvwQ1nlvyZx8lM= X-Google-Smtp-Source: ABdhPJwdZ+6m4d3OhO97R82qtoEWedvMY89isfUe+fLm1i4J6BHit1D/95VDRZWMmJWSrYJ4SZNymYJ2aDFygtrJaaY= X-Received: by 2002:a05:6602:21c7:: with SMTP id c7mr1598249ioc.1.1593147229392; Thu, 25 Jun 2020 21:53:49 -0700 (PDT) MIME-Version: 1.0 References: <20200609194207.24328-1-manishc@marvell.com> <20200609194207.24328-2-manishc@marvell.com> In-Reply-To: <20200609194207.24328-2-manishc@marvell.com> From: Jerin Jacob Date: Fri, 26 Jun 2020 10:23:33 +0530 Message-ID: To: Manish Chopra , Gaetan Rivet Cc: Jerin Jacob , Ferruh Yigit , dpdk-dev , Igor Russkikh , Rasesh Mody , GR-Everest-DPDK-Dev Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH 1/6] net/qede: define PCI config space specific osals X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Jun 10, 2020 at 1:13 AM Manish Chopra wrote: > > This patch defines various PCI config space access APIs > in order to read and find IOV specific PCI capabilities. > > With these definitions implemented, it enables the base > driver to do SR-IOV specific initialization and HW specific > configuration required from PF-PMD driver instance. > > Signed-off-by: Manish Chopra > Signed-off-by: Igor Russkikh > Signed-off-by: Rasesh Mody > --- > + > +int osal_pci_find_next_ext_capability(struct rte_pci_device *dev, > + int cap) + Gaetan (PCI maintainer) Manish, It must be a candidate for a generic PCI API as it is nothing to do with qede. Please move to common PCI code if such API is not already present. > +{ > + int pos = PCI_CFG_SPACE_SIZE; > + uint32_t header; > + int ttl; > + > + /* minimum 8 bytes per capability */ > + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; > + > + if (rte_pci_read_config(dev, &header, 4, pos) < 0) > + return -1; > + > + /* > + * If we have no capabilities, this is indicated by cap ID, > + * cap version and next pointer all being 0. > + */ > + if (header == 0) > + return 0; > + > + while (ttl-- > 0) { > + if (PCI_EXT_CAP_ID(header) == cap) > + return pos; > + > + pos = PCI_EXT_CAP_NEXT(header); > + > + if (pos < PCI_CFG_SPACE_SIZE) > + break; > + > + if (rte_pci_read_config(dev, &header, 4, pos) < 0) > + return -1; > + } > + > + return 0; > +} > > > +#define PCICFG_VENDOR_ID_OFFSET 0x00 > +#define PCICFG_DEVICE_ID_OFFSET 0x02 > +#define PCI_CFG_SPACE_SIZE 256 > +#define PCI_EXP_DEVCTL 0x0008 > +#define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff) > +#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc) > +#define PCI_CFG_SPACE_EXP_SIZE 4096 > + > +#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ > +#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ > +#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ > +#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ > +#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ > +#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ > +#define PCI_SRIOV_VF_DID 0x1a > +#define PCI_SRIOV_SUP_PGSIZE 0x1c > +#define PCI_SRIOV_CAP 0x04 > +#define PCI_SRIOV_FUNC_LINK 0x12 > +#define PCI_EXT_CAP_ID_SRIOV 0x10 Dont DEFINE PCI_ symbols in drivers, It may conflict with other PCI definitions in the future. Please move GENERIC PCI_ symbols to the generic PCI layer. > +