From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC38EA04C0; Tue, 29 Sep 2020 10:04:09 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C3B011D703; Tue, 29 Sep 2020 10:04:08 +0200 (CEST) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by dpdk.org (Postfix) with ESMTP id 1F8281D5C9 for ; Tue, 29 Sep 2020 10:04:06 +0200 (CEST) Received: by mail-io1-f67.google.com with SMTP id j2so3865675ioj.7 for ; Tue, 29 Sep 2020 01:04:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wEgNmZlGM1tFZrvJ8l2sqd7o3wtwIThxE4HNKNcYXqw=; b=DTgfzQjWQTfWZ3isfV910NWj7jnlRWcmebtdaLUj7xbXRa53uiXiv4YRVYPqp9vND5 w8CMd5/xyynqhEoASwLP96PhQJ9LVHcXujoe3UMFxeXiCyLQjAO/0MYBs9nBFTOyz1v7 hCxL0C0caTQe6l1F9Yc5yZBp6XCeOoAp+wujDy1lGTtaj9vYQ7vJYeWWzqDOH+CklxII sWYKISE6IBv5+fhDOTi9fp0K9VafD2zDp1Y7khdYtvhwvPK8njHILMRB6g7ueHn1A5dY a0JnTmUwdSOWaFSiJZgFqN8o8+7GnGwxKz6VSrleBKcqKgnFITtUcJs3KugB/0qfjjCe FSMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wEgNmZlGM1tFZrvJ8l2sqd7o3wtwIThxE4HNKNcYXqw=; b=H9jtDlAZrH5lGgprA0YfqHUcmteREWg8Zq9syxARwGQg8oNFT8QVgvVzlpriY7W+UT vsJ9jIrPpYr9FbcuEfelUoCmXoLmX60pgEvi7oQzCFhILmQw3YG8oU2d+mMJoVReD6eE nrkQtSY/dYHm3ISu4m8iOGuWRrR8lxHy7cKJuu1UdYl8Ju0Nnrgcar98sOjBMDnVloau SJZqclGb3Iba1DsiCUfpe6s1a5d0hE5AHP12SxHtlE1l8uiMHag55lknCxP/m4wE7HAd 7+aU2OH48Xq8S+PcTT6mM1zFaJHvW2CgNdrlMaDKuuCQKOjxCJmpSE1CKixV0DxanQZg prqg== X-Gm-Message-State: AOAM531S0cabP7J9eX/Kd+ODOrhoWoDuxV/u6bnb0XZsuMIQZIZkM3D1 DorKFfZldwobNyD1ASZ0HyOTSsTLxgaxFTSq315NFmXoh85+6w== X-Google-Smtp-Source: ABdhPJzRShXZysUOFgJHvf3c2DA1mrAniCrHdpf8ts0L7MlwvZSbCO9uzA9hU5Q5ywdSUcBz3S8Prs/DJKFaeS73Zns= X-Received: by 2002:a05:6602:2a45:: with SMTP id k5mr1605186iov.1.1601366644420; Tue, 29 Sep 2020 01:04:04 -0700 (PDT) MIME-Version: 1.0 References: <20200821065930.191028-1-kirankumark@marvell.com> In-Reply-To: <20200821065930.191028-1-kirankumark@marvell.com> From: Jerin Jacob Date: Tue, 29 Sep 2020 13:33:48 +0530 Message-ID: To: Kiran Kumar K Cc: Jerin Jacob , Nithin Dabilpuram , dpdk-dev Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH] net/octeontx2: set max vtag insertion size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Aug 21, 2020 at 12:29 PM wrote: > > From: Kiran Kumar K > > When TX side VTAG insertion is enabled, As we are not setting the max > vtag insertion size an interrupt has been received. This patch will fix > the issue by configuring the max vtag insertion size to 8B. > > Signed-off-by: Kiran Kumar K Updated git comment to provide more detail while applying: `` net/octeontx2: set max vtag insertion size When TX side VTAG insertion is enabled, SMQ should be configured with the maximum VTAG insertion size to avoid generating NIX_SQINT_SEND_ERR interrupt. Since the default value is zero, This patch configures the VTAG insertion size to the max supported value. Signed-off-by: Kiran Kumar K Acked-by: Jerin Jacob `` Applied to dpdk-next-net-mrvl/main. Thanks > --- > drivers/net/octeontx2/otx2_tm.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c > index 8ed059549..b76242a60 100644 > --- a/drivers/net/octeontx2/otx2_tm.c > +++ b/drivers/net/octeontx2/otx2_tm.c > @@ -560,8 +560,9 @@ populate_tm_reg(struct otx2_eth_dev *dev, > * smaller > */ > reg[k] = NIX_AF_SMQX_CFG(schq); > - regval[k] = BIT_ULL(50) | NIX_MIN_HW_FRS; > - regval_mask[k] = ~(BIT_ULL(50) | 0x7f); > + regval[k] = BIT_ULL(50) | ((uint64_t)NIX_MAX_VTAG_INS << 36) | > + NIX_MIN_HW_FRS; > + regval_mask[k] = ~(BIT_ULL(50) | (0x7ULL << 36) | 0x7f); > k++; > > /* Parent and schedule conf */ > -- > 2.25.1 >