From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 37C80440B6; Fri, 24 May 2024 15:17:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B6E02402C7; Fri, 24 May 2024 15:17:21 +0200 (CEST) Received: from mail-qt1-f177.google.com (mail-qt1-f177.google.com [209.85.160.177]) by mails.dpdk.org (Postfix) with ESMTP id 6FFCB40271 for ; Fri, 24 May 2024 15:17:20 +0200 (CEST) Received: by mail-qt1-f177.google.com with SMTP id d75a77b69052e-43fb155fc69so3836081cf.2 for ; Fri, 24 May 2024 06:17:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716556639; x=1717161439; darn=dpdk.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=6A5puog8Hd0tu9R6j+Tjl0hDIKiFTC9tGJxgrzL8IwI=; b=Sz9bCvyDmDzz7qck8wT6qRx/s4BfAlfQihEHD1n4gKvRE6GQF3ns9XawT733u4C1bK z8i0e8wJ9vITRHYbtKDnj+X04jAfr5kPOlWXrGDOemcldz8xHw6/Vy1nVW6847qreDwS U2v2Th2IOT2FKCs52AE4nZFPEKrtE2+wrxngFkIpNyCWZ/tyzLldvgJywjSG3EO8K70y r9Fbc9XD3UEfG3rfqMQJsCEHV7wvwzUwL60MPvXZuGKcngo9R/Q7+69bmMJ8Inbnydtx JIuk/dxoLKmplhyCKahpnbGo5jzjLkEejng9Ppq+hczEvVqWl3zDn0iHiOlYI/RvJTdU 3QAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716556639; x=1717161439; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6A5puog8Hd0tu9R6j+Tjl0hDIKiFTC9tGJxgrzL8IwI=; b=gWCtwVC4gzM8GXeSpJdv9EELE+X1xm38XN7PE0N22Z0/vrIqY8baR9IeAXdhNi8uCe 6wVl3j2I32o0tdgKF+vlw1crk1U3Gd73XBqLQydJ1fjGpctSbT01Ly23+QfpmX/FvRKd VQh+mKVRFMouEvPTtVsoBh5E8WevyOnZitI+oFTP/8k+EV4PC3jWTw07Q/uXcex5dVy8 b2KTsYB9llhn3kCKe5DguEXnVYJfjSrCMgg6gPxRg6KzK1x44L8+yNuxwgtFDVy9TZAB eEl5eIKr4rrrXqALDHW8KEUSTk9brmUZDT/AQ4XpVqPYaPxq1ez8o8v5pCQ/qz3+RZ7w vhDQ== X-Forwarded-Encrypted: i=1; AJvYcCVssNiDZxaSDjrxQQCDjHrFqsUxJVU/DqX7BHkSqJmSBUYVplKdpb5PtSfbSfb8fgvmyduxFtiWR4Z/Rzc= X-Gm-Message-State: AOJu0YxCBReOTLJekqavEICbRbvs9jQKHE8qzQvKOTAeri/OZrQ+umqV Vi+c8CZ3kXHGwtv8FSg7o2deC3wUbDechJDoa2oos1ZUG9qfYcbdnnZhSZe7AAfc4itP3UiryEw m57CyCSMkzUNLfG/OX9MOTlTf+y4= X-Google-Smtp-Source: AGHT+IE8M0awWu+qXXKKl4XfAXpZR+nUK09WbKehgAcWf/pcptQnppYqWR2yrAbru8cRpdPw9GpNHGAmQNGa9iIPyWs= X-Received: by 2002:a05:622a:180b:b0:43a:f697:6670 with SMTP id d75a77b69052e-43fb0ef7462mr19177571cf.49.1716556639452; Fri, 24 May 2024 06:17:19 -0700 (PDT) MIME-Version: 1.0 References: <20240522144520.1907-1-pbhagavatula@marvell.com> In-Reply-To: <20240522144520.1907-1-pbhagavatula@marvell.com> From: Jerin Jacob Date: Fri, 24 May 2024 18:46:51 +0530 Message-ID: Subject: Re: [PATCH] dma/cnxk: add higher chunk size support To: pbhagavatula@marvell.com Cc: jerinj@marvell.com, Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Harman Kalra , Vamsi Attunuru , dev@dpdk.org, Amit Prakash Shukla Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Wed, May 22, 2024 at 8:15=E2=80=AFPM wrote: > > From: Pavan Nikhilesh > > Add support to configure higher chunk size by using the new > OPEN_V2 mailbox, this improves performance as the number of > mempool allocs are reduced. > > Signed-off-by: Pavan Nikhilesh > Signed-off-by: Amit Prakash Shukla > --- > drivers/common/cnxk/roc_dpi.c | 39 ++++++++++++++++++++++++++++++ > drivers/common/cnxk/roc_dpi.h | 2 ++ > drivers/common/cnxk/roc_dpi_priv.h | 1 + > drivers/common/cnxk/version.map | 1 + > drivers/dma/cnxk/cnxk_dmadev.c | 31 ++++++++++++++++-------- > drivers/dma/cnxk/cnxk_dmadev.h | 1 + New feature spotted, please update release note for PMD specific API. > 6 files changed, 65 insertions(+), 10 deletions(-) > + > +int > +roc_dpi_configure_v2(struct roc_dpi *roc_dpi, uint32_t chunk_sz, uint64_= t aura, uint64_t chunk_base) > +{ > + struct plt_pci_device *pci_dev; > + dpi_mbox_msg_t mbox_msg; > + uint64_t reg; > + int rc; > + > + if (!roc_dpi) { > + plt_err("roc_dpi is NULL"); > + return -EINVAL; > + } > + > + pci_dev =3D roc_dpi->pci_dev; > + > + roc_dpi_disable(roc_dpi); > + reg =3D plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR); > + while (!(reg & BIT_ULL(63))) > + reg =3D plt_read64(roc_dpi->rbase + DPI_VDMA_SADDR); Is timeout needed?