From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 80228A00C4; Sun, 1 May 2022 15:45:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2AB4D4069D; Sun, 1 May 2022 15:45:30 +0200 (CEST) Received: from mail-io1-f43.google.com (mail-io1-f43.google.com [209.85.166.43]) by mails.dpdk.org (Postfix) with ESMTP id D4D7B4003F for ; Sun, 1 May 2022 15:45:28 +0200 (CEST) Received: by mail-io1-f43.google.com with SMTP id g21so13913624iom.13 for ; Sun, 01 May 2022 06:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=3vPZxMHFHw4oXV4dtRDnDSwBE8znhR5BZiir2CAW8Qw=; b=Ty9yFXXAYdgJXZQCfMyQBNM1+LWuaVSfwkuFjmHrx+20x4iaJY1dQepMsNEBpKYCBe kOtYvVtYNZFqFt0i5+xp8h1q8YLj4y0uAy72jSNutbNr260ELRj4W6o7qDKyG+oySBoI zvp/7SKkj40e2WbVCpIap9YcNJFFTiIk4Nt+0xrtyRPT1LznMTFT8xTAqn6JZKPfp6Uj p2OEe0UAxaXRe/znoBkiQOB8lUx8ZpDFuss/Xf/QMX4/A4wkocZLKogi0vFKvz95+jPK yax8ztCSXCChswn0cBzD+Jzfolr+epDUC08sJgmsUUPMuSDEo5WHwck7hLW0MWTVnN0X qj6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=3vPZxMHFHw4oXV4dtRDnDSwBE8znhR5BZiir2CAW8Qw=; b=JPdrL/+Ex1Pw7Ge6EjURs3Zz1DiBvTIyXlfyK+gXEmakvMEsn1kaj/g1v32FgWZlZM lU6dSeKJi/9lXZZM6OKguCKLGHU7lTkojR66x1d/ConF3rcpYlZKpTK4yNpasexoSRmX jxB1Yu/sCmqzhS7ivfcjNHeT/WZNyGzMf/R0XRH/4RHFX3fAVfXVvTQ2abURsOJxOF1g 4MJJzsvxiIzs14lJW09ZPN6SXXdOK88i6ieVbTT6z+qGcfAgvqKP5w8xakNHrWcLHN8G nZvXGJs0vknsC74o25UTsNc8EquBpFqJtEkOj375oAqwieQTlwhwvnxHrZL8eT+0+2J9 zQYw== X-Gm-Message-State: AOAM533+lQyRLTDuHq3Fo7ifX5Vq8TTZ2L47rdD/rY6lv+e6tKjpElH4 svjtJQigAOSl8NYTT0mxm4vqW314Nm46q5vTTK4= X-Google-Smtp-Source: ABdhPJxOleJOPfsb/593+Ty6slJ+bmj1kOad9B7NUSTGNkKnyd4FAl7HBVxGb4xstl7g0jGvSKhbrmtgCl6/iISC+Vs= X-Received: by 2002:a05:6638:150e:b0:32b:3a56:1681 with SMTP id b14-20020a056638150e00b0032b3a561681mr3314154jat.280.1651412727707; Sun, 01 May 2022 06:45:27 -0700 (PDT) MIME-Version: 1.0 References: <20220325130351.3207019-1-rbhansali@marvell.com> In-Reply-To: <20220325130351.3207019-1-rbhansali@marvell.com> From: Jerin Jacob Date: Sun, 1 May 2022 19:15:01 +0530 Message-ID: Subject: Re: [PATCH 1/4] common/cnxk: add CN103XX platform support To: Rahul Bhansali , Thomas Monjalon , Ferruh Yigit Cc: dpdk-dev , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Jerin Jacob Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Fri, Mar 25, 2022 at 6:34 PM Rahul Bhansali wrote: > > Added support for CN103XX (cn10kb) platform. Since 2/4. 3/4, 4/4 patches do not have any special description. Please squash all patches and send v2. It can go through the main tree as it touches all driver's PCI ID values. > > Signed-off-by: Rahul Bhansali > --- > doc/guides/platform/cnxk.rst | 1 + > drivers/common/cnxk/roc_constants.h | 1 + > drivers/common/cnxk/roc_model.c | 4 ++++ > drivers/common/cnxk/roc_model.h | 11 ++++++++++- > 4 files changed, 16 insertions(+), 1 deletion(-) > > diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst > index 3dee725ac5..92aa702a78 100644 > --- a/doc/guides/platform/cnxk.rst > +++ b/doc/guides/platform/cnxk.rst > @@ -18,6 +18,7 @@ Supported OCTEON cnxk SoCs > - CN98xx > - CN106xx > - CNF105xx > +- CN103XX > > Resource Virtualization Unit architecture > ----------------------------------------- > diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h > index 38e2087a26..1daaabfe55 100644 > --- a/drivers/common/cnxk/roc_constants.h > +++ b/drivers/common/cnxk/roc_constants.h > @@ -52,6 +52,7 @@ > #define PCI_SUBSYSTEM_DEVID_CN10KA 0xB900 > #define PCI_SUBSYSTEM_DEVID_CN10KAS 0xB900 > #define PCI_SUBSYSTEM_DEVID_CNF10KA 0xBA00 > +#define PCI_SUBSYSTEM_DEVID_CN10KB 0xB900 > > #define PCI_SUBSYSTEM_DEVID_CN9KA 0x0000 > #define PCI_SUBSYSTEM_DEVID_CN9KB 0xb400 > diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c > index 4120029541..1dd374e0fd 100644 > --- a/drivers/common/cnxk/roc_model.c > +++ b/drivers/common/cnxk/roc_model.c > @@ -16,6 +16,7 @@ struct roc_model *roc_model; > #define PART_106xx 0xB9 > #define PART_105xx 0xBA > #define PART_105xxN 0xBC > +#define PART_103xx 0xBE > #define PART_98xx 0xB1 > #define PART_96xx 0xB2 > #define PART_95xx 0xB3 > @@ -46,6 +47,7 @@ static const struct model_db { > } model_db[] = { > {VENDOR_ARM, PART_106xx, 0, 0, ROC_MODEL_CN106xx_A0, "cn10ka_a0"}, > {VENDOR_ARM, PART_105xx, 0, 0, ROC_MODEL_CNF105xx_A0, "cnf10ka_a0"}, > + {VENDOR_ARM, PART_103xx, 0, 0, ROC_MODEL_CN103xx_A0, "cn10kb_a0"}, > {VENDOR_ARM, PART_105xxN, 0, 0, ROC_MODEL_CNF105xxN_A0, "cnf10kb_a0"}, > {VENDOR_CAVIUM, PART_98xx, 0, 0, ROC_MODEL_CN98xx_A0, "cn98xx_a0"}, > {VENDOR_CAVIUM, PART_96xx, 0, 0, ROC_MODEL_CN96xx_A0, "cn96xx_a0"}, > @@ -92,6 +94,8 @@ cn10k_part_get(void) > soc = PART_105xx; > } else if (strcmp("cnf10kb", ptr) == 0) { > soc = PART_105xxN; > + } else if (strcmp("cn10kb", ptr) == 0) { > + soc = PART_103xx; > } else { > plt_err("Unidentified 'CPU compatible': <%s>", ptr); > goto fclose; > diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h > index 4567566169..885c3d668f 100644 > --- a/drivers/common/cnxk/roc_model.h > +++ b/drivers/common/cnxk/roc_model.h > @@ -24,6 +24,7 @@ struct roc_model { > #define ROC_MODEL_CN106xx_A0 BIT_ULL(20) > #define ROC_MODEL_CNF105xx_A0 BIT_ULL(21) > #define ROC_MODEL_CNF105xxN_A0 BIT_ULL(22) > +#define ROC_MODEL_CN103xx_A0 BIT_ULL(23) > /* Following flags describe platform code is running on */ > #define ROC_ENV_HW BIT_ULL(61) > #define ROC_ENV_EMUL BIT_ULL(62) > @@ -50,8 +51,10 @@ struct roc_model { > #define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0) > #define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0) > #define ROC_MODEL_CNF105xxN (ROC_MODEL_CNF105xxN_A0) > +#define ROC_MODEL_CN103xx (ROC_MODEL_CN103xx_A0) > #define ROC_MODEL_CN10K \ > - (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN) > + (ROC_MODEL_CN106xx | ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN | \ > + ROC_MODEL_CN103xx) > #define ROC_MODEL_CNF10K (ROC_MODEL_CNF105xx | ROC_MODEL_CNF105xxN) > > /* Runtime variants */ > @@ -152,6 +155,12 @@ roc_model_is_cnf10kb(void) > return roc_model->flag & ROC_MODEL_CNF105xxN; > } > > +static inline uint64_t > +roc_model_is_cn10kb_a0(void) > +{ > + return roc_model->flag & ROC_MODEL_CN103xx_A0; > +} > + > static inline uint64_t > roc_model_is_cn10ka_a0(void) > { > -- > 2.25.1 >