From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A560429A5; Fri, 21 Apr 2023 07:00:50 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C2C8410DD; Fri, 21 Apr 2023 07:00:50 +0200 (CEST) Received: from mail-vk1-f172.google.com (mail-vk1-f172.google.com [209.85.221.172]) by mails.dpdk.org (Postfix) with ESMTP id 3FE6440E6E for ; Fri, 21 Apr 2023 07:00:48 +0200 (CEST) Received: by mail-vk1-f172.google.com with SMTP id 71dfb90a1353d-4408b81ed86so405144e0c.3 for ; Thu, 20 Apr 2023 22:00:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682053247; x=1684645247; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=E+YXlEWPOAQfdT0dtHxyjEXLiyXDFq3pU4XHuUEm6Js=; b=ryRSs6hkF4rrHwybQzXIp5GyoIetf5uhivDMgqSfgNvHiH/yFghpZxYwyeO2jQmYut /WcMra7Q5S3g96LFKZuEW9rn5J+RqCFRT5T3qNMeJZFODcVhZIpOXPZcTMV4Z6IDrxsX 5dFrHEOrdCy8YOMX34w0ugkuLjZr+8BHpg6kDS72jyiY/kN+W/qw10rcud1CeYKof6I8 3xTyttWwmjf9hKQr5SY4p2YX7kT+Vb21ZpdfV28vvA7fSirOSPP3jBVoXs7/NgTJ07jc Ti8yud7X/oq7towO2gF2lnc5Mld6YrMvQC1PAOUXTNBwxL3BVrBgaLSKBJOyxfskt5H2 n1ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682053247; x=1684645247; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E+YXlEWPOAQfdT0dtHxyjEXLiyXDFq3pU4XHuUEm6Js=; b=d4wKktVcaRRIgl3eGc1YzoSAIT6U4wQ3hizpsMBjuMSCHD10ppu91MEWj/2Uf2+dNc fjAwkHARingPdVcxz9CAi1yKxqnSk8GMA7iDNoe16NuvHg90uqcyF1bHnjuSt/HkUVn/ 4Hc94iObblDSOnw19l12BHBsjm6w96/4bS15mHbWMsTCupluQTi7etpsOvA0pTsMJczL bqh9iwjBXsQkq/jP48McKdh8xmjzwHpT3buPvuA4MB8bX7ByjXddZNQ2sJSGdMvOKH2f ek7TZviWxCRy0EfdIbpuM0JN9Jg30jqdCYW4ItvZtflsqewzzvZ1fWbl5j9sUjyl9RPz RRDg== X-Gm-Message-State: AAQBX9ctHm+dL2Pk7OOrPNamXwd/X+Oyh9VGPnzPV3DjDTaqhqkJ6+16 UTluTbO9c3mJV6SXV86BZGcTuPvp7x3MvayrEobuvtjX9AKuWEl3 X-Google-Smtp-Source: AKy350ZtAWWwdcsk8uRES5hKOeN0xElZE9ae2LbPnnwg/IOjZ/8fJlmoaAV/doXVd6uk5RwHgxtz8ip5kLb5wY2uuns= X-Received: by 2002:a1f:4146:0:b0:43f:cadf:9ef3 with SMTP id o67-20020a1f4146000000b0043fcadf9ef3mr331803vka.8.1682053247163; Thu, 20 Apr 2023 22:00:47 -0700 (PDT) MIME-Version: 1.0 References: <20230404141855.1025625-2-sedara@marvell.com> <20230405142537.1899973-1-sedara@marvell.com> <20230405142537.1899973-9-sedara@marvell.com> In-Reply-To: <20230405142537.1899973-9-sedara@marvell.com> From: Jerin Jacob Date: Fri, 21 Apr 2023 10:30:21 +0530 Message-ID: Subject: Re: [PATCH v2 08/10] net/octeon_ep: support Mailbox between VF and PF To: Sathesh Edara Cc: sburla@marvell.com, jerinj@marvell.com, Radha Mohan Chintakuntla , Veerasenareddy Burru , dev@dpdk.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Wed, Apr 5, 2023 at 7:56=E2=80=AFPM Sathesh Edara w= rote: > > This patch adds the mailbox communication between > VF and PF and supports the following mailbox > messages. > - Get and set MAC address > - Get link information > - Get stats > - Get and set link status > - Set and get MTU > - Send notification to PF > > Signed-off-by: Sathesh Edara 1) Change "Mailbox" to "mailbox" in subject line 2) Please cross check, Do you need to update new items in doc/guides/nics/features/octeon_ep.ini by adding this new features. See doc/guides/nics/features.rst for list of features. > --- > drivers/net/octeon_ep/cnxk_ep_vf.c | 1 + > drivers/net/octeon_ep/cnxk_ep_vf.h | 12 +- > drivers/net/octeon_ep/meson.build | 1 + > drivers/net/octeon_ep/otx_ep_common.h | 26 +++ > drivers/net/octeon_ep/otx_ep_ethdev.c | 143 +++++++++++- > drivers/net/octeon_ep/otx_ep_mbox.c | 309 ++++++++++++++++++++++++++ > drivers/net/octeon_ep/otx_ep_mbox.h | 163 ++++++++++++++ > 7 files changed, 642 insertions(+), 13 deletions(-) > create mode 100644 drivers/net/octeon_ep/otx_ep_mbox.c > create mode 100644 drivers/net/octeon_ep/otx_ep_mbox.h > > diff --git a/drivers/net/octeon_ep/cnxk_ep_vf.c b/drivers/net/octeon_ep/c= nxk_ep_vf.c > index a437ae68cb..cadb4ecbf9 100644 > --- a/drivers/net/octeon_ep/cnxk_ep_vf.c > +++ b/drivers/net/octeon_ep/cnxk_ep_vf.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include "otx_ep_common.h" > #include "cnxk_ep_vf.h" > > static void > diff --git a/drivers/net/octeon_ep/cnxk_ep_vf.h b/drivers/net/octeon_ep/c= nxk_ep_vf.h > index 072b38ea15..86277449ea 100644 > --- a/drivers/net/octeon_ep/cnxk_ep_vf.h > +++ b/drivers/net/octeon_ep/cnxk_ep_vf.h > @@ -5,7 +5,7 @@ > #define _CNXK_EP_VF_H_ > > #include > -#include "otx_ep_common.h" > + > #define CNXK_CONFIG_XPANSION_BAR 0x38 > #define CNXK_CONFIG_PCIE_CAP 0x70 > #define CNXK_CONFIG_PCIE_DEVCAP 0x74 > @@ -92,6 +92,10 @@ > #define CNXK_EP_R_OUT_BYTE_CNT_START 0x10190 > #define CNXK_EP_R_OUT_CNTS_ISM_START 0x10510 > > +#define CNXK_EP_R_MBOX_PF_VF_DATA_START 0x10210 > +#define CNXK_EP_R_MBOX_VF_PF_DATA_START 0x10230 > +#define CNXK_EP_R_MBOX_PF_VF_INT_START 0x10220 > + > #define CNXK_EP_R_OUT_CNTS(ring) \ > (CNXK_EP_R_OUT_CNTS_START + ((ring) * CNXK_EP_RING_OFFSET)) > > @@ -125,6 +129,12 @@ > #define CNXK_EP_R_OUT_CNTS_ISM(ring) \ > (CNXK_EP_R_OUT_CNTS_ISM_START + ((ring) * CNXK_EP_RING_OFFSET)) > > +#define CNXK_EP_R_MBOX_VF_PF_DATA(ring) \ > + (CNXK_EP_R_MBOX_VF_PF_DATA_START + ((ring) * CNXK_EP_RING_OFFSET)= ) > + > +#define CNXK_EP_R_MBOX_PF_VF_INT(ring) \ > + (CNXK_EP_R_MBOX_PF_VF_INT_START + ((ring) * CNXK_EP_RING_OFFSET)) > + > /*------------------ R_OUT Masks ----------------*/ > #define CNXK_EP_R_OUT_INT_LEVELS_BMODE (1ULL << 63) > #define CNXK_EP_R_OUT_INT_LEVELS_TIMET (32) > diff --git a/drivers/net/octeon_ep/meson.build b/drivers/net/octeon_ep/me= son.build > index a267b60290..e698bf9792 100644 > --- a/drivers/net/octeon_ep/meson.build > +++ b/drivers/net/octeon_ep/meson.build > @@ -8,4 +8,5 @@ sources =3D files( > 'otx_ep_vf.c', > 'otx2_ep_vf.c', > 'cnxk_ep_vf.c', > + 'otx_ep_mbox.c', > ) > diff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_e= p/otx_ep_common.h > index 3beec71968..0bf5454a39 100644 > --- a/drivers/net/octeon_ep/otx_ep_common.h > +++ b/drivers/net/octeon_ep/otx_ep_common.h > @@ -4,6 +4,7 @@ > #ifndef _OTX_EP_COMMON_H_ > #define _OTX_EP_COMMON_H_ > > +#include > > #define OTX_EP_NW_PKT_OP 0x1220 > #define OTX_EP_NW_CMD_OP 0x1221 > @@ -67,6 +68,9 @@ > #define oct_ep_read64(addr) rte_read64_relaxed((void *)(addr)) > #define oct_ep_write64(val, addr) rte_write64_relaxed((val), (void *)(ad= dr)) > > +/* Mailbox maximum data size */ > +#define MBOX_MAX_DATA_BUF_SIZE 320 > + > /* Input Request Header format */ > union otx_ep_instr_irh { > uint64_t u64; > @@ -488,6 +492,18 @@ struct otx_ep_device { > > /* DMA buffer for SDP ISM messages */ > const struct rte_memzone *ism_buffer_mz; > + > + /* Mailbox lock */ > + rte_spinlock_t mbox_lock; > + > + /* Mailbox data */ > + uint8_t mbox_data_buf[MBOX_MAX_DATA_BUF_SIZE]; > + > + /* Mailbox data index */ > + int32_t mbox_data_index; > + > + /* Mailbox receive message length */ > + int32_t mbox_rcv_message_len; > }; > > int otx_ep_setup_iqs(struct otx_ep_device *otx_ep, uint32_t iq_no, > @@ -541,6 +557,16 @@ struct otx_ep_buf_free_info { > #define OTX_EP_CLEAR_SLIST_DBELL 0xFFFFFFFF > #define OTX_EP_CLEAR_SDP_OUT_PKT_CNT 0xFFFFFFFFF > > +/* Max overhead includes > + * - Ethernet hdr > + * - CRC > + * - nested VLANs > + * - octeon rx info > + */ > +#define OTX_EP_ETH_OVERHEAD \ > + (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \ > + (2 * RTE_VLAN_HLEN) + OTX_EP_DROQ_INFO_SIZE) > + > /* PCI IDs */ > #define PCI_VENDOR_ID_CAVIUM 0x177D > > diff --git a/drivers/net/octeon_ep/otx_ep_ethdev.c b/drivers/net/octeon_e= p/otx_ep_ethdev.c > index 0f710b1ffa..885fbb475f 100644 > --- a/drivers/net/octeon_ep/otx_ep_ethdev.c > +++ b/drivers/net/octeon_ep/otx_ep_ethdev.c > @@ -10,6 +10,7 @@ > #include "otx2_ep_vf.h" > #include "cnxk_ep_vf.h" > #include "otx_ep_rxtx.h" > +#include "otx_ep_mbox.h" > > #define OTX_EP_DEV(_eth_dev) \ > ((struct otx_ep_device *)(_eth_dev)->data->dev_private) > @@ -31,15 +32,24 @@ otx_ep_dev_info_get(struct rte_eth_dev *eth_dev, > struct rte_eth_dev_info *devinfo) > { > struct otx_ep_device *otx_epvf; > + int max_rx_pktlen; > > otx_epvf =3D OTX_EP_DEV(eth_dev); > > + max_rx_pktlen =3D otx_ep_mbox_get_max_pkt_len(eth_dev); > + if (!max_rx_pktlen) { > + otx_ep_err("Failed to get Max Rx packet length"); > + return -EINVAL; > + } > + > devinfo->speed_capa =3D RTE_ETH_LINK_SPEED_10G; > devinfo->max_rx_queues =3D otx_epvf->max_rx_queues; > devinfo->max_tx_queues =3D otx_epvf->max_tx_queues; > > devinfo->min_rx_bufsize =3D OTX_EP_MIN_RX_BUF_SIZE; > - devinfo->max_rx_pktlen =3D OTX_EP_MAX_PKT_SZ; > + devinfo->max_rx_pktlen =3D max_rx_pktlen; > + devinfo->max_mtu =3D devinfo->max_rx_pktlen - OTX_EP_ETH_OVERHEAD= ; > + devinfo->min_mtu =3D RTE_ETHER_MIN_LEN; > devinfo->rx_offload_capa =3D RTE_ETH_RX_OFFLOAD_SCATTER; > devinfo->tx_offload_capa =3D RTE_ETH_TX_OFFLOAD_MULTI_SEGS; > > @@ -54,6 +64,71 @@ otx_ep_dev_info_get(struct rte_eth_dev *eth_dev, > return 0; > } > > +static int > +otx_ep_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete= ) > +{ > + RTE_SET_USED(wait_to_complete); > + > + if (!eth_dev->data->dev_started) > + return 0; > + struct rte_eth_link link; > + int ret =3D 0; > + > + memset(&link, 0, sizeof(link)); > + ret =3D otx_ep_mbox_get_link_info(eth_dev, &link); > + if (ret) > + return -EINVAL; > + otx_ep_dbg("link status resp link %d duplex %d autoneg %d link_sp= eed %d\n", > + link.link_status, link.link_duplex, link.link_autoneg= , link.link_speed); > + return rte_eth_linkstatus_set(eth_dev, &link); > +} > + > +static int > +otx_ep_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) > +{ > + struct rte_eth_dev_info devinfo; > + int32_t ret =3D 0; > + > + if (otx_ep_dev_info_get(eth_dev, &devinfo)) { > + otx_ep_err("Cannot set MTU to %u: failed to get device in= fo", mtu); > + return -EPERM; > + } > + > + /* Check if MTU is within the allowed range */ > + if (mtu < devinfo.min_mtu) { > + otx_ep_err("Invalid MTU %u: lower than minimum MTU %u", m= tu, devinfo.min_mtu); > + return -EINVAL; > + } > + > + if (mtu > devinfo.max_mtu) { > + otx_ep_err("Invalid MTU %u; higher than maximum MTU %u", = mtu, devinfo.max_mtu); > + return -EINVAL; > + } > + > + ret =3D otx_ep_mbox_set_mtu(eth_dev, mtu); > + if (ret) > + return -EINVAL; > + > + otx_ep_dbg("MTU is set to %u", mtu); > + > + return 0; > +} > + > +static int > +otx_ep_dev_set_default_mac_addr(struct rte_eth_dev *eth_dev, > + struct rte_ether_addr *mac_addr) > +{ > + int ret; > + > + ret =3D otx_ep_mbox_set_mac_addr(eth_dev, mac_addr); > + if (ret) > + return -EINVAL; > + otx_ep_dbg("Default MAC address " RTE_ETHER_ADDR_PRT_FMT "\n", > + RTE_ETHER_ADDR_BYTES(mac_addr)); > + rte_ether_addr_copy(mac_addr, eth_dev->data->mac_addrs); > + return 0; > +} > + > static int > otx_ep_dev_start(struct rte_eth_dev *eth_dev) > { > @@ -78,6 +153,7 @@ otx_ep_dev_start(struct rte_eth_dev *eth_dev) > rte_read32(otx_epvf->droq[q]->pkts_credit_reg)); > } > > + otx_ep_dev_link_update(eth_dev, 0); > otx_ep_info("dev started\n"); > > return 0; > @@ -454,6 +530,7 @@ otx_ep_dev_close(struct rte_eth_dev *eth_dev) > struct otx_ep_device *otx_epvf =3D OTX_EP_DEV(eth_dev); > uint32_t num_queues, q_no; > > + otx_ep_mbox_send_dev_exit(eth_dev); > otx_epvf->fn_list.disable_io_queues(otx_epvf); > num_queues =3D otx_epvf->nb_rx_queues; > for (q_no =3D 0; q_no < num_queues; q_no++) { > @@ -482,19 +559,17 @@ otx_ep_dev_close(struct rte_eth_dev *eth_dev) > } > > static int > -otx_ep_dev_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete= ) > +otx_ep_dev_get_mac_addr(struct rte_eth_dev *eth_dev, > + struct rte_ether_addr *mac_addr) > { > - RTE_SET_USED(wait_to_complete); > - > - if (!eth_dev->data->dev_started) > - return 0; > - struct rte_eth_link link; > + int ret; > > - memset(&link, 0, sizeof(link)); > - link.link_status =3D RTE_ETH_LINK_UP; > - link.link_speed =3D RTE_ETH_SPEED_NUM_10G; > - link.link_duplex =3D RTE_ETH_LINK_FULL_DUPLEX; > - return rte_eth_linkstatus_set(eth_dev, &link); > + ret =3D otx_ep_mbox_get_mac_addr(eth_dev, mac_addr); > + if (ret) > + return -EINVAL; > + otx_ep_dbg("Get MAC address " RTE_ETHER_ADDR_PRT_FMT "\n", > + RTE_ETHER_ADDR_BYTES(mac_addr)); > + return 0; > } > > /* Define our ethernet definitions */ > @@ -511,6 +586,8 @@ static const struct eth_dev_ops otx_ep_eth_dev_ops = =3D { > .stats_reset =3D otx_ep_dev_stats_reset, > .link_update =3D otx_ep_dev_link_update, > .dev_close =3D otx_ep_dev_close, > + .mtu_set =3D otx_ep_dev_mtu_set, > + .mac_addr_set =3D otx_ep_dev_set_default_mac_addr, > }; > > static int > @@ -526,6 +603,37 @@ otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev) > return 0; > } > > +static int otx_ep_eth_dev_query_set_vf_mac(struct rte_eth_dev *eth_dev, > + struct rte_ether_addr *mac_add= r) > +{ > + int ret_val; > + > + memset(mac_addr, 0, sizeof(struct rte_ether_addr)); > + ret_val =3D otx_ep_dev_get_mac_addr(eth_dev, mac_addr); > + if (!ret_val) { > + if (!rte_is_valid_assigned_ether_addr(mac_addr)) { > + otx_ep_dbg("PF doesn't have valid VF MAC addr" RT= E_ETHER_ADDR_PRT_FMT "\n", > + RTE_ETHER_ADDR_BYTES(mac_addr)); > + rte_eth_random_addr(mac_addr->addr_bytes); > + otx_ep_dbg("Setting Random MAC address" RTE_ETHER= _ADDR_PRT_FMT "\n", > + RTE_ETHER_ADDR_BYTES(mac_addr)); > + ret_val =3D otx_ep_dev_set_default_mac_addr(eth_d= ev, mac_addr); > + if (ret_val) { > + otx_ep_err("Setting MAC address " RTE_ETH= ER_ADDR_PRT_FMT "fails\n", > + RTE_ETHER_ADDR_BYTES(mac_addr= )); > + return ret_val; > + } > + } > + otx_ep_dbg("Received valid MAC addr from PF" RTE_ETHER_AD= DR_PRT_FMT "\n", > + RTE_ETHER_ADDR_BYTES(mac_addr)); > + } else { > + otx_ep_err("Getting MAC address from PF via Mbox fails wi= th ret_val: %d\n", > + ret_val); > + return ret_val; > + } > + return 0; > +} > + > static int > otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) > { > @@ -541,6 +649,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) > otx_epvf->eth_dev =3D eth_dev; > otx_epvf->port_id =3D eth_dev->data->port_id; > eth_dev->dev_ops =3D &otx_ep_eth_dev_ops; > + rte_spinlock_init(&otx_epvf->mbox_lock); > eth_dev->data->mac_addrs =3D rte_zmalloc("otx_ep", RTE_ETHER_ADDR= _LEN, 0); > if (eth_dev->data->mac_addrs =3D=3D NULL) { > otx_ep_err("MAC addresses memory allocation failed\n"); > @@ -572,6 +681,16 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev) > return -EINVAL; > } > > + if (otx_ep_mbox_version_check(eth_dev)) > + return -EINVAL; > + > + if (otx_ep_eth_dev_query_set_vf_mac(eth_dev, > + (struct rte_ether_addr *)&vf_mac_addr)) { > + otx_ep_err("set mac addr failed\n"); > + return -ENODEV; > + } > + rte_ether_addr_copy(&vf_mac_addr, eth_dev->data->mac_addrs); > + > return 0; > } > > diff --git a/drivers/net/octeon_ep/otx_ep_mbox.c b/drivers/net/octeon_ep/= otx_ep_mbox.c > new file mode 100644 > index 0000000000..1ad36e14c8 > --- /dev/null > +++ b/drivers/net/octeon_ep/otx_ep_mbox.c > @@ -0,0 +1,309 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(C) 2021 Marvell. > + */ > + > +#include > +#include > +#include > + > +#include "otx_ep_common.h" > +#include "otx_ep_vf.h" > +#include "otx2_ep_vf.h" > +#include "cnxk_ep_vf.h" > +#include "otx_ep_mbox.h" > + > +static int > +__otx_ep_send_mbox_cmd(struct otx_ep_device *otx_ep, > + union otx_ep_mbox_word cmd, > + union otx_ep_mbox_word *rsp) > +{ > + volatile uint64_t reg_val =3D 0ull; > + int count =3D 0; > + > + cmd.s.type =3D OTX_EP_MBOX_TYPE_CMD; > + otx2_write64(cmd.u64, otx_ep->hw_addr + CNXK_EP_R_MBOX_VF_PF_DATA= (0)); > + > + /* No response for notification messages */ > + if (!rsp) > + return 0; > + > + for (count =3D 0; count < OTX_EP_MBOX_TIMEOUT_MS; count++) { > + rte_delay_ms(1); > + reg_val =3D otx2_read64(otx_ep->hw_addr + CNXK_EP_R_MBOX_= VF_PF_DATA(0)); > + if (reg_val !=3D cmd.u64) { > + rsp->u64 =3D reg_val; > + break; > + } > + } > + if (count =3D=3D OTX_EP_MBOX_TIMEOUT_MS) { > + otx_ep_err("mbox send Timeout count:%d\n", count); > + return OTX_EP_MBOX_TIMEOUT_MS; > + } > + if (rsp->s.type !=3D OTX_EP_MBOX_TYPE_RSP_ACK) { > + otx_ep_err("mbox received NACK from PF\n"); > + return OTX_EP_MBOX_CMD_STATUS_NACK; > + } > + > + rsp->u64 =3D reg_val; > + return 0; > +} > + > +static int > +otx_ep_send_mbox_cmd(struct otx_ep_device *otx_ep, > + union otx_ep_mbox_word cmd, > + union otx_ep_mbox_word *rsp) > +{ > + int ret; > + > + rte_spinlock_lock(&otx_ep->mbox_lock); > + ret =3D __otx_ep_send_mbox_cmd(otx_ep, cmd, rsp); > + rte_spinlock_unlock(&otx_ep->mbox_lock); > + return ret; > +} > + > +static int > +otx_ep_mbox_bulk_read(struct otx_ep_device *otx_ep, > + enum otx_ep_mbox_opcode opcode, > + uint8_t *data, int32_t *size) > +{ > + union otx_ep_mbox_word cmd; > + union otx_ep_mbox_word rsp; > + int read_cnt, i =3D 0, ret; > + int data_len =3D 0, tmp_len =3D 0; > + > + rte_spinlock_lock(&otx_ep->mbox_lock); > + cmd.u64 =3D 0; > + cmd.s_data.opcode =3D opcode; > + cmd.s_data.frag =3D 0; > + /* Send cmd to read data from PF */ > + ret =3D __otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp); > + if (ret) { > + otx_ep_err("mbox bulk read data request failed\n"); > + rte_spinlock_unlock(&otx_ep->mbox_lock); > + return ret; > + } > + /* PF sends the data length of requested CMD > + * in ACK > + */ > + memcpy(&data_len, rsp.s_data.data, sizeof(data_len)); > + tmp_len =3D data_len; > + cmd.u64 =3D 0; > + rsp.u64 =3D 0; > + cmd.s_data.opcode =3D opcode; > + cmd.s_data.frag =3D 1; > + while (data_len) { > + ret =3D __otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp); > + if (ret) { > + otx_ep_err("mbox bulk read data request failed\n"= ); > + otx_ep->mbox_data_index =3D 0; > + memset(otx_ep->mbox_data_buf, 0, OTX_EP_MBOX_MAX_= DATA_BUF_SIZE); > + rte_spinlock_unlock(&otx_ep->mbox_lock); > + return ret; > + } > + if (data_len > OTX_EP_MBOX_MAX_DATA_SIZE) { > + data_len -=3D OTX_EP_MBOX_MAX_DATA_SIZE; > + read_cnt =3D OTX_EP_MBOX_MAX_DATA_SIZE; > + } else { > + read_cnt =3D data_len; > + data_len =3D 0; > + } > + for (i =3D 0; i < read_cnt; i++) { > + otx_ep->mbox_data_buf[otx_ep->mbox_data_index] = =3D > + rsp.s_data.data[i]; > + otx_ep->mbox_data_index++; > + } > + cmd.u64 =3D 0; > + rsp.u64 =3D 0; > + cmd.s_data.opcode =3D opcode; > + cmd.s_data.frag =3D 1; > + } > + memcpy(data, otx_ep->mbox_data_buf, tmp_len); > + *size =3D tmp_len; > + otx_ep->mbox_data_index =3D 0; > + memset(otx_ep->mbox_data_buf, 0, OTX_EP_MBOX_MAX_DATA_BUF_SIZE); > + rte_spinlock_unlock(&otx_ep->mbox_lock); > + return 0; > +} > + > +int > +otx_ep_mbox_set_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu) > +{ > + struct otx_ep_device *otx_ep =3D > + (struct otx_ep_device *)(eth_dev)->data->dev_private; > + union otx_ep_mbox_word cmd; > + union otx_ep_mbox_word rsp; > + int ret =3D 0; > + > + cmd.u64 =3D 0; > + cmd.s_set_mtu.opcode =3D OTX_EP_MBOX_CMD_SET_MTU; > + cmd.s_set_mtu.mtu =3D mtu; > + > + ret =3D otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp); > + if (ret) { > + otx_ep_err("set MTU failed\n"); > + return -EINVAL; > + } > + otx_ep_dbg("mtu set success mtu %u\n", mtu); > + > + return 0; > +} > + > +int > +otx_ep_mbox_set_mac_addr(struct rte_eth_dev *eth_dev, > + struct rte_ether_addr *mac_addr) > +{ > + struct otx_ep_device *otx_ep =3D > + (struct otx_ep_device *)(eth_dev)->data->dev_private; > + union otx_ep_mbox_word cmd; > + union otx_ep_mbox_word rsp; > + int i, ret; > + > + cmd.u64 =3D 0; > + cmd.s_set_mac.opcode =3D OTX_EP_MBOX_CMD_SET_MAC_ADDR; > + for (i =3D 0; i < RTE_ETHER_ADDR_LEN; i++) > + cmd.s_set_mac.mac_addr[i] =3D mac_addr->addr_bytes[i]; > + ret =3D otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp); > + if (ret) { > + otx_ep_err("set MAC address failed\n"); > + return -EINVAL; > + } > + otx_ep_dbg("%s VF MAC " RTE_ETHER_ADDR_PRT_FMT "\n", > + __func__, RTE_ETHER_ADDR_BYTES(mac_addr)); > + rte_ether_addr_copy(mac_addr, eth_dev->data->mac_addrs); > + return 0; > +} > + > +int > +otx_ep_mbox_get_mac_addr(struct rte_eth_dev *eth_dev, > + struct rte_ether_addr *mac_addr) > +{ > + struct otx_ep_device *otx_ep =3D > + (struct otx_ep_device *)(eth_dev)->data->dev_private; > + union otx_ep_mbox_word cmd; > + union otx_ep_mbox_word rsp; > + int i, ret; > + > + cmd.u64 =3D 0; > + cmd.s_set_mac.opcode =3D OTX_EP_MBOX_CMD_GET_MAC_ADDR; > + ret =3D otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp); > + if (ret) { > + otx_ep_err("get MAC address failed\n"); > + return -EINVAL; > + } > + for (i =3D 0; i < RTE_ETHER_ADDR_LEN; i++) > + mac_addr->addr_bytes[i] =3D rsp.s_set_mac.mac_addr[i]; > + otx_ep_dbg("%s VF MAC " RTE_ETHER_ADDR_PRT_FMT "\n", > + __func__, RTE_ETHER_ADDR_BYTES(mac_addr)); > + return 0; > +} > + > +int otx_ep_mbox_get_link_status(struct rte_eth_dev *eth_dev, > + uint8_t *oper_up) > +{ > + struct otx_ep_device *otx_ep =3D > + (struct otx_ep_device *)(eth_dev)->data->dev_private; > + union otx_ep_mbox_word cmd; > + union otx_ep_mbox_word rsp; > + int ret; > + > + cmd.u64 =3D 0; > + cmd.s_link_status.opcode =3D OTX_EP_MBOX_CMD_GET_LINK_STATUS; > + ret =3D otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp); > + if (ret) { > + otx_ep_err("Get link status failed\n"); > + return -EINVAL; > + } > + *oper_up =3D rsp.s_link_status.status; > + return 0; > +} > + > +int otx_ep_mbox_get_link_info(struct rte_eth_dev *eth_dev, > + struct rte_eth_link *link) > +{ > + int32_t ret, size; > + struct otx_ep_iface_link_info link_info; > + struct otx_ep_device *otx_ep =3D > + (struct otx_ep_device *)(eth_dev)->data->dev_private; > + memset(&link_info, 0, sizeof(struct otx_ep_iface_link_info)); > + ret =3D otx_ep_mbox_bulk_read(otx_ep, OTX_EP_MBOX_CMD_GET_LINK_IN= FO, > + (uint8_t *)&link_info, (int32_t *)&= size); > + if (ret) { > + otx_ep_err("Get link info failed\n"); > + return ret; > + } > + link->link_status =3D RTE_ETH_LINK_UP; > + link->link_duplex =3D RTE_ETH_LINK_FULL_DUPLEX; > + link->link_autoneg =3D (link_info.autoneg =3D=3D > + OTX_EP_LINK_AUTONEG) ? RTE_ETH_LINK_AUTONEG= : RTE_ETH_LINK_FIXED; > + > + link->link_autoneg =3D link_info.autoneg; > + link->link_speed =3D link_info.speed; > + return 0; > +} > + > +void > +otx_ep_mbox_enable_interrupt(struct otx_ep_device *otx_ep) > +{ > + rte_write64(0x2, (uint8_t *)otx_ep->hw_addr + > + CNXK_EP_R_MBOX_PF_VF_INT(0)); > +} > + > +void > +otx_ep_mbox_disable_interrupt(struct otx_ep_device *otx_ep) > +{ > + rte_write64(0x00, (uint8_t *)otx_ep->hw_addr + > + CNXK_EP_R_MBOX_PF_VF_INT(0)); > +} > + > +int > +otx_ep_mbox_get_max_pkt_len(struct rte_eth_dev *eth_dev) > +{ > + struct otx_ep_device *otx_ep =3D > + (struct otx_ep_device *)(eth_dev)->data->dev_private; > + union otx_ep_mbox_word cmd; > + union otx_ep_mbox_word rsp; > + int ret; > + > + rsp.u64 =3D 0; > + cmd.u64 =3D 0; > + cmd.s_get_mtu.opcode =3D OTX_EP_MBOX_CMD_GET_MTU; > + > + ret =3D otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp); > + if (ret) > + return ret; > + return rsp.s_get_mtu.mtu; > +} > + > +int otx_ep_mbox_version_check(struct rte_eth_dev *eth_dev) > +{ > + struct otx_ep_device *otx_ep =3D > + (struct otx_ep_device *)(eth_dev)->data->dev_private; > + union otx_ep_mbox_word cmd; > + union otx_ep_mbox_word rsp; > + int ret; > + > + cmd.u64 =3D 0; > + cmd.s_version.opcode =3D OTX_EP_MBOX_CMD_VERSION; > + cmd.s_version.version =3D OTX_EP_MBOX_VERSION; > + ret =3D otx_ep_send_mbox_cmd(otx_ep, cmd, &rsp); > + if (!ret) > + return 0; > + if (ret =3D=3D OTX_EP_MBOX_CMD_STATUS_NACK) { > + otx_ep_err("VF Mbox version:%u is not compatible with PF\= n", > + (uint32_t)cmd.s_version.version); > + } > + return ret; > +} > + > +int otx_ep_mbox_send_dev_exit(struct rte_eth_dev *eth_dev) > +{ > + struct otx_ep_device *otx_ep =3D > + (struct otx_ep_device *)(eth_dev)->data->dev_private; > + union otx_ep_mbox_word cmd; > + int ret; > + > + cmd.u64 =3D 0; > + cmd.s_version.opcode =3D OTX_EP_MBOX_CMD_DEV_REMOVE; > + ret =3D otx_ep_send_mbox_cmd(otx_ep, cmd, NULL); > + return ret; > +} > diff --git a/drivers/net/octeon_ep/otx_ep_mbox.h b/drivers/net/octeon_ep/= otx_ep_mbox.h > new file mode 100644 > index 0000000000..9df3c53edd > --- /dev/null > +++ b/drivers/net/octeon_ep/otx_ep_mbox.h > @@ -0,0 +1,163 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(C) 2021 Marvell. > + */ > + > +#ifndef _OTX_EP_MBOX_H_ > +#define _OTX_EP_MBOX_H_ > + > + > +#define OTX_EP_MBOX_VERSION 1 > + > +enum otx_ep_mbox_opcode { > + OTX_EP_MBOX_CMD_VERSION, > + OTX_EP_MBOX_CMD_SET_MTU, > + OTX_EP_MBOX_CMD_SET_MAC_ADDR, > + OTX_EP_MBOX_CMD_GET_MAC_ADDR, > + OTX_EP_MBOX_CMD_GET_LINK_INFO, > + OTX_EP_MBOX_CMD_GET_STATS, > + OTX_EP_MBOX_CMD_SET_RX_STATE, > + OTX_EP_MBOX_CMD_SET_LINK_STATUS, > + OTX_EP_MBOX_CMD_GET_LINK_STATUS, > + OTX_EP_MBOX_CMD_GET_MTU, > + OTX_EP_MBOX_CMD_DEV_REMOVE, > + OTX_EP_MBOX_CMD_LAST, > +}; > + > +enum otx_ep_mbox_word_type { > + OTX_EP_MBOX_TYPE_CMD, > + OTX_EP_MBOX_TYPE_RSP_ACK, > + OTX_EP_MBOX_TYPE_RSP_NACK, > +}; > + > +enum otx_ep_mbox_cmd_status { > + OTX_EP_MBOX_CMD_STATUS_NOT_SETUP =3D 1, > + OTX_EP_MBOX_CMD_STATUS_TIMEDOUT =3D 2, > + OTX_EP_MBOX_CMD_STATUS_NACK =3D 3, > + OTX_EP_MBOX_CMD_STATUS_BUSY =3D 4 > +}; > + > +enum otx_ep_mbox_state { > + OTX_EP_MBOX_STATE_IDLE =3D 0, > + OTX_EP_MBOX_STATE_BUSY =3D 1, > +}; > + > +enum otx_ep_link_status { > + OTX_EP_LINK_STATUS_DOWN, > + OTX_EP_LINK_STATUS_UP, > +}; > + > +enum otx_ep_link_duplex { > + OTX_EP_LINK_HALF_DUPLEX, > + OTX_EP_LINK_FULL_DUPLEX, > +}; > + > +enum otx_ep_link_autoneg { > + OTX_EP_LINK_FIXED, > + OTX_EP_LINK_AUTONEG, > +}; > + > +#define OTX_EP_MBOX_TIMEOUT_MS 1200 > +#define OTX_EP_MBOX_MAX_RETRIES 2 > +#define OTX_EP_MBOX_MAX_DATA_SIZE 6 > +#define OTX_EP_MBOX_MAX_DATA_BUF_SIZE 256 > +#define OTX_EP_MBOX_MORE_FRAG_FLAG 1 > +#define OTX_EP_MBOX_WRITE_WAIT_TIME msecs_to_jiffies(1) > + > +union otx_ep_mbox_word { > + uint64_t u64; > + struct { > + uint64_t opcode:8; > + uint64_t type:2; > + uint64_t rsvd:6; > + uint64_t data:48; > + } s; > + struct { > + uint64_t opcode:8; > + uint64_t type:2; > + uint64_t frag:1; > + uint64_t rsvd:5; > + uint8_t data[6]; > + } s_data; > + struct { > + uint64_t opcode:8; > + uint64_t type:2; > + uint64_t rsvd:6; > + uint64_t version:48; > + } s_version; > + struct { > + uint64_t opcode:8; > + uint64_t type:2; > + uint64_t rsvd:6; > + uint8_t mac_addr[6]; > + } s_set_mac; > + struct { > + uint64_t opcode:8; > + uint64_t type:2; > + uint64_t rsvd:6; > + uint64_t mtu:48; > + } s_set_mtu; > + struct { > + uint64_t opcode:8; > + uint64_t type:2; > + uint64_t rsvd:6; > + uint64_t mtu:48; > + } s_get_mtu; > + struct { > + uint64_t opcode:8; > + uint64_t type:2; > + uint64_t state:1; > + uint64_t rsvd:53; > + } s_link_state; > + struct { > + uint64_t opcode:8; > + uint64_t type:2; > + uint64_t status:1; > + uint64_t rsvd:53; > + } s_link_status; > +} __rte_packed; > + > +/* Hardware interface link state information. */ > +struct otx_ep_iface_link_info { > + /* Bitmap of Supported link speeds/modes. */ > + uint64_t supported_modes; > + > + /* Bitmap of Advertised link speeds/modes. */ > + uint64_t advertised_modes; > + > + /* Negotiated link speed in Mbps. */ > + uint32_t speed; > + > + /* MTU */ > + uint16_t mtu; > + > + /* Autonegotiation state. */ > +#define OCTEP_VF_LINK_MODE_AUTONEG_SUPPORTED BIT(0) > +#define OCTEP_VF_LINK_MODE_AUTONEG_ADVERTISED BIT(1) > + uint8_t autoneg; > + > + /* Pause frames setting. */ > +#define OCTEP_VF_LINK_MODE_PAUSE_SUPPORTED BIT(0) > +#define OCTEP_VF_LINK_MODE_PAUSE_ADVERTISED BIT(1) > + uint8_t pause; > + > + /* Admin state of the link (ifconfig up/down */ > + uint8_t admin_up; > + > + /* Operational state of the link: physical link is up down */ > + uint8_t oper_up; > +}; > + > +int otx_ep_mbox_set_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu); > +int otx_ep_mbox_set_mac_addr(struct rte_eth_dev *eth_dev, > + struct rte_ether_addr *mac_addr); > +int otx_ep_mbox_get_mac_addr(struct rte_eth_dev *eth_dev, > + struct rte_ether_addr *mac_addr); > +int otx_ep_mbox_get_link_status(struct rte_eth_dev *eth_dev, > + uint8_t *oper_up); > +int otx_ep_mbox_get_link_info(struct rte_eth_dev *eth_dev, struct rte_et= h_link *link); > +void otx_ep_mbox_enable_interrupt(struct otx_ep_device *otx_ep); > +void otx_ep_mbox_disable_interrupt(struct otx_ep_device *otx_ep); > +int otx_ep_mbox_get_max_pkt_len(struct rte_eth_dev *eth_dev); > +int otx_ep_mbox_version_check(struct rte_eth_dev *eth_dev); > +int otx_ep_mbox_send_dev_exit(struct rte_eth_dev *eth_dev); > +#endif > -- > 2.31.1 >