From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B77E545AA0; Thu, 3 Oct 2024 17:52:43 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A6B4240652; Thu, 3 Oct 2024 17:52:43 +0200 (CEST) Received: from mail-qt1-f171.google.com (mail-qt1-f171.google.com [209.85.160.171]) by mails.dpdk.org (Postfix) with ESMTP id 4FBE64014F for ; Thu, 3 Oct 2024 17:52:42 +0200 (CEST) Received: by mail-qt1-f171.google.com with SMTP id d75a77b69052e-4582f9abb43so7566351cf.2 for ; Thu, 03 Oct 2024 08:52:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727970761; x=1728575561; darn=dpdk.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=gWWzkwzZo3hSnX26UPd7R7SJvJ8TH7NR5dnS6MO4yws=; b=PgZiIRh7coIR5DHs9TVZYmWBivC7Uqgy+hTQ8BQWy6xSuXThcjVyXTmy85mStM1xll 0todT5pOxyhasrs4F/K25cybiJCDd3tJFpkr3eYn6F4iElFk6ppNZf4/7ZFQ56yZqqfF UPTWehyMhs+CpnTbNOuYktE8apUfPlGteaaHXgTWhRScean/JZgv12RgGYtnr49WxavS AMaPp9UAn1QJ6Gqqs6D2RDtNovYw+Jr5Fk20poubnXBQaUKw2fTuDT1yYeATPF1Zg5Ea nO4Ag8+yfMEVhWvP0jFzcc0wFHTF30dsFn2eP/3gZd1AcOuKfQ7Lh78aUvvuRqMDoiOQ msEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727970761; x=1728575561; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gWWzkwzZo3hSnX26UPd7R7SJvJ8TH7NR5dnS6MO4yws=; b=UyunS3mPnDb6PzeBXafzVMrJDzb+y9d0pNurzCZTR4DSkEfFK2Ki4w+vlDOHyh9/Uy htWppmR7L+knviN1gFfSbhgr6H+Ze1arypmZen0KVnVTy5F9lOLgnMdtYfhS9RJCaj38 pw2uwV4fr9s3xn+D11tGBZ3BlDjUCcaWASJJEtBwWb0so4UHI7oyqejyHww0vwIkhf6A Cj59aBU36xFGvNIonkHcXHa34OBCbInQ5zgwsBrJFrhGZdF5NlPcPjAtG5mMKfMfM5P0 Ogdkk2x64JECvE9CZ5iD3Jx9hxzzvEoAuhzK/l86Bd0kC8dmfyXdaTU5lp0ZRqnz/VMf q+PA== X-Forwarded-Encrypted: i=1; AJvYcCWIrAfBhMeSXe6DuJp12P9bRi99R34zjPcFhvaiUFS8GsHK1W5lfCF+U35FbniLDb+MYNQ=@dpdk.org X-Gm-Message-State: AOJu0YxzQzXCPrfl0gjSsllQ7ctx3CKYznRWPW2Zxrzs+SJMQSiqYTZo /zL5EYYZG9VALUd2mGnxpHJFB2OJ4VC2geZ/9443e4X420rPS6dCh65Mtn/Km4PZdhM8KIeRcqF C2Zbz69/L17uGLlBl2OAKWrERqJY= X-Google-Smtp-Source: AGHT+IF7BEaSV5l8glM+0YtY9cuKICtKdSKrD65w3+X4IYn82QAtuGx40VCWzIjAxaEtzbMp/6ozeedblD5UBbEqU88= X-Received: by 2002:a05:622a:446:b0:456:802e:ddc9 with SMTP id d75a77b69052e-45d8049558bmr99307811cf.3.1727970761397; Thu, 03 Oct 2024 08:52:41 -0700 (PDT) MIME-Version: 1.0 References: <20240910085909.1514457-1-ndabilpuram@marvell.com> <20241001124053.3774325-1-ndabilpuram@marvell.com> In-Reply-To: <20241001124053.3774325-1-ndabilpuram@marvell.com> From: Jerin Jacob Date: Thu, 3 Oct 2024 21:22:14 +0530 Message-ID: Subject: Re: [PATCH v3 00/18] add Marvell cn20k SOC support for mempool and net To: Nithin Dabilpuram Cc: jerinj@marvell.com, dev@dpdk.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Wed, Oct 2, 2024 at 4:49=E2=80=AFAM Nithin Dabilpuram wrote: > > This series adds support for Marvell cn20k SOC for mempool and > net PMD's. > > This series also adds few net/cnxk PMD updates to expose IPsec > features supported by HW that are very custom in nature and > some enhancements for cn10k. > > > Ashwin Sekhar T K (4): > mempool/cnxk: add cn20k PCI device ids > common/cnxk: accommodate change in aura field width > common/cnxk: use new NPA aq enq mbox for cn20k > mempool/cnxk: initialize mempool ops for cn20k > > Nithin Dabilpuram (9): > net/cnxk: add cn20k base control path support > net/cnxk: support Rx function select for cn20k > net/cnxk: support Tx function select for cn20k > net/cnxk: support Rx burst scalar for cn20k > net/cnxk: support Rx burst vector for cn20k > net/cnxk: support Tx burst scalar for cn20k > net/cnxk: support Tx multi-seg in cn20k > net/cnxk: support Tx burst vector for cn20k > net/cnxk: support Tx multi-seg in vector for cn20k > > Satha Rao (5): > common/cnxk: add cn20k NIX register definitions > common/cnxk: support NIX queue config for cn20k > common/cnxk: support bandwidth profile for cn20k > common/cnxk: support NIX debug for cn20k > common/cnxk: add RSS support for cn20k Applied series to dpdk-next-net-mrvl/for-main with following diff. Thanks [for-main]dell[dpdk-next-net-mrvl] $ git diff diff --git a/drivers/net/cnxk/cn20k_rx.h b/drivers/net/cnxk/cn20k_rx.h index d1bf0c615e..01bf483787 100644 --- a/drivers/net/cnxk/cn20k_rx.h +++ b/drivers/net/cnxk/cn20k_rx.h @@ -52,9 +52,8 @@ static inline void nix_mbuf_validate_next(struct rte_mbuf *m) { - if (m->nb_segs =3D=3D 1 && m->next) { + if (m->nb_segs =3D=3D 1 && m->next) rte_panic("mbuf->next[%p] valid when mbuf->nb_segs is %d", m->next, m->nb_segs); - } } #else static inline void diff --git a/drivers/net/cnxk/cn20k_tx.h b/drivers/net/cnxk/cn20k_tx.h index bcf7ce6035..c731406529 100644 --- a/drivers/net/cnxk/cn20k_tx.h +++ b/drivers/net/cnxk/cn20k_tx.h @@ -2431,7 +2431,7 @@ cn20k_nix_xmit_pkts_vector(void *tx_queue, uint64_t *ws, struct rte_mbuf **tx_pk senddesc23_w1 =3D vshlq_n_u64(senddesc23_w1, 1); /* Move OLFLAGS bits 55:52 to 51:48 - * with zeros preprended on the byte and rest + * with zeros prepended on the byte and rest * don't care */ xtmp128 =3D vshrq_n_u8(xtmp128, 4); [for-main]dell[dpdk-next-net-mrvl] $