From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 23FB4A0A02; Wed, 24 Mar 2021 17:20:18 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 09226140F2F; Wed, 24 Mar 2021 17:20:18 +0100 (CET) Received: from mail-io1-f46.google.com (mail-io1-f46.google.com [209.85.166.46]) by mails.dpdk.org (Postfix) with ESMTP id 26253140F2E for ; Wed, 24 Mar 2021 17:20:17 +0100 (CET) Received: by mail-io1-f46.google.com with SMTP id r193so22092487ior.9 for ; Wed, 24 Mar 2021 09:20:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=J1KG8Ld8nc+742UGVakjzVQYjPfpgpWafSGI+vNQ2Z8=; b=gRqN8rnvz+LXNRBKYM6llNc7tCxhamadJqzhtTzc+yDyRCiobnf4EvQm75phlB+m3C r8krK5Wv9e/zrdq75SMKbCky2AWTemTA6XIqtipl92vtQ+ZiIYhYARh7AO0qE2jFSR1w sSIbBJpgiGllsp5YNnPzjfNaj1JI6JchTSoC/2gfEFALXGTt34V1SpSWpBFlQvMYtapT JKpZj1lnlneB+XCMGEkYQNowT6OL2eY/VamnbEQM+BNwYJ8sqTe2LxxYCqNvdXGsomwD Q9FZKjSR4zhG7p34glHi4QkFQSJwD5IVMm5ADgfHyi1nnnih+fdwSC7rKLQzKGCoqs2R z29A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=J1KG8Ld8nc+742UGVakjzVQYjPfpgpWafSGI+vNQ2Z8=; b=Uru9lXOdQKXrPv0aqMZzA9VVeZ23Redllsz3Ply8FxqVw1hj0NIIcevqdaS+U2M8u0 rWg/tcHQn5LhuIsNpYWeno/vyR1ZlXgHLcXbBNMNr+/JabJ0hStmUflv3U5iQfC7Lm4d PST2yNNXyaqzk3b6a2a3mAYim+bPdSweDtZwLQNYgP3rtfaQJ9Tt/Q49spTWUxcpCkNF eRmh5emGmbR9nskigN7S22OmUiA6dwYmEO3P4kDF58T9CaXCOUcJXG+uANlBEAhzp0rU jaarFx0mDaYLjqiqIMVoV2n0NXGSodl/Wv3tbkpl7rUaHws+ZhsT8RoG9V2drszAdaFk HGIQ== X-Gm-Message-State: AOAM530mahqWHyw6+T3i0OAL/qpPUxg+SrtqBi4fwVsGHgaCJ0M0eNVn 2f9lp7ufS24Vb+6YTu5ZAnLp0AKTz5uKRlqUheU= X-Google-Smtp-Source: ABdhPJw32NF4jQdbNa5PzJ6A8XXqU+y5TLDs3LW8KIVZJRYmotfHKi+sCqapMGqnQhneASuw9DNOGiuwHJtW1m+gNYo= X-Received: by 2002:a6b:b7cd:: with SMTP id h196mr2986326iof.59.1616602816512; Wed, 24 Mar 2021 09:20:16 -0700 (PDT) MIME-Version: 1.0 References: <20210225190112.2073-1-pbhagavatula@marvell.com> In-Reply-To: From: Jerin Jacob Date: Wed, 24 Mar 2021 21:50:00 +0530 Message-ID: To: David Marchand Cc: Ray Kinsella , Pavan Nikhilesh , Harman Kalra , Thomas Monjalon , Jerin Jacob , Bruce Richardson , dpdk-dev Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH 1/2] eal: make max interrupt vector id configurable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Mar 24, 2021 at 8:56 PM David Marchand wrote: > > On Wed, Mar 24, 2021 at 1:55 PM Jerin Jacob wrote: > > > > IMO, We dont need to make it configurable and each platform sets its > > > > value. That scheme won't work as generic distribution build will fail > > > > to run. > > > > Since PCIe specification defines this value and there is no > > > > performance impact on increasing this, > > > > IMO, We can change to 2048 as default. > > > > > > It probably breaks rte_intr_* ABI. > > > > Yes. Even though all APIs are used as a pointer (ie. "struct > > rte_intr_handle *"), the definition > > kept in the header file. > > > > > > > struct rte_intr_handle { > > > ... > > > int efds[RTE_MAX_RXTX_INTR_VEC_ID]; /**< intr vectors/efds mapping */ > > > struct rte_epoll_event elist[RTE_MAX_RXTX_INTR_VEC_ID]; > > > /**< intr vector epoll event */ > > > ... > > > > > > > > > I see you need this for octeontx2, so wondering if you could handle > > > this differently in octeontx2 drivers? > > > > This is an issue with any PCIe device that has more than 512 MSIX interrupts. > > > > The PCI spec the max is defined as 2K. > > > > CN10K drivers have 1K interrupt lines per PCIe device. > > > > I think, following are the options. > > 1) To avoid ABI breakage in default configuration use the existing patch > > 2) In 21.11 break ABI and Either change to > > a) RTE_MAX_RXTX_INTR_VEC_ID as 1024 > > or > > b) Make it full dynamic allocation based on PCI device MSIX size on probe time. > > That brings some kind of dependency rte_intr with PCI device. Need to > > understand, > > How it can clearly be abstracted out and Is it worth trouble for the > > amount of memory. > > Looks like the cost of one entry is 40B. So additional 512 is 40B * > > 512 = 21KB virtual memory. > > Since you mentioned performance is not impacted, I guess this is > control path only. Yes. > And there is no need to expose this. > So: > > c) Rework API so that we don't expose such details. Yes. That's what I meant by option (b).("Make it fully dynamic allocation based on PCI device MSIX size on probe time.") > > > -- > David Marchand >