From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66F2FA0350; Tue, 30 Jun 2020 07:14:13 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0D34F1B13C; Tue, 30 Jun 2020 07:14:13 +0200 (CEST) Received: from mail-io1-f68.google.com (mail-io1-f68.google.com [209.85.166.68]) by dpdk.org (Postfix) with ESMTP id E3BDD1150 for ; Tue, 30 Jun 2020 07:14:11 +0200 (CEST) Received: by mail-io1-f68.google.com with SMTP id f6so4047847ioj.5 for ; Mon, 29 Jun 2020 22:14:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=NkjYf8INeNF9Oip1JEo1sr1N60MwqSqv7FJRmJzh0J0=; b=lG3CnNDtBKDlBjfgbAOtHE7mjCjCkhgOfM2rqQO/V/5LoQ1PXUbqW5XJHHr0pGO+v4 0uSMlULbKaDZhA56RRSL3fML5vSslS1K0N0SJTXZvijinepV7nbGVkYdELgsuAcKpSHD MSRo+6+hlUTCgP9GfEtZtnhzswIm1/bO9Sfib+pveyOQOjjiXO9RykV6IVkqUBJt4aVA 23r5PYUkFgBFIQKOQJ6tH6L8gWNXtFiO4PDeLxSMyccltctzs+F5vQQpZJF4o0AcUDjc OmGGOk8GEo+zgUuGF9l/L/UmBnwfpc8hGSzKn+fjg5ewPBL6pNLwM3fTXx/IS1xSj4nH immw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NkjYf8INeNF9Oip1JEo1sr1N60MwqSqv7FJRmJzh0J0=; b=o2Inybx3swEJBwSCkfLqb6EGLnGrC25MYWS5MiTRfG3KGnzQsviSzyvk7/DpEXwAKn MqlTux8E8G/mBz84y/Da/azShUJqSH42D/V0sMLyl3ooJVCewUF1xrPkuVdgZ7/X3Ewc 2kPlweafm633QoUM1ay+4pAUJNjLAmLGKV36SnYeUcJzZlv726h3rmKTHZFDpVwjWSc3 LfOfIWcAYd8+kzGZopOF7TmJc3rvDjrAEEesBvBaPKatgj6FmsSElnhj6BsdFfQIUL1R ZKMlO8u8a7jSMqC6yGFr44yK3wmdZWSKZtcMPgRwGBx+LE6ov2SZ93iZlcWZmqX5EaaM 5E1A== X-Gm-Message-State: AOAM530NfOIf8eV6YD+Qwrx9qhTLpRkvuSlqQlv6kjSPtX7Jk0BIi70w Povr6udR6Ns0OTE7fWRR+ZLxcMUo3Boyb8+XtD8= X-Google-Smtp-Source: ABdhPJzeRS8og6Rioor0IwSW3EVOcIzncgoiNVmsol+GMEfNly8wifN7NWZQL0wIcq6rIti4BMJd8kkGElLLvboc71o= X-Received: by 2002:a02:2b24:: with SMTP id h36mr21663940jaa.104.1593494051171; Mon, 29 Jun 2020 22:14:11 -0700 (PDT) MIME-Version: 1.0 References: <20200410164127.54229-1-gavin.hu@arm.com> <20200627191208.34520-1-honnappa.nagarahalli@arm.com> In-Reply-To: From: Jerin Jacob Date: Tue, 30 Jun 2020 10:43:55 +0530 Message-ID: To: Honnappa Nagarahalli Cc: "dev@dpdk.org" , Ruifeng Wang , "jerinj@marvell.com" , "hemant.agrawal@nxp.com" , "Ajit Khaparde (ajit.khaparde@broadcom.com)" , "igorch@amazon.com" , "thomas@monjalon.net" , "viacheslavo@mellanox.com" , "arybchenko@solarflare.com" , "bruce.richardson@intel.com" , nd Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2] eal: adjust barriers for IO on Armv8-a X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Sun, Jun 28, 2020 at 12:55 AM Honnappa Nagarahalli wrote: > > Hi Jerin, > You had a comment earlier about deprecating rte_cio_[rw]mb. Let me know if you are ok with this patch and I can add those changes (replace references to rte_cio_[rw]mb with rte_io_[rw]mb and a deprecation notice). Acked-by: Jerin Jacob for this patch Please send the deprecation notice for overlapping rte_cio_* for 20.11 > > Thanks, > Honnappa > > > -----Original Message----- > > From: Honnappa Nagarahalli > > Sent: Saturday, June 27, 2020 2:12 PM > > To: dev@dpdk.org; Honnappa Nagarahalli ; > > Ruifeng Wang ; jerinj@marvell.com; > > hemant.agrawal@nxp.com; Ajit Khaparde (ajit.khaparde@broadcom.com) > > ; igorch@amazon.com; > > thomas@monjalon.net; viacheslavo@mellanox.com; > > arybchenko@solarflare.com; bruce.richardson@intel.com > > Cc: nd > > Subject: [PATCH v2] eal: adjust barriers for IO on Armv8-a > > > > Change the barrier APIs for IO to reflect that Armv8-a is other-multi-copy > > atomicity memory model. > > > > Armv8-a memory model has been strengthened to require other-multi-copy > > atomicity. This property requires memory accesses from an observer to > > become visible to all other observers simultaneously [3]. This means > > > > a) A write arriving at an endpoint shared between multiple CPUs is > > visible to all CPUs > > b) A write that is visible to all CPUs is also visible to all other > > observers in the shareability domain > > > > This allows for using cheaper DMB instructions in the place of DSB for devices > > that are visible to all CPUs (i.e. devices that DPDK caters to). > > > > Please refer to [1], [2] and [3] for more information. > > > > [1] > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id > > =22ec71615d824f4f11d38d0e55a88d8956b7e45f > > [2] https://www.youtube.com/watch?v=i6DayghhA8Q > > [3] https://www.cl.cam.ac.uk/~pes20/armv8-mca/ > > > > Signed-off-by: Honnappa Nagarahalli > > Tested-by: Ruifeng Wang > > --- > > lib/librte_eal/arm/include/rte_atomic_64.h | 12 ++++++------ > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h > > b/lib/librte_eal/arm/include/rte_atomic_64.h > > index 7b7099cdc..e42f69edc 100644 > > --- a/lib/librte_eal/arm/include/rte_atomic_64.h > > +++ b/lib/librte_eal/arm/include/rte_atomic_64.h > > @@ -1,6 +1,6 @@ > > /* SPDX-License-Identifier: BSD-3-Clause > > * Copyright(c) 2015 Cavium, Inc > > - * Copyright(c) 2019 Arm Limited > > + * Copyright(c) 2020 Arm Limited > > */ > > > > #ifndef _RTE_ATOMIC_ARM64_H_ > > @@ -19,11 +19,11 @@ extern "C" { > > #include > > #include > > > > -#define rte_mb() asm volatile("dsb sy" : : : "memory") > > +#define rte_mb() asm volatile("dmb osh" : : : "memory") > > > > -#define rte_wmb() asm volatile("dsb st" : : : "memory") > > +#define rte_wmb() asm volatile("dmb oshst" : : : "memory") > > > > -#define rte_rmb() asm volatile("dsb ld" : : : "memory") > > +#define rte_rmb() asm volatile("dmb oshld" : : : "memory") > > > > #define rte_smp_mb() asm volatile("dmb ish" : : : "memory") > > > > @@ -37,9 +37,9 @@ extern "C" { > > > > #define rte_io_rmb() rte_rmb() > > > > -#define rte_cio_wmb() asm volatile("dmb oshst" : : : "memory") > > +#define rte_cio_wmb() rte_wmb() > > > > -#define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory") > > +#define rte_cio_rmb() rte_rmb() > > > > /*------------------------ 128 bit atomic operations -------------------------*/ > > > > -- > > 2.17.1 >