From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 843DCA0563; Tue, 10 Mar 2020 08:50:37 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5A9091C00E; Tue, 10 Mar 2020 08:50:37 +0100 (CET) Received: from mail-io1-f68.google.com (mail-io1-f68.google.com [209.85.166.68]) by dpdk.org (Postfix) with ESMTP id 2B3321BF96 for ; Tue, 10 Mar 2020 08:50:35 +0100 (CET) Received: by mail-io1-f68.google.com with SMTP id v3so5763309iom.13 for ; Tue, 10 Mar 2020 00:50:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ey1OSGTlCLeHrYK16+sD3dUfcXx2Sd9Vavgfg8w8ZXg=; b=Xrp3b1zo/7Uvo5nhLt8V9HtiCNh9s4EUBrtcl9uBPhHcO+rY82FzNVs+OymkkwTtOV LtW4RFrH/FaIXrIm7OS0r+kvKxUnnYLsWt3TU2873iywp8SRFd+KrBXGLcIxxq8fYso0 0U9iTxDGu7vY+u4cHBgWsiW2CRCM0/cQmSvmDZLHHfqoC8Oa67UABqyqYW+Ki2Qnh64X eE9JZk75GuHpTYOJ2X7HgHBGtw8xkJ1LBviZDnMpRB5k6SN/0ClDlJa5MajqS5hSO9X9 u21X3avvLWmk0lOFiQeLi1YBO5rioCSWxE3rr6YWW1XOFfFYhmM0E8xkFu8hfichQf1i TTtQ== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Mar 10, 2020 at 12:52 PM Linhaifeng wrote: > > > > > -----Original Message----- > > From: Gavin Hu [mailto:Gavin.Hu@arm.com] > > Sent: Tuesday, March 10, 2020 3:11 PM > > To: Linhaifeng ; dev@dpdk.org; > > thomas@monjalon.net > > Cc: chenchanghu ; xudingke > > ; Lilijun (Jerry) ; Honnappa > > Nagarahalli ; Steve Capper > > ; nd > > Subject: RE: [PATCH] cycles: add isb before read cntvct_el0 > > > > Hi Haifeng, > > > > > -----Original Message----- > > > From: dev On Behalf Of Linhaifeng > > > Sent: Monday, March 9, 2020 5:23 PM > > > To: dev@dpdk.org; thomas@monjalon.net > > > Cc: chenchanghu ; xudingke > > > ; Lilijun (Jerry) > > > Subject: [dpdk-dev] [PATCH] cycles: add isb before read cntvct_el0 > > > > > > We should use isb rather than dsb to sync system counter to cntvct_el0. > > > > > > Signed-off-by: Haifeng Lin > > > --- > > > lib/librte_eal/common/include/arch/arm/rte_atomic_64.h | 3 +++ > > > lib/librte_eal/common/include/arch/arm/rte_cycles_64.h | 2 ++ > > > 2 files changed, 5 insertions(+) > > > > > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > index 859ae129d..7e8049725 100644 > > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > @@ -21,6 +21,7 @@ extern "C" { > > > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define > > > dmb(opt) asm volatile("dmb " #opt : : : "memory") > > > +#define isb() asm volatile("isb" : : : "memory") > > > #define rte_mb() dsb(sy) > > > @@ -44,6 +45,8 @@ extern "C" { > > > #define rte_cio_rmb() dmb(oshld) > > > +#define rte_isb() isb() > > > + > > > /*------------------------ 128 bit atomic operations > > > -------------------------*/ #if defined(__ARM_FEATURE_ATOMICS) || > > > defined(RTE_ARM_FEATURE_ATOMICS) > > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > > b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > > index 68e7c7338..29f524901 100644 > > > --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > > +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > > @@ -18,6 +18,7 @@ extern "C" { > > > * The time base for this lcore. > > > */ > > > #ifndef RTE_ARM_EAL_RDTSC_USE_PMU > > > + > > > /** > > > * This call is portable to any ARMv8 architecture, however, typically > > > * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks. > > > @@ -27,6 +28,7 @@ rte_rdtsc(void) > > > { > > > uint64_t tsc; > > > + rte_isb(); > > Good catch, could you add a link to the commit log as a reference. > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/ar > > m64/include/asm/arch_timer.h?h=v5.5#n220 > > > > Ok. > > > > asm volatile("mrs %0, cntvct_el0" : "=r" (tsc)); > > In kernel, there is a call to arch_counter_enforce_ordering(cnt), maybe it is > > also necessary. > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/ar > > m64/include/asm/arch_timer.h?h=v5.5#n168 > > Should we add isb and arch_counter_enforce_ordering in rte_rdtsc or rte_rdtsc_precise? Only for rte_rdtsc_precise() as some cases would not need a barrier. rte_rdtsc_precise() created for this specific purpose. > > > > return tsc; > > > } > > > --