From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2FC45A04BC; Thu, 8 Oct 2020 10:55:00 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 041AB1BB40; Thu, 8 Oct 2020 10:54:59 +0200 (CEST) Received: from mail-il1-f193.google.com (mail-il1-f193.google.com [209.85.166.193]) by dpdk.org (Postfix) with ESMTP id 1F4AB1BACB for ; Thu, 8 Oct 2020 10:54:57 +0200 (CEST) Received: by mail-il1-f193.google.com with SMTP id r10so101225ilm.11 for ; Thu, 08 Oct 2020 01:54:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=hZpBc73IFxrlNg8uvpw7TE5Z65kZZgZRHP3/DF6QM8A=; b=DQKv1hil04QQg9jxL0GjcpuVGZzc52BUBCPl8RDd0shmJVLikWokECO0JxyPJtc04R ZLz99DXHpf5ibhrnJ4z93rWSUJL8MwTP8NVzJvBxIO5zn3ix+SoU/64sJWU0UOWFNZhC 944zk32ZxpkkZVdjmT1mifM8t35pn2pnMSAUIN7MgHcEa+4vxQrQsBhx4zyesWGaz8Rg riAtNNhMtyd3Hghwj+Czja9H2TQkdjX2+29r70JvQBklFIg3PJ82eWZvck7PSz23HDdp jQd7dyLQOV4jqvJfxxXIt+pjHKVwnxr+1skxbiA0ktLWI4JAu5lnqAhwQRM/mKNHjPv1 djbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=hZpBc73IFxrlNg8uvpw7TE5Z65kZZgZRHP3/DF6QM8A=; b=kLOHJ3Dx3k2hELv2ADnr7QNzn4+rE0Jz5g3hBfzMBdMi3brGFCBCbyFzoAEgd2mHAH gawBk5WopUIqy5v8Hj5BQfLbJPG4wmZPSMYzKaEfGdEhpC5Az3MofxyF3xxv+Ve8zaDF txhqL5yQuPc8Jzik9rLf6b8t4eYY35gMEQJ3bC2ggvyfiFbB7W1xRDxJ++XkiC4UelHB ikGMwhAKBTaRnWC1pxc1lWVLjH/k5EvP67BLEjrXGFa4Fo5b+QIFHtEwRt98NgSI/YT5 /EOp39/t3HlDOpRLR/cFyL4iuu5wggKqkGsZWGt8gb0wbkxxdi0V/x9veYzcKUAOHUka 7g9w== X-Gm-Message-State: AOAM533mK7LdYnB4cIvZHbe3GyRQcXUtAzT02ChdjO3OhmL0AO2p78oY qCMjAfoc7q6/833Q+/vWh6PDilyBFL8qKBbIDks= X-Google-Smtp-Source: ABdhPJy+WrFLZmKumu7KZTkWzhNJ1H+PoRDFA9PUHwjN0z718ftKyRJpP665+HpaOC01jfTUB8a9Q91RJevUhGFjSNY= X-Received: by 2002:a92:d7c4:: with SMTP id g4mr6012799ilq.162.1602147295469; Thu, 08 Oct 2020 01:54:55 -0700 (PDT) MIME-Version: 1.0 References: <20200911091919.62167-1-harry.van.haaren@intel.com> <20200914151021.23806-1-harry.van.haaren@intel.com> In-Reply-To: <20200914151021.23806-1-harry.van.haaren@intel.com> From: Jerin Jacob Date: Thu, 8 Oct 2020 14:24:39 +0530 Message-ID: To: Harry van Haaren Cc: dpdk-dev , Pavan Nikhilesh Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2] eal: add new prefetch write variants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Sep 14, 2020 at 8:39 PM Harry van Haaren wrote: > > This commit adds a new rte_prefetch0_write() variants, suggesting to the > compiler to use a prefetch instruction with intention to write. As a > compiler builtin, the compiler can choose based on compilation target > what the best implementation for this instruction is. > > Signed-off-by: Harry van Haaren > > --- > > v2: > - Add L1, L2, and L3 variants as ARM64 uarch supports them (Pavan) > > The integer constants passed to the builtin are not available as > a #define value, and doing #defines just for this write variant > does not seems a nice solution to me... particularly for those using > IDEs where any #define value is auto-hinted for code-completion. > --- > lib/librte_eal/include/generic/rte_prefetch.h | 49 +++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/lib/librte_eal/include/generic/rte_prefetch.h b/lib/librte_eal/include/generic/rte_prefetch.h > index 6e47bdfbad..3dfca77a74 100644 > --- a/lib/librte_eal/include/generic/rte_prefetch.h > +++ b/lib/librte_eal/include/generic/rte_prefetch.h > @@ -51,4 +51,53 @@ static inline void rte_prefetch2(const volatile void *p); > */ > static inline void rte_prefetch_non_temporal(const volatile void *p); > > +/** > + * Prefetch a cache line into all cache levels, with intention to write. This > + * prefetch variant hints to the CPU that the program is expecting to write to > + * the cache line being prefetched. > + * > + * @param p Address to prefetch > + */ > +static inline void rte_prefetch0_write(const void *p) Typically DPDK coding standards is to have static inline void rte_prefetch0_write(const void *p) vs static inline void rte_prefetch0_write(const void *p) Either way: Reviewed-by: Jerin Jacob > +{ > + /* 1 indicates intention to write, 3 sets target cache level to L1. See > + * GCC docs where these integer constants are described in more detail: > + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html > + */ > + __builtin_prefetch(p, 1, 3); > +} > + > +/** > + * Prefetch a cache line into all cache levels, except the 0th, with intention > + * to write. This prefetch variant hints to the CPU that the program is > + * expecting to write to the cache line being prefetched. > + * > + * @param p Address to prefetch > + */ > +static inline void rte_prefetch1_write(const void *p) > +{ > + /* 1 indicates intention to write, 2 sets target cache level to L2. See > + * GCC docs where these integer constants are described in more detail: > + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html > + */ > + __builtin_prefetch(p, 1, 2); > +} > + > +/** > + * Prefetch a cache line into all cache levels, except the 0th and 1st, with > + * intention to write. This prefetch variant hints to the CPU that the program > + * is expecting to write to the cache line being prefetched. > + * > + * @param p Address to prefetch > + */ > +static inline void rte_prefetch2_write(const void *p) > +{ > + /* 1 indicates intention to write, 1 sets target cache level to L3. See > + * GCC docs where these integer constants are described in more detail: > + * https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html > + */ > + __builtin_prefetch(p, 1, 1); > +} > + > + > #endif /* _RTE_PREFETCH_H_ */ > -- > 2.17.1 >