From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BFABC42CA0; Tue, 13 Jun 2023 08:57:09 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9ECCB40A8A; Tue, 13 Jun 2023 08:57:09 +0200 (CEST) Received: from mail-ua1-f46.google.com (mail-ua1-f46.google.com [209.85.222.46]) by mails.dpdk.org (Postfix) with ESMTP id 04C2D40698 for ; Tue, 13 Jun 2023 08:57:09 +0200 (CEST) Received: by mail-ua1-f46.google.com with SMTP id a1e0cc1a2514c-78676ca8435so444683241.1 for ; Mon, 12 Jun 2023 23:57:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686639428; x=1689231428; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Ad5Cc9NPS/Y9G5zVi6nVhZsRhui/hmg1iAGeBDip5XU=; b=bsoyRLTtxk8xGRTmZXT8ZNXpvsFC4mlT8e17ArUMVb587wzCE0fHO/w/TuMubL7rsy x8+Ne9A+pzHcuuXlJzo+w3VzyHzRfBtAGpRnr1hS8USc1AvMEMGqx+Vw0+yOIgN9oZS3 FGp8AXHMnxmJppY74plCsPvpiWL7HyAg6fUMqMIEVt3u6262B0ehtOF7T8YgPrjWNS31 LimxvIsigxeFHpPqM9S0yZR+9rhxg2bFfQYsC94nmVI9QOs0igkzwRiC85nH++QtpYsB HjT5C/JS5A7ZKx7mcg0gkBn2NQpny2WElPNerSdp65Ex11+qtSQSEVxCb16RevHApz1j lh3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686639428; x=1689231428; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ad5Cc9NPS/Y9G5zVi6nVhZsRhui/hmg1iAGeBDip5XU=; b=D9PUWH+w5PnZAB3zfGJw3DXNF4u/k/dovMJ6OdCoSESG1XndWYfmV/haGJo2zbiIOA ZE4wXjP/7SZg/vTZuXKS2WHlOlCyi0oKxfWqR+amzwJwyWyD99S2FAz8Idin7xHsfPoO pG2uNV9Se450+idbUTYA/m50oWSiZIMeR7qL7d9yIM7CHbLQrwFFzFG03IrFzoxVslk5 CvB+TyHLwLFvOdjkwoJbsGGnK8guXc5eUBr0CIkooiOaPEb0KDhYyoSnXqNgtw3SBiJM 3+/jN7gwvx/dcth369+XphmLOqgctIa7QxkOMIetzn22j26i3QPUUuYpXQ5407W0xzLh 38jA== X-Gm-Message-State: AC+VfDygbxsDCOtxL0N9nQTEth5mAENe8q0O3j5IqLLXHUigvT9lizcl +BSAJMxfeq374GVYwvYRPat5F+TIBYu4zsAstvDbLLxa1H+HQg== X-Google-Smtp-Source: ACHHUZ4Q/XHLQynacw+7Q9NMnznTH2VUCvifh+5w5UGY6nuvQ1LTD2eSJcxQjVw+QpXSl2CgyYiIe7+ESiXE0CpAB7E= X-Received: by 2002:a05:6102:4584:b0:439:55ed:226c with SMTP id dx4-20020a056102458400b0043955ed226cmr5159934vsb.14.1686639428221; Mon, 12 Jun 2023 23:57:08 -0700 (PDT) MIME-Version: 1.0 References: <20230606061249.833290-1-rbhansali@marvell.com> In-Reply-To: <20230606061249.833290-1-rbhansali@marvell.com> From: Jerin Jacob Date: Tue, 13 Jun 2023 12:26:41 +0530 Message-ID: Subject: Re: [PATCH] net/cnxk: add atomic fc check in poll mode Tx path To: Rahul Bhansali Cc: dev@dpdk.org, Nithin Kumar Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , jerinj@marvell.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Tue, Jun 6, 2023 at 11:43=E2=80=AFAM Rahul Bhansali wrote: > > Add a support of atomic fc check in poll mode Tx path. This atomic > check is useful if multiple threads are using the same Tx queue. > This will be enabled when Tx offload RTE_ETH_TX_OFFLOAD_MT_LOCKFREE > is set. > > Signed-off-by: Rahul Bhansali Updated the git commit as follows and applied to dpdk-next-net-mrvl/for-next-net. Thanks net/cnxk: improve Tx queue depth calculation Add a support of atomic flow control check in poll mode Tx path. This atomic check is useful if multiple threads are using the same Tx q= ueue. This will be enabled when Tx offload RTE_ETH_TX_OFFLOAD_MT_LOCKFREE is set. Signed-off-by: Rahul Bhansali > --- > drivers/net/cnxk/cn10k_ethdev.c | 3 ++ > drivers/net/cnxk/cn10k_rxtx.h | 1 + > drivers/net/cnxk/cn10k_tx.h | 61 ++++++++++++++++++++++++++------- > 3 files changed, 52 insertions(+), 13 deletions(-) > > diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_eth= dev.c > index 792c1b1970..4c4acc7cf0 100644 > --- a/drivers/net/cnxk/cn10k_ethdev.c > +++ b/drivers/net/cnxk/cn10k_ethdev.c > @@ -241,6 +241,9 @@ cn10k_nix_tx_queue_setup(struct rte_eth_dev *eth_dev,= uint16_t qid, > return rc; > } > > + /* Set Txq flag for MT_LOCKFREE */ > + txq->flag =3D !!(dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MT_LOCKFRE= E); > + > /* Store lmt base in tx queue for easy access */ > txq->lmt_base =3D nix->lmt_base; > txq->io_addr =3D sq->io_addr; > diff --git a/drivers/net/cnxk/cn10k_rxtx.h b/drivers/net/cnxk/cn10k_rxtx.= h > index 65dd57494a..b4287e2864 100644 > --- a/drivers/net/cnxk/cn10k_rxtx.h > +++ b/drivers/net/cnxk/cn10k_rxtx.h > @@ -51,6 +51,7 @@ struct cn10k_eth_txq { > rte_iova_t io_addr; > uint16_t sqes_per_sqb_log2; > int16_t nb_sqb_bufs_adj; > + uint8_t flag; > rte_iova_t cpt_io_addr; > uint64_t sa_base; > uint64_t *cpt_fc; > diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h > index 4f23a8dfc3..17793493cc 100644 > --- a/drivers/net/cnxk/cn10k_tx.h > +++ b/drivers/net/cnxk/cn10k_tx.h > @@ -47,6 +47,47 @@ > } = \ > } while (0) > > +#define NIX_XMIT_FC_OR_RETURN_MTS(txq, pkts) = \ > + do { = \ > + int64_t *fc_cache =3D &(txq)->fc_cache_pkts; = \ > + uint8_t retry_count =3D 8; = \ > + int64_t val, newval; = \ > + retry: = \ > + /* Reduce the cached count */ = \ > + val =3D (int64_t)__atomic_fetch_sub(fc_cache, pkts, __ATO= MIC_RELAXED); \ > + val -=3D pkts; = \ > + /* Cached value is low, Update the fc_cache_pkts */ = \ > + if (unlikely(val < 0)) { = \ > + /* Multiply with sqe_per_sqb to express in pkts *= / \ > + newval =3D txq->nb_sqb_bufs_adj - __atomic_load_n= (txq->fc_mem, \ > + _= _ATOMIC_RELAXED); \ > + newval =3D (newval << (txq)->sqes_per_sqb_log2) -= newval; \ > + newval -=3D pkts; = \ > + if (!__atomic_compare_exchange_n(fc_cache, &val, = newval, false, \ > + __ATOMIC_RELAXED= , __ATOMIC_RELAXED)) { \ > + if (retry_count) { = \ > + retry_count--; = \ > + goto retry; = \ > + } else = \ > + return 0; = \ > + } = \ > + /* Update and check it again for the room */ = \ > + if (unlikely(newval < 0)) = \ > + return 0; = \ > + } = \ > + } while (0) > + > +#define NIX_XMIT_FC_CHECK_RETURN(txq, pkts) = \ > + do { = \ > + if (unlikely((txq)->flag)) = \ > + NIX_XMIT_FC_OR_RETURN_MTS(txq, pkts); = \ > + else { = \ > + NIX_XMIT_FC_OR_RETURN(txq, pkts); = \ > + /* Reduce the cached count */ = \ > + txq->fc_cache_pkts -=3D pkts; = \ > + } = \ > + } while (0) > + > /* Encoded number of segments to number of dwords macro, each value of n= b_segs > * is encoded as 4bits. > */ > @@ -1174,11 +1215,9 @@ cn10k_nix_xmit_pkts(void *tx_queue, uint64_t *ws, = struct rte_mbuf **tx_pkts, > if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F && txq->tx_compl.ena) > handle_tx_completion_pkts(txq, flags & NIX_TX_VWQE_F); > > - if (!(flags & NIX_TX_VWQE_F)) { > - NIX_XMIT_FC_OR_RETURN(txq, pkts); > - /* Reduce the cached count */ > - txq->fc_cache_pkts -=3D pkts; > - } > + if (!(flags & NIX_TX_VWQE_F)) > + NIX_XMIT_FC_CHECK_RETURN(txq, pkts); > + > /* Get cmd skeleton */ > cn10k_nix_tx_skeleton(txq, cmd, flags, !(flags & NIX_TX_VWQE_F)); > > @@ -1323,11 +1362,9 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, uint64_t = *ws, > if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F && txq->tx_compl.ena) > handle_tx_completion_pkts(txq, flags & NIX_TX_VWQE_F); > > - if (!(flags & NIX_TX_VWQE_F)) { > - NIX_XMIT_FC_OR_RETURN(txq, pkts); > - /* Reduce the cached count */ > - txq->fc_cache_pkts -=3D pkts; > - } > + if (!(flags & NIX_TX_VWQE_F)) > + NIX_XMIT_FC_CHECK_RETURN(txq, pkts); > + > /* Get cmd skeleton */ > cn10k_nix_tx_skeleton(txq, cmd, flags, !(flags & NIX_TX_VWQE_F)); > > @@ -1879,11 +1916,9 @@ cn10k_nix_xmit_pkts_vector(void *tx_queue, uint64_= t *ws, > handle_tx_completion_pkts(txq, flags & NIX_TX_VWQE_F); > > if (!(flags & NIX_TX_VWQE_F)) { > - NIX_XMIT_FC_OR_RETURN(txq, pkts); > scalar =3D pkts & (NIX_DESCS_PER_LOOP - 1); > pkts =3D RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP); > - /* Reduce the cached count */ > - txq->fc_cache_pkts -=3D pkts; > + NIX_XMIT_FC_CHECK_RETURN(txq, pkts); > } else { > scalar =3D pkts & (NIX_DESCS_PER_LOOP - 1); > pkts =3D RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP); > -- > 2.25.1 >