From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1E9CCA04B5; Tue, 12 Jan 2021 05:39:10 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 63763140D02; Tue, 12 Jan 2021 05:39:09 +0100 (CET) Received: from mail-io1-f41.google.com (mail-io1-f41.google.com [209.85.166.41]) by mails.dpdk.org (Postfix) with ESMTP id 61A71140CFC; Tue, 12 Jan 2021 05:39:07 +0100 (CET) Received: by mail-io1-f41.google.com with SMTP id r9so1391557ioo.7; Mon, 11 Jan 2021 20:39:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=xF+jmuVzcEtmaChh0pdZdIu59PL68w2bSsR9oKIgCE0=; b=Zn9Dn0UcAbYKBzgt670HvryS3wFRHENXcyzwjOI3wtxK7jg0GpU8DMCzhFEQBRw6kp ht0HLY2SP5nkghkzoL5WCnZDZ9wS/N5hOFq8vx4ItuICcesAjWT3liz3ANVnTzRt9KCp MMgA8eOst25RyO+MTf7btIAAfRpqNuYyXIUZGTGmRUGBWO+nVlSXnhpw5CoROmZCbomJ gJYWI05UUSb65NGIaW+dkPgSyntribEEOiTEuIcUtFBVVA4GfktBCdTKOsAVptgdiNYD qNbAcRigvdsTd0ifSzsQHtA3VThEElqySs6SpuCgrsyJU1SSFWppVfkiOdWj3/loRO8U xVHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=xF+jmuVzcEtmaChh0pdZdIu59PL68w2bSsR9oKIgCE0=; b=tdn7qKh4YUTdbkkcHzDkhcUj4cnYhW4H9+8a4SJWGKT9Zg6qcscoQgyzf/i036z1QB CF5qKedSprPW+m/i6/JPIXtpmmjxfheYZXcvsYihR+tE3AoYseFahYjqPfEc1UjBWPuZ 7kN6bF1vndHEEbY6RWY4ezjEIdGZpRGreDPiI7BwgwBEIZ1s+f4YufPK9fwc1W7cAVOl w+fAk4grGsjPAGIv4QIo/tJRAb+OcCYl4fV8+11Y2ST8Dc08l9hKbO5W+VWKaOr6TiZY mkrqPXGJwOFk0e7dGVurWkoy8Zt4MY+jvEtTI9Tzp1nH3S+MbThiS1c1hYWTawcgbGPq GMPg== X-Gm-Message-State: AOAM5339bYyLAfqKHpYLb0EulVvyC++EI9sOL+ILm96zVmsvV8Ba3sIf lZtf4MScGePG6mCjhunhI5ZXQRNg14lLIacyTNE= X-Google-Smtp-Source: ABdhPJx/VAUAocVKukF0tyDQO0HTD9jOItQJiXiG9ctLjK1ho/c5+QSAFq4V1pSOkVuVPeLOnjkWFLeQudN0ZVuXuBg= X-Received: by 2002:a5d:959a:: with SMTP id a26mr1982429ioo.94.1610426346659; Mon, 11 Jan 2021 20:39:06 -0800 (PST) MIME-Version: 1.0 References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210112025709.1121523-1-ruifeng.wang@arm.com> <20210112025709.1121523-5-ruifeng.wang@arm.com> In-Reply-To: <20210112025709.1121523-5-ruifeng.wang@arm.com> From: Jerin Jacob Date: Tue, 12 Jan 2021 10:08:50 +0530 Message-ID: To: Ruifeng Wang Cc: Jerin Jacob , Nithin Dabilpuram , Pavan Nikhilesh , dpdk-dev , Vladimir Medvedkin , Hemant Agrawal , Honnappa Nagarahalli , nd , dpdk stable Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v3 4/5] common/octeontx2: fix build with sve enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Jan 12, 2021 at 8:28 AM Ruifeng Wang wrote: > > Building with gcc 10.2 with SVE extension enabled got error: > > {standard input}: Assembler messages: > {standard input}:4002: Error: selected processor does not support `mov z3.b,#0' > {standard input}:4003: Error: selected processor does not support `whilelo p1.b,xzr,x7' > {standard input}:4005: Error: selected processor does not support `ld1b z0.b,p1/z,[x8]' > {standard input}:4006: Error: selected processor does not support `whilelo p4.s,wzr,w7' > > This is because inline assembly code explicitly resets cpu model to > not have SVE support. Thus SVE instructions generated by compiler > auto vectorization got rejected by assembler. > > Added SVE to the cpu model specified by inline assembly for SVE support. > Not replacing the inline assembly with C atomics because the driver relies > on specific LSE instruction to interface to co-processor [1]. > > Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs") > Cc: jerinj@marvell.com > Cc: stable@dpdk.org Reviewed-by: Jerin Jacob > > [1] https://mails.dpdk.org/archives/dev/2021-January/196092.html > > Signed-off-by: Ruifeng Wang > --- > v3: > Keep inline assembly and add sve extension to fix issue. (Pavan) > > drivers/common/octeontx2/otx2_io_arm64.h | 15 +++++++++++---- > 1 file changed, 11 insertions(+), 4 deletions(-) > > diff --git a/drivers/common/octeontx2/otx2_io_arm64.h b/drivers/common/octeontx2/otx2_io_arm64.h > index b5c85d9a6..34268e3af 100644 > --- a/drivers/common/octeontx2/otx2_io_arm64.h > +++ b/drivers/common/octeontx2/otx2_io_arm64.h > @@ -21,6 +21,12 @@ > #define otx2_prefetch_store_keep(ptr) ({\ > asm volatile("prfm pstl1keep, [%x0]\n" : : "r" (ptr)); }) > > +#if defined(__ARM_FEATURE_SVE) > +#define __LSE_PREAMBLE " .cpu generic+lse+sve\n" > +#else > +#define __LSE_PREAMBLE " .cpu generic+lse\n" > +#endif > + > static __rte_always_inline uint64_t > otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr) > { > @@ -28,7 +34,7 @@ otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr) > > /* Atomic add with no ordering */ > asm volatile ( > - ".cpu generic+lse\n" > + __LSE_PREAMBLE > "ldadd %x[i], %x[r], [%[b]]" > : [r] "=r" (result), "+m" (*ptr) > : [i] "r" (incr), [b] "r" (ptr) > @@ -43,7 +49,7 @@ otx2_atomic64_add_sync(int64_t incr, int64_t *ptr) > > /* Atomic add with ordering */ > asm volatile ( > - ".cpu generic+lse\n" > + __LSE_PREAMBLE > "ldadda %x[i], %x[r], [%[b]]" > : [r] "=r" (result), "+m" (*ptr) > : [i] "r" (incr), [b] "r" (ptr) > @@ -57,7 +63,7 @@ otx2_lmt_submit(rte_iova_t io_address) > uint64_t result; > > asm volatile ( > - ".cpu generic+lse\n" > + __LSE_PREAMBLE > "ldeor xzr,%x[rf],[%[rs]]" : > [rf] "=r"(result): [rs] "r"(io_address)); > return result; > @@ -69,7 +75,7 @@ otx2_lmt_submit_release(rte_iova_t io_address) > uint64_t result; > > asm volatile ( > - ".cpu generic+lse\n" > + __LSE_PREAMBLE > "ldeorl xzr,%x[rf],[%[rs]]" : > [rf] "=r"(result) : [rs] "r"(io_address)); > return result; > @@ -104,4 +110,5 @@ otx2_lmt_mov_seg(void *out, const void *in, const uint16_t segdw) > dst128[i] = src128[i]; > } > > +#undef __LSE_PREAMBLE > #endif /* _OTX2_IO_ARM64_H_ */ > -- > 2.25.1 >