From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 44EBDA04B5; Mon, 11 Jan 2021 04:09:27 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B41D3140CA4; Mon, 11 Jan 2021 04:09:26 +0100 (CET) Received: from mail-io1-f53.google.com (mail-io1-f53.google.com [209.85.166.53]) by mails.dpdk.org (Postfix) with ESMTP id 53780140C9E for ; Mon, 11 Jan 2021 04:09:25 +0100 (CET) Received: by mail-io1-f53.google.com with SMTP id i18so16441908ioa.1 for ; Sun, 10 Jan 2021 19:09:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=AUOqU6khc2p45I0WXa64n53718sJdV96vGfTYyaBBh0=; b=MTgKJpsW0tdrYcT75/JV9urws+4XpSKibfKoCtvmq2LBRq1ITVEeD7CtxQslP4EtoB wi1J3s+IaP7zGNhgSFExsNqspSp4+VOD5ynFo7RN3ZIPljhLYafi8V3SXhSAVVzZgNKB QJFNmBsusPShvB8PPSbA4LhgWBWEzJBs6BpVr/Jv+pHffJpPC6W9a/+/CxCEvPXLBtT4 4MX7BPjscv+m4GEInYh2slHle/V7kZTgU3/hFzNvwoNgef4dPVoOeOjSyOrCgnxEUyWA jEhuxeY3I+Bl/OjgXac+b43Yn8fDj/Mo9wj0Hm+H5ppy6KY2YqPAVyGMHIByBjXR6P6I hvGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=AUOqU6khc2p45I0WXa64n53718sJdV96vGfTYyaBBh0=; b=d9wn+ggLdwFKzIfutoZ4icRsS9EJtnlx43IGi20e2Hs0mvCKxDw3QDHO0IFw/aGK+a fmy5SysFFN7hsLj/QtVp7wwSL2ha77VRDbtyNA6RU4rpWlkBfmb07DdYQZ0szuxwSts4 v5rUK5nHFzKGzdiUAa5+WyNxu+PZ1JP2mw7/4VUWXvbziKz0IxUY42T+Zvc/WjeS13vX OyyDvNQwHysZpI5npDwLLBFXkYfNx9m3x3VpETivAgmjX2c8qzW4aPHRjRiq+EPzfpqZ PrjtEPa+s9TggYcaSHCclH6LgVNcfyndISymSPZhzLQr8NYieFF4HsMtHjbqftyFrz7E 5vOw== X-Gm-Message-State: AOAM5320GRYgMk8oR0zWH3OwxDdN0qEAu/X/o6cE8hvcg1rEPLNfEbfU +cESfGEHhZSR70MaCyw+OwzyQrdpzf7rrbwHZk4= X-Google-Smtp-Source: ABdhPJw0lu+2hWdaohEcO9TlS8whWnDBfo2UP/a2CBi5hW3ecFWAxcuyg5P+8kuImA02xShq4qKjll6tx9N6wu/AJkc= X-Received: by 2002:a5d:959a:: with SMTP id a26mr13629808ioo.94.1610334564532; Sun, 10 Jan 2021 19:09:24 -0800 (PST) MIME-Version: 1.0 References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210108082523.1062058-1-ruifeng.wang@arm.com> <20210108082523.1062058-6-ruifeng.wang@arm.com> In-Reply-To: From: Jerin Jacob Date: Mon, 11 Jan 2021 08:39:08 +0530 Message-ID: To: Ruifeng Wang Cc: Honnappa Nagarahalli , "jerinj@marvell.com" , Jan Viktorin , Bruce Richardson , "dev@dpdk.org" , "vladimir.medvedkin@intel.com" , "hemant.agrawal@nxp.com" , nd Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2 5/5] config: add Arm Neoverse N2 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Jan 11, 2021 at 8:31 AM Ruifeng Wang wrote: > > > > -----Original Message----- > > From: Honnappa Nagarahalli > > Sent: Saturday, January 9, 2021 7:58 AM > > To: Ruifeng Wang ; jerinj@marvell.com; Ruifeng > > Wang ; Jan Viktorin ; > > Bruce Richardson > > Cc: dev@dpdk.org; vladimir.medvedkin@intel.com; > > hemant.agrawal@nxp.com; nd ; Honnappa Nagarahalli > > ; nd > > Subject: RE: [PATCH v2 5/5] config: add Arm Neoverse N2 > > > > + Juraj > > > > Please note that this clashes with Juraj's patch for meson rework. > > Yes. I didn't base it on the build options rework series. > I will rebase when that series got merged. > > > > > > > > > > > > Add Arm Neoverse N2 cpu support. > > > > > > Signed-off-by: Ruifeng Wang > > > --- > > > config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++ > > > config/arm/meson.build | 11 ++++++++++- > > > 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 > > > config/arm/arm64_n2_linux_gcc > > > > > > diff --git a/config/arm/arm64_n2_linux_gcc > > > b/config/arm/arm64_n2_linux_gcc new file mode 100644 index > > > 000000000..78f6f3e2b > > > --- /dev/null > > > +++ b/config/arm/arm64_n2_linux_gcc > > > @@ -0,0 +1,17 @@ > > > +[binaries] > > > +c = 'aarch64-linux-gnu-gcc' > > > +cpp = 'aarch64-linux-gnu-cpp' > > > +ar = 'aarch64-linux-gnu-gcc-ar' > > > +strip = 'aarch64-linux-gnu-strip' > > > +pkgconfig = 'aarch64-linux-gnu-pkg-config' > > > +pcap-config = '' > > > + > > > +[host_machine] > > > +system = 'linux' > > > +cpu_family = 'aarch64' > > > +cpu = 'armv8-a' > > > +endian = 'little' > > > + > > > +[properties] > > > +implementor_id = '0x41' > > > +implementor_pn = '0xd49' > > > diff --git a/config/arm/meson.build b/config/arm/meson.build index > > > 42b4e43c7..58e0ae643 100644 > > > --- a/config/arm/meson.build > > > +++ b/config/arm/meson.build > > > @@ -89,6 +89,14 @@ flags_n1generic_extra = [ > > > ['RTE_MAX_NUMA_NODES', 1], > > > ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], > > > ['RTE_LIBRTE_VHOST_NUMA', false]] > > > +flags_n2generic_extra = [ > > > + ['RTE_MACHINE', '"neoverse-n2"'], > > > + ['RTE_MAX_LCORE', 64], > > > + ['RTE_CACHE_LINE_SIZE', 64], > > > + ['RTE_ARM_FEATURE_ATOMICS', true], > > > + ['RTE_USE_C11_MEM_MODEL', true], > > > + ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], > > > + ['RTE_LIBRTE_VHOST_NUMA', false]] > > Do we need a flag RTE_ARM_FEATURE_SVE? > > I don't think extra flag is needed. We can rely on __ARM_FEATURE_SVE from compiler. > One scenario I can think of where RTE_ARM_FEATURE_SVE can be needed is, when we are > writing inline assembly with sve instructions and using compiler that has no sve support. > I'm not sure we will have sve inline assembly as C intrinsics are available. It may be useful to introduce RTE_ARM_FEATURE_SVE to abstract any compiler difference in future(GCC vs clang or another tool chain etc). > > > > > > > > machine_args_generic = [ > > > ['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -100,7 > > > +108,8 @@ machine_args_generic = [ > > > ['0xd09', ['-mcpu=cortex-a73']], > > > ['0xd0a', ['-mcpu=cortex-a75']], > > > ['0xd0b', ['-mcpu=cortex-a76']], > > > - ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], > > > flags_n1generic_extra]] > > > + ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], > > > flags_n1generic_extra], > > > + ['0xd49', ['-march=armv8.5-a+crypto+sve'], flags_n2generic_extra]] > > Should this be 'sve2'? There should be a flag to indicate SVE2. > > Yes. N2 supports sve2 and sve2 is superset of sve. > I will do the change in next version. > > > > > > > > machine_args_cavium = [ > > > ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], > > > -- > > > 2.25.1 >