From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 944CCA09D3; Thu, 12 Nov 2020 17:37:47 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 73F48592B; Thu, 12 Nov 2020 17:37:46 +0100 (CET) Received: from mail-io1-f67.google.com (mail-io1-f67.google.com [209.85.166.67]) by dpdk.org (Postfix) with ESMTP id 373B3569B; Thu, 12 Nov 2020 17:37:44 +0100 (CET) Received: by mail-io1-f67.google.com with SMTP id u21so6652289iol.12; Thu, 12 Nov 2020 08:37:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=IN3fJ/7srk+1NZ0lQTh8mb99vsEMGfoBPYTOk8P5uEU=; b=ZNqO0km3zR/u+jB5AxXOU4yfemFY61jdxTUwFseHA0zK6JqBbtMkPyZvxAQLtwUSns RiEnTVJbEry1UuxEu1VHvsYp7Hxihtjm719ORMuRf0s+h4BLjVhxr/x3QlgpruDeqnBH FggLKm2ZzceqngCRZQ9Kl9iiwmKSK+isJT7VO38NkhpIu4HoUwxtUbJERyd9okSNhDwE mnLlKEtW26hpWlmoQFUQZT6j1iS88sHggpyVxVi9hDmtJwvSpbtRcateKMlDdUjWXgn/ GidscukV29+8DyXdMpIdt29EteSpMjjx7loLjsuCQ76RYTEzXLm5tloLRhBucTlY/e1v eMAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=IN3fJ/7srk+1NZ0lQTh8mb99vsEMGfoBPYTOk8P5uEU=; b=Mg6Y/WD1GUAYEhhUOaeWHtmeeCh++2Lcu2vBXTApOFxMwQtt5EsXJ0z82ozitv0uB8 wFVzcvvIf6Kc/lckmz2IO6C4G9l72QAymFRsNA4EiVYClqbqZEi4VUQy4vZE9s0yAPK3 T/EP045OLgALV9pUSjbKQtmdm0OgFzfuUyggBx/QBRz9LotK0Q3BKgDD2ilV/uBJdvXE uFKigDu22oVuz7F+jWuCYhsBxeyhkv5eIBYFDEczJn0lg7v6QvGqLvma3PCk98KK5BqU rXDK0K/9+w3ZeqQH+zer4M6bqQmxHs0eGTTaHYmz2YDiaXcf8sSpkXVUrJeEcS+fSfrU 7anQ== X-Gm-Message-State: AOAM5330gRfuDu3aSAPcoflJW5uwZGy/ZtbmMBmUJJGUxUA1OKjA8EZ2 SiX9swQefBRkuTi9ae596bHrDxRMimDGaZGOsTM= X-Google-Smtp-Source: ABdhPJzWRA3+nAtgHei97sWeTxCNWs1qRYe6HYFki2Qh6f30pmVSbgKsofCKkQEp6PMLNzrtSBFTpsOIK24pjZkQ3Ec= X-Received: by 2002:a6b:5805:: with SMTP id m5mr23311029iob.1.1605199063462; Thu, 12 Nov 2020 08:37:43 -0800 (PST) MIME-Version: 1.0 References: <20201112103157.53486-1-ruifeng.wang@arm.com> In-Reply-To: <20201112103157.53486-1-ruifeng.wang@arm.com> From: Jerin Jacob Date: Thu, 12 Nov 2020 22:07:27 +0530 Message-ID: To: Ruifeng Wang Cc: Jerin Jacob , David Marchand , Honnappa Nagarahalli , Phil Yang , dpdk-dev , nd , dpdk stable Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v1] eal/arm: fix clang build of native target X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Thu, Nov 12, 2020 at 4:02 PM Ruifeng Wang wrote: > > When doing Clang build with '-mcpu=native' on N1 platform, build failed > with: > ../lib/librte_eal/arm/include/rte_atomic_64.h:76:39: > error: instruction requires: lse > __ATOMIC128_CAS_OP(__cas_128_release, "caspl") > > This is because native detection for Neoverse N1 was added in Clang-11. > Prior version of Clang's assembler doesn't know LSE support on hardware. > Fixed this for Clang earlier than version 11 by specifying architecture > for assembler. > Referred to [1] for this fix. > > Fixes: 7e2c3e17fe2c ("eal/arm64: add 128-bit atomic compare exchange") > Cc: stable@dpdk.org > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e0d5896bd356cd577f9710a02d7a474cdf58426b > > Signed-off-by: Ruifeng Wang Reviewed-by: Jerin Jacob > --- > lib/librte_eal/arm/include/rte_atomic_64.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h > index 2cef88629..7fcd17466 100644 > --- a/lib/librte_eal/arm/include/rte_atomic_64.h > +++ b/lib/librte_eal/arm/include/rte_atomic_64.h > @@ -46,6 +46,8 @@ rte_atomic_thread_fence(int memorder) > /*------------------------ 128 bit atomic operations -------------------------*/ > > #if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS) > +#define __LSE_PREAMBLE ".arch armv8-a+lse\n" > + > #define __ATOMIC128_CAS_OP(cas_op_name, op_string) \ > static __rte_noinline rte_int128_t \ > cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated) \ > @@ -59,6 +61,7 @@ cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated) \ > register uint64_t x2 __asm("x2") = (uint64_t)updated.val[0]; \ > register uint64_t x3 __asm("x3") = (uint64_t)updated.val[1]; \ > asm volatile( \ > + __LSE_PREAMBLE \ > op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]" \ > : [old0] "+r" (x0), \ > [old1] "+r" (x1) \ > @@ -76,6 +79,7 @@ __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa") > __ATOMIC128_CAS_OP(__cas_128_release, "caspl") > __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal") > > +#undef __LSE_PREAMBLE > #undef __ATOMIC128_CAS_OP > > #endif > -- > 2.20.1 >