From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66EC5A0C51; Thu, 10 Jun 2021 08:22:08 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 09BB44067C; Thu, 10 Jun 2021 08:22:08 +0200 (CEST) Received: from mail-io1-f44.google.com (mail-io1-f44.google.com [209.85.166.44]) by mails.dpdk.org (Postfix) with ESMTP id 989164003C for ; Thu, 10 Jun 2021 08:22:07 +0200 (CEST) Received: by mail-io1-f44.google.com with SMTP id k5so15766719iow.12 for ; Wed, 09 Jun 2021 23:22:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=XMDvhXvgZ0JaFFhfJcX5hNY5PSw1mwUgIqkY9ODltuk=; b=ji4Qh13ULHZey5xiiXR68oalbdstr7lVpwyVVJ3960o4HoR/Auz2l+iLGvx6ELrqkt iArtP7eW05j6XzEC7oEHVxGn24MMGfte2YNWbqTm8LAwQrP6oMuNcviRymNowCyAe2kX YNbDmaZnj8693PR5wvBboQ0jR5ZmGgYvHX44tgzbcdGcpYJ1iXFmocUxfbZndfkREHWl doEeW6wmJccdZKgZJFuIF8/fk45rHPZ9sZ+Ji7sJ/t6Sd2TMsZnsJ05y9Ie1JBX6ZU2m CVLaEaMKPNSeO+qJFF7+gL8a+p/Y2LeEs2xpIoCnn4fE11734xMkFAjt085AvtnxbSf6 QNfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=XMDvhXvgZ0JaFFhfJcX5hNY5PSw1mwUgIqkY9ODltuk=; b=tnLYr0bu/wVw3W2UE/fKV+j5i6PXH4nQblQXHJmx3GiKMMLzZdVsZsXDpJq0PBduMh NxWs8oPoDPkUd3GPSSivl54FF5pQhRbUwaDtsfsdt5VRChfuMUu/aRy117lQUG/w65bQ PVx+6nqObof5xcRAyewv7VFEEnIee++YYAOHvdL8yb8DZqTxA0iPO0taYCxPtR1ZrfYx S8oGxyNmLoDcHZiSw14OayDBA29KyKIKIeQkyzYu0xrahuHKlbugkMpTSu29S9jk1aKd p9EW3GWze90uxzpwEzgRU/GHTu2dzDN0lSLi+RGsu79PH8LSpuuj/T8wDcOYaptvXjAg 8Bfw== X-Gm-Message-State: AOAM533a0XlC/c3SCSfx6ex0+mBpG3xPgC2U74wMFFS30Os/Alaoi7XU tnLrF2lp/CffCQ8sX1tNfUTEJnpfGee1q6w/zLg= X-Google-Smtp-Source: ABdhPJwSPVks5FpWw2TpTEEw0OXFCgpj59min/SvzHpM5avh1Zwt7FDgxtgvQjSsorxujzqloPP7i8rfig8wKJ6ygWU= X-Received: by 2002:a6b:3e88:: with SMTP id l130mr2557592ioa.59.1623306126896; Wed, 09 Jun 2021 23:22:06 -0700 (PDT) MIME-Version: 1.0 References: <20210531214142.30167-1-tduszynski@marvell.com> <20210531214142.30167-7-tduszynski@marvell.com> In-Reply-To: <20210531214142.30167-7-tduszynski@marvell.com> From: Jerin Jacob Date: Thu, 10 Jun 2021 11:51:51 +0530 Message-ID: To: Tomasz Duszynski Cc: dpdk-dev , jpalider@marvell.com, Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH 06/28] common/cnxk: add support for setting link mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Jun 1, 2021 at 3:12 AM Tomasz Duszynski wrote: > > Add support for setting link mode. > > Signed-off-by: Tomasz Duszynski > Signed-off-by: Jakub Palider > --- > drivers/common/cnxk/roc_bphy_cgx.c | 28 ++++++++++++ > drivers/common/cnxk/roc_bphy_cgx.h | 11 +++++ > drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +++++++++++++++++++++++++ > drivers/common/cnxk/version.map | 1 + > 4 files changed, 101 insertions(+) > > diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c > index dbdaddcd0..930057bb0 100644 > --- a/drivers/common/cnxk/roc_bphy_cgx.c > +++ b/drivers/common/cnxk/roc_bphy_cgx.c > @@ -283,6 +283,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, > return 0; > } > > +int > +roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, > + struct roc_bphy_cgx_link_mode *mode) > +{ > + uint64_t scr1, scr0; > + > + if (roc_model_is_cn10k()) > + return -ENOTSUP; > + > + if (!roc_cgx) > + return -EINVAL; > + > + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) > + return -EINVAL; -ENODEV? Access the series, please attempt to have proper return value if possible. > + > + if (!mode) > + return -EINVAL; > + > + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) | > + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) | > + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) | > + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) | > + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) | > + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode)); > + > + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); > +} > + > int > roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) > { > diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h > index a5e18565d..f68ddfcc9 100644 > --- a/drivers/common/cnxk/roc_bphy_cgx.h > +++ b/drivers/common/cnxk/roc_bphy_cgx.h > @@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode { > __MAX_ROC_BPHY_CGX_ETH_LINK_MODE > }; > > +struct roc_bphy_cgx_link_mode { > + bool full_duplex; > + bool an; > + unsigned int port; > + enum roc_bphy_cgx_eth_link_speed speed; > + enum roc_bphy_cgx_eth_link_mode mode; > +}; > + > struct roc_bphy_cgx_link_info { > bool link_up; > bool full_duplex; > @@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); > __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, > unsigned int lmac, > struct roc_bphy_cgx_link_info *info); > +__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, > + unsigned int lmac, > + struct roc_bphy_cgx_link_mode *mode); > __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, > unsigned int lmac); > __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, > diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h > index 4e86ae4ea..ee7578423 100644 > --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h > +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h > @@ -5,10 +5,64 @@ > #ifndef _ROC_BPHY_CGX_PRIV_H_ > #define _ROC_BPHY_CGX_PRIV_H_ > > +/* LINK speed types */ > +enum eth_link_speed { > + ETH_LINK_NONE, > + ETH_LINK_10M, > + ETH_LINK_100M, > + ETH_LINK_1G, > + ETH_LINK_2HG, /* 2.5 Gbps */ > + ETH_LINK_5G, > + ETH_LINK_10G, > + ETH_LINK_20G, > + ETH_LINK_25G, > + ETH_LINK_40G, > + ETH_LINK_50G, > + ETH_LINK_80G, > + ETH_LINK_100G, > + ETH_LINK_MAX, > +}; > + > +/* Supported LINK MODE enums > + * Each link mode is a bit mask of these > + * enums which are represented as bits > + */ > +enum eth_mode { > + ETH_MODE_SGMII_BIT = 0, > + ETH_MODE_1000_BASEX_BIT, > + ETH_MODE_QSGMII_BIT, > + ETH_MODE_10G_C2C_BIT, > + ETH_MODE_10G_C2M_BIT, > + ETH_MODE_10G_KR_BIT, /* = 5 */ > + ETH_MODE_20G_C2C_BIT, > + ETH_MODE_25G_C2C_BIT, > + ETH_MODE_25G_C2M_BIT, > + ETH_MODE_25G_2_C2C_BIT, > + ETH_MODE_25G_CR_BIT, /* = 10 */ > + ETH_MODE_25G_KR_BIT, > + ETH_MODE_40G_C2C_BIT, > + ETH_MODE_40G_C2M_BIT, > + ETH_MODE_40G_CR4_BIT, > + ETH_MODE_40G_KR4_BIT, /* = 15 */ > + ETH_MODE_40GAUI_C2C_BIT, > + ETH_MODE_50G_C2C_BIT, > + ETH_MODE_50G_C2M_BIT, > + ETH_MODE_50G_4_C2C_BIT, > + ETH_MODE_50G_CR_BIT, /* = 20 */ > + ETH_MODE_50G_KR_BIT, > + ETH_MODE_80GAUI_C2C_BIT, > + ETH_MODE_100G_C2C_BIT, > + ETH_MODE_100G_C2M_BIT, > + ETH_MODE_100G_CR4_BIT, /* = 25 */ > + ETH_MODE_100G_KR4_BIT, > + ETH_MODE_MAX_BIT /* = 27 */ > +}; > + > /* REQUEST ID types. Input to firmware */ > enum eth_cmd_id { > ETH_CMD_GET_LINK_STS = 4, > ETH_CMD_INTERNAL_LBK = 7, > + ETH_CMD_MODE_CHANGE = 11, /* hot plug support */ > ETH_CMD_INTF_SHUTDOWN = 12, > ETH_CMD_SET_PTP_MODE = 34, > }; > @@ -63,6 +117,13 @@ enum eth_cmd_own { > /* struct eth_ctl_args */ > #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8) > > +/* struct eth_mode_change_args */ > +#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8) > +#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12) > +#define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13) > +#define SCR1_ETH_MODE_CHANGE_ARGS_PORT GENMASK_ULL(21, 14) > +#define SCR1_ETH_MODE_CHANGE_ARGS_MODE GENMASK_ULL(63, 22) > + > #define SCR1_OWN_STATUS GENMASK_ULL(1, 0) > > #endif /* _ROC_BPHY_CGX_PRIV_H_ */ > diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map > index 205a0602b..15a6d3a3b 100644 > --- a/drivers/common/cnxk/version.map > +++ b/drivers/common/cnxk/version.map > @@ -16,6 +16,7 @@ INTERNAL { > roc_bphy_cgx_intlbk_enable; > roc_bphy_cgx_ptp_rx_disable; > roc_bphy_cgx_ptp_rx_enable; > + roc_bphy_cgx_set_link_mode; > roc_clk_freq_get; > roc_error_msg_get; > roc_idev_lmt_base_addr_get; > -- > 2.25.1 >