From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A6F5F4240F; Wed, 18 Jan 2023 16:06:32 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 55C2D40223; Wed, 18 Jan 2023 16:06:32 +0100 (CET) Received: from mail-vs1-f53.google.com (mail-vs1-f53.google.com [209.85.217.53]) by mails.dpdk.org (Postfix) with ESMTP id 7DD52400D6 for ; Wed, 18 Jan 2023 16:06:31 +0100 (CET) Received: by mail-vs1-f53.google.com with SMTP id k4so35989397vsc.4 for ; Wed, 18 Jan 2023 07:06:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Vvcuh6QPZcM3ItzKzYnXPPc8nM6gqPZmMcdoPpT5QOM=; b=o0MXhTP3BUHLUOEY+evtUbZ/4LOKaEOIG57aTNz4VZekGolfH+voTro4wu3Gy5P3xK HXfeAdqgbRZdLUgxQOB+i2B3PGA69CWizTDtTHT22zeR+Zhg9oFC+//xswSDhwmLZsLn GAQxtMTMx0lZXCK+AQzZwyKCPc+Sr8Vy9zjwEpZzhYERkaF4zSpj7plwvpqI0SQJL8I/ zU4Jjw0emTMXN5KrrLS746Wn6EiuaU4FxGaoD+gqxc8Zhi2k3iKw9UER+NPmkzXv74jL v0vZaiLGX/rpTyVkb28WmauPDdCw39qy6zaegUWpjtkaCcLDnKme/WnVU5nOHcJxT7vs bXTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Vvcuh6QPZcM3ItzKzYnXPPc8nM6gqPZmMcdoPpT5QOM=; b=PRzKN2fcDC+hleNa0UoigcpGB5YbSVr2YJgAva++4LNo6CydhhPpmRPI5EjwG4AGUk fyXC+hBR4XCZyQd3iO0IcAEB4dTuyt6NUWk4GJLaEj7SZI1dU5w5T7qbMNp0ZHzYD03O +hM2Nuy76mQgi10ALzrkRiT45JTuA3X3V0HKvh4EG2W05cSlJLp3xT/kx4SWa71sHSHY QO71VOjMHBBSnD/pj6kBkp2Dn0lqQhKY+81cS7ncpQGtnBsaYQiTNG7D6FydAtW5/2A2 RqDVUy25QfckwbNwipQJOl4/T0WdoVwPdZVyXld0JIsugIRQzplM920Y548dUZBxgQZv hV3g== X-Gm-Message-State: AFqh2kopOAHh4Avsrrh6hwvnHT2b4HggLFY3O3kd4X5JrFvgJhXfDHD5 sSFf2P79nmvbgrVNxj/ItAC0W/yVIG9CkwR6uNQ= X-Google-Smtp-Source: AMrXdXsjEaCkLuuQklaRiBrxbIuO3ZVL2cXjY5jMzxIXYU7xWxEOPzD/60ostIRlMrGRf/4ELNfq3j/kWAFrYu4nk2w= X-Received: by 2002:a67:b64b:0:b0:3d0:c96e:25ac with SMTP id e11-20020a67b64b000000b003d0c96e25acmr903803vsm.73.1674054390698; Wed, 18 Jan 2023 07:06:30 -0800 (PST) MIME-Version: 1.0 References: <20221209134121.1757306-1-rbhansali@marvell.com> In-Reply-To: <20221209134121.1757306-1-rbhansali@marvell.com> From: Jerin Jacob Date: Wed, 18 Jan 2023 20:36:04 +0530 Message-ID: Subject: Re: [PATCH] event/cnxk: wait for CPT fc on wqe path To: Rahul Bhansali Cc: dev@dpdk.org, Pavan Nikhilesh , Shijith Thotton , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , jerinj@marvell.com Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Fri, Dec 9, 2022 at 7:11 PM Rahul Bhansali wrote: > > Wait for CPT flow control on WQE path. Please add Why? If it is bug add Fixes: Also change the subject as event/cnxk: wait for CPT flow control on WQE path > > Signed-off-by: Rahul Bhansali > --- > drivers/event/cnxk/cn9k_worker.h | 1 + > drivers/net/cnxk/cn9k_tx.h | 10 ++++++++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h > index 4c3932da47..d3c5180fbc 100644 > --- a/drivers/event/cnxk/cn9k_worker.h > +++ b/drivers/event/cnxk/cn9k_worker.h > @@ -730,6 +730,7 @@ cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base, > > rte_io_wmb(); > cn9k_sso_txq_fc_wait(txq); > + cn9k_nix_sec_fc_wait_one(txq); > > /* Write CPT instruction to lmt line */ > vst1q_u64(lmt_addr, cmd01); > diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h > index 404edd6aed..7362025a34 100644 > --- a/drivers/net/cnxk/cn9k_tx.h > +++ b/drivers/net/cnxk/cn9k_tx.h > @@ -388,6 +388,16 @@ cn9k_nix_xmit_prep_lmt(uint64_t *cmd, void *lmt_addr, const uint32_t flags) > roc_lmt_mov(lmt_addr, cmd, cn9k_nix_tx_ext_subs(flags)); > } > > +static __rte_always_inline void > +cn9k_nix_sec_fc_wait_one(const struct cn9k_eth_txq *txq) > +{ > + uint64_t nb_desc = txq->cpt_desc; > + uint64_t *fc = txq->cpt_fc; > + > + while (nb_desc <= __atomic_load_n(fc, __ATOMIC_RELAXED)) > + ; > +} > + > static __rte_always_inline uint64_t > cn9k_nix_xmit_submit_lmt(const rte_iova_t io_addr) > { > -- > 2.25.1 >