From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7C29A034C; Thu, 24 Feb 2022 21:40:13 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 985FA41143; Thu, 24 Feb 2022 21:40:13 +0100 (CET) Received: from mail-io1-f53.google.com (mail-io1-f53.google.com [209.85.166.53]) by mails.dpdk.org (Postfix) with ESMTP id 04E554113D for ; Thu, 24 Feb 2022 21:40:13 +0100 (CET) Received: by mail-io1-f53.google.com with SMTP id r7so4225411iot.3 for ; Thu, 24 Feb 2022 12:40:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=u/U4w48S3lJlpsj69sYn09ruIYbgxkpyKIdX1M5aImQ=; b=C1wq6o+F8AzdQHy9MNyakW91/mNUReHpIUY8/uMKV3BKuoJ26KJUaU7VYU5iNhn90V oPbS/ytjR57K+5iYjxzOSIFw2ZDhgiKw5HPO/Jz0ji4VaPzCjks2Qnxcls1mFrNThASo iq9kUzmu2omrE3PEDuahQgGJh3v3JWksPLUC7aMsjWKnaX4M47x8IouLy8z+q/rJN+mm TsMnTpS80V4uATP+Mf9sfqLeBqx8q/DWUzU10SxQ+w2IFlUj+x9S0yrOk4OfBR3qU3CZ k46r//BRHq/smMLvrDStB2lE42hEy1uOyD9ETRoHHjiaJ/uuF4YiTEVb7dJjhR/bfHBs s0ZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=u/U4w48S3lJlpsj69sYn09ruIYbgxkpyKIdX1M5aImQ=; b=eBu23l3SiWPOl/M2KBlwyb7IXavsL98/15mrVNcg+rHBNB2V6wWDWnhWeGZUxHunaG 2Ab1dTLMI3K6cxp6GbiNpqAL4SXXhpVd9t+Sl4EH7X7z0qCzxuPhLdlHLlnVcfajLIgd 8jq9ufh6HzmG3sUJ67Cy3q5TOqV/PmuqGoJWpjNNnHmsqtDT05Coonq3a1mC4t5wcRDx qNgfR967/t642AZNCmhPd9eRRsa/47tx9VcfQaRTKfxwOq6aqSlrrCCOn7WDkwJiCf0K mnAO4XDLOZUv5wtdbayHWNupRkYzTlVmEbgC55G1U0Rfxci4PKhuPTvNlfp5fBvLhft6 OtnQ== X-Gm-Message-State: AOAM532wtaxlEP+i6IA3ToP1U300eogANokadR946KjhNLUCqfOm6VhM I1WdLugvZVEiVHpMKiwJOiYzLDYQqBNm0wbaN1anGI0dDDVfDQ== X-Google-Smtp-Source: ABdhPJzF841Sm+NyDa3a67Rdv60DfMVWyDX4keu6/cEKfY816BUXSHDzfmOyns8vx7bf5a3nmy91Ev5Vw9LNkqnkuLU= X-Received: by 2002:a02:aca:0:b0:314:9da8:7be0 with SMTP id 193-20020a020aca000000b003149da87be0mr3481382jaw.280.1645735210921; Thu, 24 Feb 2022 12:40:10 -0800 (PST) MIME-Version: 1.0 References: <20220224161013.4566-1-pbhagavatula@marvell.com> <20220224184039.786663-1-jerinj@marvell.com> In-Reply-To: <20220224184039.786663-1-jerinj@marvell.com> From: Jerin Jacob Date: Fri, 25 Feb 2022 02:09:45 +0530 Message-ID: Subject: Re: [dpdk-dev] [PATCH v3 1/2] net/cnxk: optimize Rx packet size extraction To: Jerin Jacob Cc: dpdk-dev , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Fri, Feb 25, 2022 at 12:09 AM wrote: > > From: Pavan Nikhilesh > > In vWQE mode, the mbuf address is calculated without using the > iova list. > > Packet length can also be calculated by using NIX_PARSE_S by > which we can completely eliminate reading 2nd cache line > depending on the offloads enabled. > > Signed-off-by: Pavan Nikhilesh > Acked-by: Jerin Jacob > --- > v3: > - Change NIX_MBUF_VALIDATE_NEXT macro to inline function > - Fixed the relevant checkpatch warning at > http://mails.dpdk.org/archives/test-report/2022-February/264235.html Series applied to dpdk-next-net-mrvl/for-next-net. Thanks. > > v2 : > - Reword commit message. > > drivers/net/cnxk/cn10k_rx.h | 73 +++++++++++++++++++++++++++---------- > 1 file changed, 53 insertions(+), 20 deletions(-) > > diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h > index abf280102b..236a1dca6e 100644 > --- a/drivers/net/cnxk/cn10k_rx.h > +++ b/drivers/net/cnxk/cn10k_rx.h > @@ -590,8 +590,8 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, > *(uint64_t *)args : > rxq->mbuf_initializer; > const uint64x2_t data_off = flags & NIX_RX_VWQE_F ? > - vdupq_n_u64(0x80ULL) : > - vdupq_n_u64(rxq->data_off); > + vdupq_n_u64(RTE_PKTMBUF_HEADROOM) : > + vdupq_n_u64(rxq->data_off); > const uint32_t qmask = flags & NIX_RX_VWQE_F ? 0 : rxq->qmask; > const uint64_t wdata = flags & NIX_RX_VWQE_F ? 0 : rxq->wdata; > const uintptr_t desc = flags & NIX_RX_VWQE_F ? 0 : rxq->desc; > @@ -687,6 +687,12 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, > cq3_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 3, 64, flags)); > > if (!(flags & NIX_RX_VWQE_F)) { > + /* Get NIX_RX_SG_S for size and buffer pointer */ > + cq0_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 0, 64, flags)); > + cq1_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 1, 64, flags)); > + cq2_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 2, 64, flags)); > + cq3_w8 = vld1q_u64(CQE_PTR_OFF(cq0, 3, 64, flags)); > + > /* Extract mbuf from NIX_RX_SG_S */ > mbuf01 = vzip2q_u64(cq0_w8, cq1_w8); > mbuf23 = vzip2q_u64(cq2_w8, cq3_w8); > @@ -705,21 +711,22 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, > mbuf2 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 0); > mbuf3 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 1); > > - /* Mask to get packet len from NIX_RX_SG_S */ > - const uint8x16_t shuf_msk = { > - 0xFF, 0xFF, /* pkt_type set as unknown */ > - 0xFF, 0xFF, /* pkt_type set as unknown */ > - 0, 1, /* octet 1~0, low 16 bits pkt_len */ > - 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */ > - 0, 1, /* octet 1~0, 16 bits data_len */ > - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; > - > - /* Form the rx_descriptor_fields1 with pkt_len and data_len */ > - f0 = vqtbl1q_u8(cq0_w8, shuf_msk); > - f1 = vqtbl1q_u8(cq1_w8, shuf_msk); > - f2 = vqtbl1q_u8(cq2_w8, shuf_msk); > - f3 = vqtbl1q_u8(cq3_w8, shuf_msk); > + if (!(flags & NIX_RX_VWQE_F)) { > + /* Mask to get packet len from NIX_RX_SG_S */ > + const uint8x16_t shuf_msk = { > + 0xFF, 0xFF, /* pkt_type set as unknown */ > + 0xFF, 0xFF, /* pkt_type set as unknown */ > + 0, 1, /* octet 1~0, low 16 bits pkt_len */ > + 0xFF, 0xFF, /* skip high 16it pkt_len, zero out */ > + 0, 1, /* octet 1~0, 16 bits data_len */ > + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; > > + /* Form the rx_descriptor_fields1 with pkt_len and data_len */ > + f0 = vqtbl1q_u8(cq0_w8, shuf_msk); > + f1 = vqtbl1q_u8(cq1_w8, shuf_msk); > + f2 = vqtbl1q_u8(cq2_w8, shuf_msk); > + f3 = vqtbl1q_u8(cq3_w8, shuf_msk); > + } > if (flags & NIX_RX_OFFLOAD_SECURITY_F) { > /* Prefetch probable CPT parse header area */ > rte_prefetch_non_temporal(RTE_PTR_ADD(mbuf0, d_off)); > @@ -731,12 +738,42 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, > /* Load CQE word0 and word 1 */ > const uint64_t cq0_w0 = *CQE_PTR_OFF(cq0, 0, 0, flags); > const uint64_t cq0_w1 = *CQE_PTR_OFF(cq0, 0, 8, flags); > + const uint64_t cq0_w2 = *CQE_PTR_OFF(cq0, 0, 16, flags); > const uint64_t cq1_w0 = *CQE_PTR_OFF(cq0, 1, 0, flags); > const uint64_t cq1_w1 = *CQE_PTR_OFF(cq0, 1, 8, flags); > + const uint64_t cq1_w2 = *CQE_PTR_OFF(cq0, 1, 16, flags); > const uint64_t cq2_w0 = *CQE_PTR_OFF(cq0, 2, 0, flags); > const uint64_t cq2_w1 = *CQE_PTR_OFF(cq0, 2, 8, flags); > + const uint64_t cq2_w2 = *CQE_PTR_OFF(cq0, 2, 16, flags); > const uint64_t cq3_w0 = *CQE_PTR_OFF(cq0, 3, 0, flags); > const uint64_t cq3_w1 = *CQE_PTR_OFF(cq0, 3, 8, flags); > + const uint64_t cq3_w2 = *CQE_PTR_OFF(cq0, 3, 16, flags); > + > + if (flags & NIX_RX_VWQE_F) { > + uint16_t psize0, psize1, psize2, psize3; > + > + psize0 = (cq0_w2 & 0xFFFF) + 1; > + psize1 = (cq1_w2 & 0xFFFF) + 1; > + psize2 = (cq2_w2 & 0xFFFF) + 1; > + psize3 = (cq3_w2 & 0xFFFF) + 1; > + > + f0 = vdupq_n_u64(0); > + f1 = vdupq_n_u64(0); > + f2 = vdupq_n_u64(0); > + f3 = vdupq_n_u64(0); > + > + f0 = vsetq_lane_u16(psize0, f0, 2); > + f0 = vsetq_lane_u16(psize0, f0, 4); > + > + f1 = vsetq_lane_u16(psize1, f1, 2); > + f1 = vsetq_lane_u16(psize1, f1, 4); > + > + f2 = vsetq_lane_u16(psize2, f2, 2); > + f2 = vsetq_lane_u16(psize2, f2, 4); > + > + f3 = vsetq_lane_u16(psize3, f3, 2); > + f3 = vsetq_lane_u16(psize3, f3, 4); > + } > > if (flags & NIX_RX_OFFLOAD_RSS_F) { > /* Fill rss in the rx_descriptor_fields1 */ > @@ -805,10 +842,6 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, > } > > if (flags & NIX_RX_OFFLOAD_VLAN_STRIP_F) { > - uint64_t cq0_w2 = *(uint64_t *)(cq0 + CQE_SZ(0) + 16); > - uint64_t cq1_w2 = *(uint64_t *)(cq0 + CQE_SZ(1) + 16); > - uint64_t cq2_w2 = *(uint64_t *)(cq0 + CQE_SZ(2) + 16); > - uint64_t cq3_w2 = *(uint64_t *)(cq0 + CQE_SZ(3) + 16); > > ol_flags0 = nix_vlan_update(cq0_w2, ol_flags0, &f0); > ol_flags1 = nix_vlan_update(cq1_w2, ol_flags1, &f1); > -- > 2.35.1 >