From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E67B9A09D3; Thu, 12 Nov 2020 18:01:00 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 9FF665F2F; Thu, 12 Nov 2020 18:00:59 +0100 (CET) Received: from mail-il1-f195.google.com (mail-il1-f195.google.com [209.85.166.195]) by dpdk.org (Postfix) with ESMTP id C8A345F18 for <dev@dpdk.org>; Thu, 12 Nov 2020 18:00:57 +0100 (CET) Received: by mail-il1-f195.google.com with SMTP id t13so5909844ilp.2 for <dev@dpdk.org>; Thu, 12 Nov 2020 09:00:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=4xqfXkrGtoV0ReXoHd4DBWVus8hj1A008Vq/FeLPCNw=; b=tEMwKbR93baY9xfeIqK3x/xU8WLTZ0jCUEcahHwkAoLWMCa/oMp/cvOA/IfXGQDFat wwHkjitstjT3Uo007EqjGguA3B2JCm/3p11f5sVcNhEqBIocvezVRbQf0o3n0HtdqarW 8E6VCY5LuFC5/nayJO5j2quacr342Z7sl3HUKU3IiTVM9Wy6wJiJbVJk1KCH0GOF40DC yKskXJDvRr4OTVBnziqYAd5y/0osbDOvbVmZLacU2JZudBetCfd3RQDMmkygIFCB6UyC Uz4ApL7IRg2csUdFchi57Hp6ZCeiMDzUiTaRNoQchIK5uzm1vk4AXW+6qEvOHNtUJLcG 1v7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=4xqfXkrGtoV0ReXoHd4DBWVus8hj1A008Vq/FeLPCNw=; b=k0T48LFzUXSd6JxdLLFLOXbYxCSgmv2o36kjAhIi7t9yLEqRmnGQoWdW6d7d8ZkSKY +p4qfCgCgtNWSzcqaIoJb46WSkbLok8NZ1iiQ4BcRBYIm2wVsGt5JfB5Qs4JSzA+QsKf 43gzG7/uEiDRIJPzDJoekgcLBdpAQGhUGoQLVGP0kpgJxgZXbB1phbK+Va8sCFHy8275 eLFPPTT3XtMierYHbrwcRtA4ZYStCynOELJ02jB+c2JUEjPYFEESk98ydbJtvJBVBm2R WJTyG8wv+aGH0t7Oxnqj66XX6FC+bdquQT7rOi9iJMJS0gNbzDPCBt6xSit/QmYiKeRS n5yg== X-Gm-Message-State: AOAM530GAaj8kaszxSC5Qm26vcViXm2LMqHGCTpYg3Up7QSrtNW8A27G gZVv7ejBTmWO8c2F+fn7BKf6GIu7KTrUdJttE5A= X-Google-Smtp-Source: ABdhPJzZm34Hs+9DMYzChy97wpjc4O9osuyqdzKJS1Hkj/bGYCPyoX0zNWHW+HYhgHdQBYno+sla6JltLhmKggeX2X8= X-Received: by 2002:a05:6e02:c61:: with SMTP id f1mr369698ilj.60.1605200454744; Thu, 12 Nov 2020 09:00:54 -0800 (PST) MIME-Version: 1.0 References: <1604649795-27476-1-git-send-email-juraj.linkes@pantheon.tech> <1605100718-7991-1-git-send-email-juraj.linkes@pantheon.tech> In-Reply-To: <1605100718-7991-1-git-send-email-juraj.linkes@pantheon.tech> From: Jerin Jacob <jerinjacobk@gmail.com> Date: Thu, 12 Nov 2020 22:30:38 +0530 Message-ID: <CALBAE1P9TQsi_PrFc3LCA-yCyk+yVvyUVuUykhmWW1BPFaTr+w@mail.gmail.com> To: =?UTF-8?Q?Juraj_Linke=C5=A1?= <juraj.linkes@pantheon.tech>, Thomas Monjalon <thomas@monjalon.net> Cc: "Richardson, Bruce" <bruce.richardson@intel.com>, "Ruifeng Wang (Arm Technology China)" <Ruifeng.Wang@arm.com>, Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>, Phil Yang <Phil.Yang@arm.com>, Vimal Chungath <vcchunga@amazon.com>, Dharmik Thakkar <Dharmik.Thakkar@arm.com>, Hemant Agrawal <hemant.agrawal@nxp.com>, Ajit Khaparde <ajit.khaparde@broadcom.com>, Ferruh Yigit <ferruh.yigit@intel.com>, dpdk-dev <dev@dpdk.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v9 00/14] Arm build options rework X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> On Wed, Nov 11, 2020 at 6:48 PM Juraj Linke=C5=A1 <juraj.linkes@pantheon.te= ch> wrote: > > The current way of specifying Arm configuration options is insufficient > since we can't identify the SoC we're building for from the MIDR > information. For example, we can't distinguish between N1SDP, Graviton2 > or Ampere Altra. > > Add a way to specify the cpu count and numa node count for cross builds > and aarch64 -> aarch64 (SoC) builds. > > We also want to be able to disable which drivers (and possibly > libraries) are built without user input. This is useful when building: > 1. on an SoC that is slow and we want to build only what is necessary > without the user having to check which libraries they have installed > 2. a cross build on a fast aarch64 machine but with target SoC which > differs in capabilities or libraries. > This is achieved by specifying the drivers in SoC configuration. > > Among libraries, only libnuma can be now disabled. > > Also add an optional way to discover cpu count a numa node count. Fix > -Dmax_lcores and -Dmax_numa_nodes for arm builds. Series Acked-by: Jerin Jacob <jerinj@marvell.com> Series Tested-by: Jerin Jacob <jerinj@marvell.com> # Verified the mcpu and cache line aspects of generic an octeontx2 build # Test the performance of build. No regression see with testpmd, l2fwd, and l3fwd, I would suggest merging this for RC4. Additional features/enhancements can be done in 21.02 for release.