From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id CAD31A0568; Wed, 11 Mar 2020 11:44:21 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id ABFD31BFFE; Wed, 11 Mar 2020 11:44:21 +0100 (CET) Received: from mail-il1-f193.google.com (mail-il1-f193.google.com [209.85.166.193]) by dpdk.org (Postfix) with ESMTP id CD7C31BF94 for ; Wed, 11 Mar 2020 11:44:20 +0100 (CET) Received: by mail-il1-f193.google.com with SMTP id k29so1541906ilg.0 for ; Wed, 11 Mar 2020 03:44:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9Om9ZNCz2xdoBgiDR2/10jpgmLOJe4oijQBhtKv8Fh8=; b=E7nOUMleKNzCq02TNlQs2vnRwveM0QN+pIRKdRbAqr7ndYR8DJ5IS5TS3yEGDHzazj 498LzaaxgtKznYiobgRu0IUJfUGTl4hAG2ZGe+9+xD6LAU2CyGyD+GHXk+6xlxUBKk+C aS+vpIEhc9+I12ItRIm0ogFX9EYPDmJhX6zu7irtYHtNyvpogyo9PZBo9Cnmt/kjV5rR +8UYUrFtGENP1ELxRItkyuCHaCoa2Bt6IxMZKMnIM5dVw/v8+6gvw89wM78cOaAeWRIR qr6Cozwmn/1E52xPskXRwBG+TKEVsu/kpC4YwiSeHa8iLz6ktNTZvqoMGVm3ilJOatUW +3/A== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v3] eal/arm64: fix rdtsc precise version X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Mar 11, 2020 at 3:35 PM Linhaifeng wrote: > > > > > -----Original Message----- > > From: Jerin Jacob [mailto:jerinjacobk@gmail.com] > > Sent: Tuesday, March 10, 2020 6:47 PM > > To: Linhaifeng > > Cc: Gavin Hu ; dev@dpdk.org; thomas@monjalon.net; > > chenchanghu ; xudingke > > ; Lilijun (Jerry) ; Honnappa > > Nagarahalli ; Steve Capper > > ; nd > > Subject: Re: [PATCH v3] eal/arm64: fix rdtsc precise version > > > > On Tue, Mar 10, 2020 at 3:09 PM Linhaifeng wrote: > > > > > > In order to get more accurate the cntvct_el0 reading, SW must invoke > > > isb and arch_counter_enforce_ordering. > > > > > > Reference of linux kernel: > > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tre > > > e/arch/arm64/include/asm/arch_timer.h?h=v5.5#n220 > > > > > > Signed-off-by: Haifeng Lin > > > > Not addressed Fixes: comment > > http://mails.dpdk.org/archives/dev/2020-March/159547.html > > > > > --- > > > .../common/include/arch/arm/rte_atomic_64.h | 3 +++ > > > .../common/include/arch/arm/rte_cycles_64.h | 20 > > +++++++++++++++++-- > > > 2 files changed, 21 insertions(+), 2 deletions(-) > > > > > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > index 859ae129d..2587f98a2 100644 > > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > @@ -21,6 +21,7 @@ extern "C" { > > > > > > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define > > > dmb(opt) asm volatile("dmb " #opt : : : "memory") > > > +#define isb() (asm volatile("isb" : : : "memory")) > > > > > > #define rte_mb() dsb(sy) > > > > > > @@ -44,6 +45,8 @@ extern "C" { > > > > > > #define rte_cio_rmb() dmb(oshld) > > > > > > +#define rte_isb() isb() > > > > Not addressed comment > > http://mails.dpdk.org/archives/dev/2020-March/159547.html > > > > > > > + > > > /*------------------------ 128 bit atomic operations > > > -------------------------*/ > > > > > > #if defined(__ARM_FEATURE_ATOMICS) || > > > defined(RTE_ARM_FEATURE_ATOMICS) diff --git > > > a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > > b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > > index 68e7c7338..bc4e3f8e6 100644 > > > --- a/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > > +++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_64.h > > > @@ -18,6 +18,7 @@ extern "C" { > > > * The time base for this lcore. > > > */ > > > #ifndef RTE_ARM_EAL_RDTSC_USE_PMU > > > + > > > /** > > > * This call is portable to any ARMv8 architecture, however, typically > > > * cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks. > > > @@ -59,11 +60,26 @@ rte_rdtsc(void) > > > } > > > #endif > > > > > > +#define arch_counter_enforce_ordering(val) do > > { \ > > > + uint64_t tmp, _val = (val); > > \ > > > + > > \ > > > + asm > > volatile( > > \ > > > + " eor %0, %1, %1\n" > > \ > > > + " add %0, sp, %0\n" > > \ > > > + " ldr xzr, [%0]" > > \ > > > + : "=r" (tmp) : "r" (_val)); > > \ > > > +} while (0) > > > + > > > > Not addressed the comments in > > http://mails.dpdk.org/archives/dev/2020-March/159547.html > > > > Gavin, Linhaifeng, > > I don't think, this ordering is valid in the DPDK context. > > > > See the patch from Will. > > https://lore.kernel.org/patchwork/patch/1076132/ > > > > Thoughts? > > I think arch_counter_enforce_ordering maybe is invalid but isb must be valid for DPDK context. Yes. Only isb required in the DPDK context. That would translate to the following change - rte_mb(); + asm volatile("isb" : : : "memory") With the above change and fixing(removing arch_counter_enforce_ordering) in git commit log: Acked-by: Jerin Jacob