From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AD57043193; Wed, 18 Oct 2023 06:30:07 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9D55B4025F; Wed, 18 Oct 2023 06:30:07 +0200 (CEST) Received: from mail-qt1-f174.google.com (mail-qt1-f174.google.com [209.85.160.174]) by mails.dpdk.org (Postfix) with ESMTP id AD8CF4003C for ; Wed, 18 Oct 2023 06:30:05 +0200 (CEST) Received: by mail-qt1-f174.google.com with SMTP id d75a77b69052e-41cbd1d7e04so1829901cf.1 for ; Tue, 17 Oct 2023 21:30:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697603405; x=1698208205; darn=dpdk.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=LMXTDeh+n3S/x/0yoW3H8AQ2tI/FJVUSyLkvnG6TTG4=; b=OoB6X0TADlyZkBEzcvrcxVI9WPm1xfgk7V6lMN/aru5zWnExKseWWTsg517ygcxPNc jogbFUqPJ72QEiC7ICfmDxUvf67XtdRDkvYNcOhiS3JS0lgzEUzS6v3cO5jFdMttx8qK pnqLvRThjS9CAgykGlVWnDujfjPjNMufVIUthlUOd7xcKDaN6xAeexhC5VsqUQpUbEfN kxxeoipinzNupURon02t/u7iKyd4mWdQGq4a993aPLr0YqlBRtffuW2dJYlknWrof2kU vaHLh1wid5PnB17FRHVZkPy44832R3+I5W92NRJEpASA2g9yKGdQRxiCq+akFAhtgAPB +PFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697603405; x=1698208205; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LMXTDeh+n3S/x/0yoW3H8AQ2tI/FJVUSyLkvnG6TTG4=; b=AYL3H23lB/YDuud84t8iU7nl5cJmBSfoBllioUh61HmkWNUHqZVFNLznS6a89DCAPU uCEd9kUAJkuY8Qdmle9kqKrlQBh56FuUj91oJTpG94tI/yoQJ3V24tK/3WNsUMKWGxB9 jfAuTR1SIczIxMy4Oz4aiEA9nJgo/DhZk3M8mXVPewodDBzggZrbfp2XciuaYEQaGAsK etWHUX+nqmUtxFSU99pebvYfbp5IjywajodC37A461zIzSHyTgzIkFOW4EPbmcaXI6mH swcUd9VViYdJksyPLOEfX4gvkEssbNIqjcPprC7Pv0UnAZQfuVUPt0PDmIPZvTHIS+24 VMXg== X-Gm-Message-State: AOJu0YxggwkCJdvFTKA5UZ9dZMyNLV10oaGV8zlBkj+frdGKJrc6r06X 5t4GUGLcBY7/1uLSxOhbi54RVFGHJpQYqY2MKTtSg/hSaUs= X-Google-Smtp-Source: AGHT+IGu2q7sn5dkKJjYN0pSC5HN8Oz5TasH3TOfciZMcngWAiQQMGH9csxxFzd5m3hjCn6ID6w5SnaI5f/kOFP7znQ= X-Received: by 2002:a05:622a:1051:b0:417:fd7e:2154 with SMTP id f17-20020a05622a105100b00417fd7e2154mr5071585qte.9.1697603405009; Tue, 17 Oct 2023 21:30:05 -0700 (PDT) MIME-Version: 1.0 References: <20231013163548.2226503-1-asekhar@marvell.com> In-Reply-To: <20231013163548.2226503-1-asekhar@marvell.com> From: Jerin Jacob Date: Wed, 18 Oct 2023 09:59:38 +0530 Message-ID: Subject: Re: [PATCH] common/cnxk: fix pool buffer size in opaque mode To: Ashwin Sekhar T K Cc: dev@dpdk.org, Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , jerinj@marvell.com, pbhagavatula@marvell.com, psatheesh@marvell.com, anoobj@marvell.com, gakhil@marvell.com, hkalra@marvell.com, Kommula Shiva Shankar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Fri, Oct 13, 2023 at 10:06=E2=80=AFPM Ashwin Sekhar T K wrote: > > From: Kommula Shiva Shankar > > Pool buffer size in opaque mode must always be set to 0. > > Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations") > > Signed-off-by: Kommula Shiva Shankar > Signed-off-by: Ashwin Sekhar T K Acked-by: Jerin Jacob > --- > drivers/common/cnxk/roc_npa.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.= c > index b76b8e2342..6c14c49901 100644 > --- a/drivers/common/cnxk/roc_npa.c > +++ b/drivers/common/cnxk/roc_npa.c > @@ -517,7 +517,11 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const ui= nt32_t block_size, > /* Update pool fields */ > pool->stack_base =3D mz->iova; > pool->ena =3D 1; > - pool->buf_size =3D block_size / ROC_ALIGN; > + /* In opaque mode buffer size must be 0 */ > + if (!pool->nat_align) > + pool->buf_size =3D 0; > + else > + pool->buf_size =3D block_size / ROC_ALIGN; > pool->stack_max_pages =3D stack_size; > pool->shift =3D plt_log2_u32(block_count); > pool->shift =3D pool->shift < 8 ? 0 : pool->shift - 8; > -- > 2.25.1 >