From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 63843A034C; Tue, 30 Aug 2022 06:51:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4B45840F18; Tue, 30 Aug 2022 06:51:29 +0200 (CEST) Received: from mail-qv1-f41.google.com (mail-qv1-f41.google.com [209.85.219.41]) by mails.dpdk.org (Postfix) with ESMTP id 17E0A40F17 for ; Tue, 30 Aug 2022 06:51:28 +0200 (CEST) Received: by mail-qv1-f41.google.com with SMTP id n4so5317649qvt.7 for ; Mon, 29 Aug 2022 21:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=97qHZdB/5hsoZJgKu3wblTlCNkyAOqWcXrLWee+w1QY=; b=WABBXTYl84gfm4AXBFwj0Pu0fWO67mmZa9iV+CEkwBzCcGxWi+H1ApqwLn/dyMutWZ a/IaLsSRZtV9KkOUid7ZL8St/q58PNuU3zV7SuMDtgVTOv2DdbicSdiQeLA0jcuWe8Ax Bn2ewyUIE+XKXYMM27+5TOl3FYVKjs0cvpnbZgVLKTL5CjIRI5ol8fy+xjaBrIKs0etn 123FvbhP3vnIhSnAwNKPMp0/Brs05RJBS9Lvh4Zvsl0RUy8T5vOHRSapbju2ArQmvenW tlahWKPE0erjW5D+VJ/KxOEWQByC7ZT3LAyju5f4Zj5FQbzPwnbV6ivj6ErjpU6EbfS1 nWVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=97qHZdB/5hsoZJgKu3wblTlCNkyAOqWcXrLWee+w1QY=; b=aWzQ99w24I0ShgOxmRliap0foc1Ab+xBwKgpDbxXCYSXSsQZ3+WfiVsEFe9NBa8e/j /e3+k+xv7rRXLy6rD11mmQh+UU9h2zgqhcmY1NFCNktrC/hPEiOoJJFpPMvA2PZwGp0I jqmzwTkEbtAhs9ToqI93lFecrBVXL6lw3CVGXcalVrxcWY7eOMa4baA8Da3+/WIrGLM7 oA/HNO/VU6erLO3+epFXXcGAq+4bDBc1Tb8YK4zV1S83aWrwCCTIhs0mXT5HKEDKGvKB 8crbk8GmoxO22i0JhuZND1DgoOFqG4MUUWua58Jp0YzhORW/QQkge75hhOCHt6g32xyR 7NeA== X-Gm-Message-State: ACgBeo06Tc+to0nqTDCuqLEdpj2Y1YUbWrf2T+DnCQdzOM+hMKanRzjO Vsy2MteBF3V97TyCeFuDM2lcw5HeS27paldOZRsA1kEDh8A= X-Google-Smtp-Source: AA6agR4xV/hvePcvXtXB51IF6MwzqmXliLEVE4nzGpwzQ/z3Lbxi2B1xS0zS/4aAEkdziUh3KiDEFX1Z9vTS+feFVHs= X-Received: by 2002:a05:6214:4005:b0:474:3c94:cdc2 with SMTP id kd5-20020a056214400500b004743c94cdc2mr13305306qvb.17.1661835087388; Mon, 29 Aug 2022 21:51:27 -0700 (PDT) MIME-Version: 1.0 References: <20220809184908.24030-1-ndabilpuram@marvell.com> In-Reply-To: <20220809184908.24030-1-ndabilpuram@marvell.com> From: Jerin Jacob Date: Tue, 30 Aug 2022 10:21:01 +0530 Message-ID: Subject: Re: [PATCH 01/23] common/cnxk: fix part value for cn10k To: Nithin Dabilpuram Cc: Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Jerin Jacob , dpdk-dev , Harman Kalra Content-Type: text/plain; charset="UTF-8" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Wed, Aug 10, 2022 at 12:19 AM Nithin Dabilpuram wrote: > > From: Harman Kalra > > Updating the logic for getting part and pass value for cn10k family, > as device tree compatible logic does not work in VMs. > Scanning all the PCI device and detect first RVU device, subsystem > device file gives part no and revision file provide pass information. > > Fixes: 014a9e222bac ("common/cnxk: add model init and IO handling API") > > Signed-off-by: Harman Kalra > --- > > Depends-on: series-23650("[v2] event/cnxk: add eth port specific PTP enable") > Depends-on: series-24029("[1/4] cnxk/net: add fc check in vector event Tx path") # In order to merge the series, We need to remove the dependency with event/cnxk patches as both are going to different trees. Could you just pull 1/4 of https://patches.dpdk.org/project/dpdk/patch/20220719111125.8276-1-pbhagavatula@marvell.com/ and rebase this series on top of dpdk-next-net-mrvl and send the next version. # Also, Please update git commit log in this series whenever there are only one liners. > > drivers/common/cnxk/roc_model.c | 152 +++++++++++++++++++++++++++---------- > drivers/common/cnxk/roc_platform.h | 3 + > 2 files changed, 113 insertions(+), 42 deletions(-) > > diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c > index a68baa6..791ffa6 100644 > --- a/drivers/common/cnxk/roc_model.c > +++ b/drivers/common/cnxk/roc_model.c > @@ -2,6 +2,7 @@ > * Copyright(C) 2021 Marvell. > */ > > +#include > #include > #include > > @@ -40,6 +41,16 @@ struct roc_model *roc_model; > #define MODEL_MINOR_SHIFT 0 > #define MODEL_MINOR_MASK ((1 << MODEL_MINOR_BITS) - 1) > > +#define MODEL_CN10K_PART_SHIFT 8 > +#define MODEL_CN10K_PASS_BITS 4 > +#define MODEL_CN10K_PASS_MASK ((1 << MODEL_CN10K_PASS_BITS) - 1) > +#define MODEL_CN10K_MAJOR_BITS 2 > +#define MODEL_CN10K_MAJOR_SHIFT 2 > +#define MODEL_CN10K_MAJOR_MASK ((1 << MODEL_CN10K_MAJOR_BITS) - 1) > +#define MODEL_CN10K_MINOR_BITS 2 > +#define MODEL_CN10K_MINOR_SHIFT 0 > +#define MODEL_CN10K_MINOR_MASK ((1 << MODEL_CN10K_MINOR_BITS) - 1) > + > static const struct model_db { > uint32_t impl; > uint32_t part; > @@ -66,55 +77,101 @@ static const struct model_db { > {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0, > "cnf95xxmm_a0"}}; > > -static uint32_t > -cn10k_part_get(void) > +/* Detect if RVU device */ > +static bool > +is_rvu_device(unsigned long val) > { > - uint32_t soc = 0x0; > - char buf[BUFSIZ]; > - char *ptr; > - FILE *fd; > - > - /* Read the CPU compatible variant */ > - fd = fopen("/proc/device-tree/compatible", "r"); > - if (!fd) { > - plt_err("Failed to open /proc/device-tree/compatible"); > - goto err; > - } > + return (val == PCI_DEVID_CNXK_RVU_PF || val == PCI_DEVID_CNXK_RVU_VF || > + val == PCI_DEVID_CNXK_RVU_AF || > + val == PCI_DEVID_CNXK_RVU_AF_VF || > + val == PCI_DEVID_CNXK_RVU_NPA_PF || > + val == PCI_DEVID_CNXK_RVU_NPA_VF || > + val == PCI_DEVID_CNXK_RVU_SSO_TIM_PF || > + val == PCI_DEVID_CNXK_RVU_SSO_TIM_VF || > + val == PCI_DEVID_CN10K_RVU_CPT_PF || > + val == PCI_DEVID_CN10K_RVU_CPT_VF); > +} > > - if (fgets(buf, sizeof(buf), fd) == NULL) { > - plt_err("Failed to read from /proc/device-tree/compatible"); > - goto fclose; > - } > - ptr = strchr(buf, ','); > - if (!ptr) { > - plt_err("Malformed 'CPU compatible': <%s>", buf); > - goto fclose; > - } > - ptr++; > - if (strcmp("cn10ka", ptr) == 0) { > - soc = PART_106xx; > - } else if (strcmp("cnf10ka", ptr) == 0) { > - soc = PART_105xx; > - } else if (strcmp("cnf10kb", ptr) == 0) { > - soc = PART_105xxN; > - } else if (strcmp("cn10kb", ptr) == 0) { > - soc = PART_103xx; > - } else { > - plt_err("Unidentified 'CPU compatible': <%s>", ptr); > - goto fclose; > +static int > +rvu_device_lookup(const char *dirname, uint32_t *part, uint32_t *pass) > +{ > + char filename[PATH_MAX]; > + unsigned long val; > + > + /* Check if vendor id is cavium */ > + snprintf(filename, sizeof(filename), "%s/vendor", dirname); > + if (plt_sysfs_value_parse(filename, &val) < 0) > + goto error; > + > + if (val != PCI_VENDOR_ID_CAVIUM) > + goto error; > + > + /* Get device id */ > + snprintf(filename, sizeof(filename), "%s/device", dirname); > + if (plt_sysfs_value_parse(filename, &val) < 0) > + goto error; > + > + /* Check if device ID belongs to any RVU device */ > + if (!is_rvu_device(val)) > + goto error; > + > + /* Get subsystem_device id */ > + snprintf(filename, sizeof(filename), "%s/subsystem_device", dirname); > + if (plt_sysfs_value_parse(filename, &val) < 0) > + goto error; > + > + *part = val >> MODEL_CN10K_PART_SHIFT; > + > + /* Get revision for pass value*/ > + snprintf(filename, sizeof(filename), "%s/revision", dirname); > + if (plt_sysfs_value_parse(filename, &val) < 0) > + goto error; > + > + *pass = val & MODEL_CN10K_PASS_MASK; > + > + return 0; > +error: > + return -EINVAL; > +} > + > +/* Scans through all PCI devices, detects RVU device and returns > + * subsystem_device > + */ > +static int > +cn10k_part_pass_get(uint32_t *part, uint32_t *pass) > +{ > +#define SYSFS_PCI_DEVICES "/sys/bus/pci/devices" > + char dirname[PATH_MAX]; > + struct dirent *e; > + DIR *dir; > + > + dir = opendir(SYSFS_PCI_DEVICES); > + if (dir == NULL) { > + plt_err("%s(): opendir failed: %s\n", __func__, > + strerror(errno)); > + return -errno; > } > > -fclose: > - fclose(fd); > + while ((e = readdir(dir)) != NULL) { > + if (e->d_name[0] == '.') > + continue; > + > + snprintf(dirname, sizeof(dirname), "%s/%s", SYSFS_PCI_DEVICES, > + e->d_name); > + > + /* Lookup for rvu device and get part pass information */ > + if (!rvu_device_lookup(dirname, part, pass)) > + break; > + } > > -err: > - return soc; > + closedir(dir); > + return 0; > } > > static bool > populate_model(struct roc_model *model, uint32_t midr) > { > - uint32_t impl, major, part, minor; > + uint32_t impl, major, part, minor, pass; > bool found = false; > size_t i; > > @@ -124,8 +181,19 @@ populate_model(struct roc_model *model, uint32_t midr) > minor = (midr >> MODEL_MINOR_SHIFT) & MODEL_MINOR_MASK; > > /* Update part number for cn10k from device-tree */ > - if (part == SOC_PART_CN10K) > - part = cn10k_part_get(); > + if (part == SOC_PART_CN10K) { > + if (cn10k_part_pass_get(&part, &pass)) > + goto not_found; > + /* > + * Pass value format: > + * Bits 0..1: minor pass > + * Bits 3..2: major pass > + */ > + minor = (pass >> MODEL_CN10K_MINOR_SHIFT) & > + MODEL_CN10K_MINOR_MASK; > + major = (pass >> MODEL_CN10K_MAJOR_SHIFT) & > + MODEL_CN10K_MAJOR_MASK; > + } > > for (i = 0; i < PLT_DIM(model_db); i++) > if (model_db[i].impl == impl && model_db[i].part == part && > @@ -136,7 +204,7 @@ populate_model(struct roc_model *model, uint32_t midr) > found = true; > break; > } > - > +not_found: > if (!found) { > model->flag = 0; > strncpy(model->name, "unknown", ROC_MODEL_STR_LEN_MAX - 1); > diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h > index 502f243..3e7adfc 100644 > --- a/drivers/common/cnxk/roc_platform.h > +++ b/drivers/common/cnxk/roc_platform.h > @@ -24,6 +24,8 @@ > #include > #include > > +#include "eal_filesystem.h" > + > #include "roc_bits.h" > > #if defined(__ARM_FEATURE_SVE) > @@ -94,6 +96,7 @@ > #define plt_pci_device rte_pci_device > #define plt_pci_read_config rte_pci_read_config > #define plt_pci_find_ext_capability rte_pci_find_ext_capability > +#define plt_sysfs_value_parse eal_parse_sysfs_value > > #define plt_log2_u32 rte_log2_u32 > #define plt_cpu_to_be_16 rte_cpu_to_be_16 > -- > 2.8.4 >