From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9CE0543B9B; Mon, 4 Mar 2024 12:45:16 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2812840271; Mon, 4 Mar 2024 12:45:16 +0100 (CET) Received: from mail-yw1-f170.google.com (mail-yw1-f170.google.com [209.85.128.170]) by mails.dpdk.org (Postfix) with ESMTP id 6AF3540262 for ; Mon, 4 Mar 2024 12:45:14 +0100 (CET) Received: by mail-yw1-f170.google.com with SMTP id 00721157ae682-60822b444c9so26784517b3.2 for ; Mon, 04 Mar 2024 03:45:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1709552713; x=1710157513; darn=dpdk.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=MSwV+numuHh/vgeBDlTfd6xvdqItrwPD19NgJ6pW59s=; b=U60luZTjM4/NTtwqsdQyE7AkW0SQTgxq/G2IIjoAO/kGweBjYVo/bAMTjTdorM6znV v66vUJayMRl4DqfN9rnF7QDiN7El5JRzhHGJ4qQVwYKEnhu9e4m6RIdR8LvfvrOdL7R7 ImAfg1yonqXAXWnQ3ZP5pg5THtfQGdyqB6a7O3u+eSrIgV59yh/WswwCfCw4ai8w8ORV LNorKWGcbw9ZVViRuNvwo/vXGqk5l1o4fG4QaYtKV7AKvVsndTVPxs2WU3t9FIn+yFKP lGsyNd5KJN78OWQybC0hl0NfCzKQHpc0z2O+l6NuA5oYJaT6E52p99ibv2bP5NDeZPiz UXvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709552713; x=1710157513; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MSwV+numuHh/vgeBDlTfd6xvdqItrwPD19NgJ6pW59s=; b=OsjNNAeVP8F2BHj65xEr5Fyjlxejch4cSYeRRhLQpdRzho1I9R7bmaql6JT8xZals7 n++HEJ+t4T/vbl1WOzz9Kef8c2fWdTmcEctdw9PaUv7/hYucJ3Fx6LrQifp6eZlY5HEY /6DAjV/Ua8ZiJTLFUnbKJMK2GgHVT42C5KqysuyQ+oMSODIQtUmz5OyBKBgc4Yk7nqbN Nw3uOrjPM7ZvXuoc7Q+/igWWQT3FvzwEnhvT9dl1dp6KoulCbIDajlhqzpQuf3sj+huV VFfctFbLvGxm+Ro6XtsBQQssnOk/X8xAMkh3QGKT0tvc5wSVOgfQvsI6RJZDhv4dvZOO WeZg== X-Forwarded-Encrypted: i=1; AJvYcCWmPMF5pB9aSuRw+qg1w5TZpFR756U8D44c86TCG03+Mk1U5A4jdy68jkxllR7vsnRBlS/M6E86uspmZDU= X-Gm-Message-State: AOJu0Yy8lutSQBHXGZRHly1lbdWsoKavUrPheZTrTnDuGFrofGbQKFqr U/Kl4tSp+srYZeXQV8W2W/Mr6j0JLK6oGuL9taQzL7ocTz3ybYiRcYd5nNzXeoBoRgjrpSTLAm7 C4Psq2JkiNHJ3it/GfhGOG97/PTBQ05grrec= X-Google-Smtp-Source: AGHT+IE2YjCuu3Di0ghN3eJTZStgQVdtg7YcO5rJn/qCctSdUQI3Ayqn4CcbXdXMVgrpV0vkTnubS80tvEu/2t1EDGY= X-Received: by 2002:a25:48c1:0:b0:dcd:a9ad:7d64 with SMTP id v184-20020a2548c1000000b00dcda9ad7d64mr5356287yba.48.1709552713541; Mon, 04 Mar 2024 03:45:13 -0800 (PST) MIME-Version: 1.0 References: <1709286509-18322-1-git-send-email-skoteshwar@marvell.com> <1709545971-17364-1-git-send-email-skoteshwar@marvell.com> In-Reply-To: <1709545971-17364-1-git-send-email-skoteshwar@marvell.com> From: Jerin Jacob Date: Mon, 4 Mar 2024 17:14:47 +0530 Message-ID: Subject: Re: [PATCH v6] net/cnxk: support Tx queue descriptor count To: skoteshwar@marvell.com Cc: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Harman Kalra , dev@dpdk.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Mon, Mar 4, 2024 at 3:30=E2=80=AFPM wrote: > > From: Satha Rao > > Added CNXK APIs to get used txq descriptor count. > > Signed-off-by: Satha Rao Applied to dpdk-next-net-mrvl/for-main. Thanks > --- > > Depends-on: series-30833 ("ethdev: support Tx queue used count") > > v2: > Updated release notes and fixed API for CPT queues. > v3: > Addressed review comments > v5: > Fixed compilation errors > v6: > Fixed checkpatch > > doc/guides/nics/features/cnxk.ini | 1 + > doc/guides/rel_notes/release_24_03.rst | 1 + > drivers/net/cnxk/cn10k_tx_select.c | 22 ++++++++++++++++++++++ > drivers/net/cnxk/cn9k_tx_select.c | 23 +++++++++++++++++++++++ > drivers/net/cnxk/cnxk_ethdev.h | 25 +++++++++++++++++++++++++ > 5 files changed, 72 insertions(+) > > diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features= /cnxk.ini > index b5d9f7e..1c8db1a 100644 > --- a/doc/guides/nics/features/cnxk.ini > +++ b/doc/guides/nics/features/cnxk.ini > @@ -40,6 +40,7 @@ Timesync =3D Y > Timestamp offload =3D Y > Rx descriptor status =3D Y > Tx descriptor status =3D Y > +Tx queue count =3D Y > Basic stats =3D Y > Stats per queue =3D Y > Extended stats =3D Y > diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_note= s/release_24_03.rst > index 2b160cf..b1942b5 100644 > --- a/doc/guides/rel_notes/release_24_03.rst > +++ b/doc/guides/rel_notes/release_24_03.rst > @@ -113,6 +113,7 @@ New Features > * Added support for Rx inject. > * Optimized SW external mbuf free for better performance and avoid SQ = corruption. > * Added support for port representors. > + * Added support for ``rte_eth_tx_queue_count``. > > * **Updated Marvell OCTEON EP driver.** > > diff --git a/drivers/net/cnxk/cn10k_tx_select.c b/drivers/net/cnxk/cn10k_= tx_select.c > index 404f5ba..aa0620e 100644 > --- a/drivers/net/cnxk/cn10k_tx_select.c > +++ b/drivers/net/cnxk/cn10k_tx_select.c > @@ -20,6 +20,24 @@ > eth_dev->tx_pkt_burst; > } > > +#if defined(RTE_ARCH_ARM64) > +static int > +cn10k_nix_tx_queue_count(void *tx_queue) > +{ > + struct cn10k_eth_txq *txq =3D (struct cn10k_eth_txq *)tx_queue; > + > + return cnxk_nix_tx_queue_count(txq->fc_mem, txq->sqes_per_sqb_log= 2); > +} > + > +static int > +cn10k_nix_tx_queue_sec_count(void *tx_queue) > +{ > + struct cn10k_eth_txq *txq =3D (struct cn10k_eth_txq *)tx_queue; > + > + return cnxk_nix_tx_queue_sec_count(txq->fc_mem, txq->sqes_per_sqb= _log2, txq->cpt_fc); > +} > +#endif > + > void > cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev) > { > @@ -63,6 +81,10 @@ > if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) > pick_tx_func(eth_dev, nix_eth_tx_vec_burst_mseg); > } > + if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) > + eth_dev->tx_queue_count =3D cn10k_nix_tx_queue_sec_count; > + else > + eth_dev->tx_queue_count =3D cn10k_nix_tx_queue_count; > > rte_mb(); > #else > diff --git a/drivers/net/cnxk/cn9k_tx_select.c b/drivers/net/cnxk/cn9k_tx= _select.c > index e08883f..5ecf919 100644 > --- a/drivers/net/cnxk/cn9k_tx_select.c > +++ b/drivers/net/cnxk/cn9k_tx_select.c > @@ -20,6 +20,24 @@ > eth_dev->tx_pkt_burst; > } > > +#if defined(RTE_ARCH_ARM64) > +static int > +cn9k_nix_tx_queue_count(void *tx_queue) > +{ > + struct cn9k_eth_txq *txq =3D (struct cn9k_eth_txq *)tx_queue; > + > + return cnxk_nix_tx_queue_count(txq->fc_mem, txq->sqes_per_sqb_log= 2); > +} > + > +static int > +cn9k_nix_tx_queue_sec_count(void *tx_queue) > +{ > + struct cn9k_eth_txq *txq =3D (struct cn9k_eth_txq *)tx_queue; > + > + return cnxk_nix_tx_queue_sec_count(txq->fc_mem, txq->sqes_per_sqb= _log2, txq->cpt_fc); > +} > +#endif > + > void > cn9k_eth_set_tx_function(struct rte_eth_dev *eth_dev) > { > @@ -59,6 +77,11 @@ > if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS) > pick_tx_func(eth_dev, nix_eth_tx_vec_burst_mseg); > } > + if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) > + eth_dev->tx_queue_count =3D cn9k_nix_tx_queue_sec_count; > + else > + eth_dev->tx_queue_count =3D cn9k_nix_tx_queue_count; > + > > rte_mb(); > #else > diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethde= v.h > index 5d42e13..5e04064 100644 > --- a/drivers/net/cnxk/cnxk_ethdev.h > +++ b/drivers/net/cnxk/cnxk_ethdev.h > @@ -464,6 +464,31 @@ struct cnxk_eth_txq_sp { > return ((struct cnxk_eth_txq_sp *)__txq) - 1; > } > > +static inline int > +cnxk_nix_tx_queue_count(uint64_t *mem, uint16_t sqes_per_sqb_log2) > +{ > + uint64_t val; > + > + val =3D rte_atomic_load_explicit((RTE_ATOMIC(uint64_t)*)mem, rte_= memory_order_relaxed); > + val =3D (val << sqes_per_sqb_log2) - val; > + > + return (val & 0xFFFF); > +} > + > +static inline int > +cnxk_nix_tx_queue_sec_count(uint64_t *mem, uint16_t sqes_per_sqb_log2, u= int64_t *sec_fc) > +{ > + uint64_t sq_cnt, sec_cnt, val; > + > + sq_cnt =3D rte_atomic_load_explicit((RTE_ATOMIC(uint64_t)*)mem, r= te_memory_order_relaxed); > + sq_cnt =3D (sq_cnt << sqes_per_sqb_log2) - sq_cnt; > + sec_cnt =3D rte_atomic_load_explicit((RTE_ATOMIC(uint64_t)*)sec_f= c, > + rte_memory_order_relaxed); > + val =3D RTE_MAX(sq_cnt, sec_cnt); > + > + return (val & 0xFFFF); > +} > + > /* Common ethdev ops */ > extern struct eth_dev_ops cnxk_eth_dev_ops; > > -- > 1.8.3.1 >