From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6392EA0A05; Tue, 19 Jan 2021 13:09:32 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2C126140DE2; Tue, 19 Jan 2021 13:09:32 +0100 (CET) Received: from mail-io1-f45.google.com (mail-io1-f45.google.com [209.85.166.45]) by mails.dpdk.org (Postfix) with ESMTP id 0FD40140DE1 for ; Tue, 19 Jan 2021 13:09:29 +0100 (CET) Received: by mail-io1-f45.google.com with SMTP id w18so39053104iot.0 for ; Tue, 19 Jan 2021 04:09:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=2OhdH8tEKf9bd/2YRiApOSXKjCT8Dg/eqxCB4GZy+qo=; b=YeMG731yg/x9pjud3i7CFlAwgIV/BEezG3AeC8ePY8TVj+z3BpVxI00UtwakHNtgVt MnBNUmqkYU3QJwpNHM1z86BsQW2LcChNKmeChmaDViCEgQYu6qWU9vn/JRym1jpAx/F3 9ufIuhQF+71Le3hYNmCHCFVeZLVskHaVRyoB8wzbyn3JCMisyQKuKbmTJFoxTkXCZMeJ 2LMwTSuBQWE05cOW9wEmovZaAacSMBpOTJVax66Ix8GKNenO+Fr6gVa1fkrrNJSdeAKI Q0leukNMmdjcv+DtRMWEKRjyjeXDdxtfzyr3mNa3xPKqSOM2wsl+WeIPBmpjBsPiCcPO K5vA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=2OhdH8tEKf9bd/2YRiApOSXKjCT8Dg/eqxCB4GZy+qo=; b=jcbDHlaIkuuxB2Evfza8W9uA6JgbOiF/YC6abzlVE9JpfNPJ9GX/oHxyPAs62m77y4 2iayeG9xXU9xSmKQspFtGcVWlw9t/UfkTl8SmY/WUpfkayctL4QOnwgqOXXAm/mVW1Dt p3jnnHRNQVURr/fZUyIQOVxHo4ko6jQ0m7AbClbPvI5r8bUC1JMsiSmeSGjNZrhCd8U3 rOc6+qx2cMQlnNaVhJ4eqt2Nz14XpgiuNMQi5Gqce5/ji3kz0RbCioFvA6UUZ0HvpTA0 270jhJxI+IEs/2fBLCfKtPwfgwTleai6Cu0bwcmbRL2rAu2il2NhCrqlDbhXkKU6iHO2 ZlmA== X-Gm-Message-State: AOAM530MsmxDbwE05G4+bIvizN8uMF3QfvmfnvgAID29XiuH1QCnxFnH X67SkXO2oNS95IGdEhNtmiC2SvHf+CCkYAFu7Vo= X-Google-Smtp-Source: ABdhPJxKm2UCsuF69SyJmozS9lAdWoML3PSN8uofEgKM3I5xetc8AgXZBGCi9KIADRDs/POAa43fKFWpiPnhY6ggWEQ= X-Received: by 2002:a5d:959a:: with SMTP id a26mr2677662ioo.94.1611058168455; Tue, 19 Jan 2021 04:09:28 -0800 (PST) MIME-Version: 1.0 References: <20210118093602.5449-1-pnalla@marvell.com> <20210118093602.5449-4-pnalla@marvell.com> In-Reply-To: <20210118093602.5449-4-pnalla@marvell.com> From: Jerin Jacob Date: Tue, 19 Jan 2021 17:39:12 +0530 Message-ID: To: Nalla Pradeep Cc: Radha Mohan Chintakuntla , Veerasenareddy Burru , Jerin Jacob , dpdk-dev , Satananda Burla Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2 04/11] net/octeontx_ep: Added basic device setup. X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Mon, Jan 18, 2021 at 3:07 PM Nalla Pradeep wrote: > > Functions to setup device, basic IQ and OQ registers are added. > > Signed-off-by: Nalla Pradeep > --- > drivers/net/octeontx_ep/meson.build | 2 + > drivers/net/octeontx_ep/otx2_ep_vf.c | 138 +++++++++++++++++++++ > drivers/net/octeontx_ep/otx2_ep_vf.h | 11 ++ > drivers/net/octeontx_ep/otx_ep_common.h | 92 ++++++++++++++ > drivers/net/octeontx_ep/otx_ep_ethdev.c | 10 ++ > drivers/net/octeontx_ep/otx_ep_vf.c | 154 ++++++++++++++++++++++++ > drivers/net/octeontx_ep/otx_ep_vf.h | 33 +++++ > 7 files changed, 440 insertions(+) > create mode 100644 drivers/net/octeontx_ep/otx2_ep_vf.c > create mode 100644 drivers/net/octeontx_ep/otx2_ep_vf.h > create mode 100644 drivers/net/octeontx_ep/otx_ep_vf.c > > diff --git a/drivers/net/octeontx_ep/meson.build b/drivers/net/octeontx_ep/meson.build > index 06663de4e2..7c43c077cf 100644 > --- a/drivers/net/octeontx_ep/meson.build > +++ b/drivers/net/octeontx_ep/meson.build > @@ -4,6 +4,8 @@ > > sources = files( > 'otx_ep_ethdev.c', > + 'otx_ep_vf.c', > + 'otx2_ep_vf.c', > ) > > extra_flags = [] > diff --git a/drivers/net/octeontx_ep/otx2_ep_vf.c b/drivers/net/octeontx_ep/otx2_ep_vf.c > new file mode 100644 > index 0000000000..e03d39f7dc > --- /dev/null > +++ b/drivers/net/octeontx_ep/otx2_ep_vf.c > @@ -0,0 +1,138 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(C) 2020 Marvell. > + */ > + > +#include "otx2_common.h" > +#include "otx_ep_common.h" > +#include "otx2_ep_vf.h" > + > +static void > +otx2_vf_setup_global_iq_reg(struct otx_ep_device *otx_ep, int q_no) > +{ > + volatile uint64_t reg_val = 0ull; > + > + /* Select ES, RO, NS, RDSIZE,DPTR Format#0 for IQs > + * IS_64B is by default enabled. > + */ > + reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(q_no)); > + > + reg_val |= SDP_VF_R_IN_CTL_RDSIZE; > + reg_val |= SDP_VF_R_IN_CTL_IS_64B; > + reg_val |= SDP_VF_R_IN_CTL_ESR; > + > + otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(q_no)); > +} > + > +static void > +otx2_vf_setup_global_oq_reg(struct otx_ep_device *otx_ep, int q_no) > +{ > + volatile uint64_t reg_val = 0ull; > + > + reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_CONTROL(q_no)); > + > +#if defined(BUFPTR_ONLY_MODE) Use devargs instead of compile-time flags. > + reg_val &= ~(SDP_VF_R_OUT_CTL_IMODE); > +#else > + reg_val |= (SDP_VF_R_OUT_CTL_IMODE); > +#endif