[dpdk-dev] [PATCH 1/2] net/octeontx2: add support to enable switch type

[dpdk-dev] [PATCH 1/2] net/octeontx2: add support to enable switch type

[kirankumark]

From: Kiran Kumar K <kirankumark@marvell.com>

Adding support to configure specific switch types like high2 and dsa
on a port. When this switch type is configured, it is expected that
all the traffic on that port should be of specific type only.

Change-Id: I41c47c4f8d844666cd6afe20a60397b83908e2f4
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
 doc/guides/nics/octeontx2.rst               | 12 +++++++++
 drivers/common/octeontx2/otx2_mbox.h        | 19 ++++++++++++-
 drivers/net/octeontx2/otx2_ethdev.c         | 30 +++++++++++++++++++++
 drivers/net/octeontx2/otx2_ethdev_devargs.c | 22 ++++++++++++++-
 drivers/net/octeontx2/otx2_flow.h           |  1 +
 5 files changed, 82 insertions(+), 2 deletions(-)

diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst
index fc8a130fb..adf7c7131 100644
--- a/doc/guides/nics/octeontx2.rst
+++ b/doc/guides/nics/octeontx2.rst
@@ -170,6 +170,18 @@ Runtime Config Options
    With the above configuration, each send queue's decscriptor buffer count is
    limited to a maximum of 64 buffers.
 
+- ``switch header enable`` (default ``none``)
+
+   A port can be configured to a specific switch header type by using
+   ``switch_header`` ``devargs`` parameter.
+
+   For example::
+
+      -w 0002:02:00.0,switch_header="higig2"
+
+   With the above configuration, higig2 will be enabled on that port and the
+   traffic on this port should be higig2 traffic only. Supported switch header
+   types are "higig2" and "dsa".
 
 .. note::
 
diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h
index 445b03e26..c2a9e9fe6 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -89,7 +89,7 @@ struct mbox_msghdr {
 #define OTX2_MBOX_RSP_SIG (0xbeef)
 	/* Signature, for validating corrupted msgs */
 	uint16_t __otx2_io sig;
-#define OTX2_MBOX_VERSION (0x0002)
+#define OTX2_MBOX_VERSION (0x0003)
 	/* Version of msg's structure for this ID */
 	uint16_t __otx2_io ver;
 	/* Offset of next msg within mailbox region */
@@ -236,6 +236,9 @@ M(NPC_DELETE_FLOW,	  0x600e, npc_delete_flow,			\
 M(NPC_MCAM_READ_ENTRY,	  0x600f, npc_mcam_read_entry,			\
 				  npc_mcam_read_entry_req,		\
 				  npc_mcam_read_entry_rsp)		\
+M(NPC_SET_PKIND,          0x6010, npc_set_pkind,                        \
+				  npc_set_pkind,                        \
+				  msg_rsp)                              \
 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */				\
 M(NIX_LF_ALLOC,		0x8000, nix_lf_alloc, nix_lf_alloc_req,		\
 				nix_lf_alloc_rsp)			\
@@ -329,6 +332,20 @@ struct ready_msg_rsp {
 	uint16_t __otx2_io rclk_freq; /* RCLK frequency */
 };
 
+/* Struct to set pkind */
+struct npc_set_pkind {
+	struct mbox_msghdr hdr;
+#define OTX2_PRIV_FLAGS_DEFAULT  BIT_ULL(0)
+#define OTX2_PRIV_FLAGS_EDSA     BIT_ULL(1)
+#define OTX2_PRIV_FLAGS_HIGIG    BIT_ULL(2)
+#define OTX2_PRIV_FLAGS_CUSTOM   BIT_ULL(63)
+	uint64_t __otx2_io mode;
+#define PKIND_TX		BIT_ULL(0)
+#define PKIND_RX		BIT_ULL(1)
+	uint8_t __otx2_io dir;
+	uint8_t __otx2_io pkind; /* valid only in case custom flag */
+};
+
 /* Structure for requesting resource provisioning.
  * 'modify' flag to be used when either requesting more
  * or detach partial of a certain resource type.
diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index 62291c698..dfa8cd205 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -90,6 +90,30 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
 	return 0;
 }
 
+static int
+nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev)
+{
+	struct otx2_mbox *mbox = dev->mbox;
+	struct npc_set_pkind *req;
+	struct msg_resp *rsp;
+	int rc;
+
+	if (dev->npc_flow.switch_header_type == 0)
+		return 0;
+
+	/* Notify AF about higig2 config */
+	req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
+	req->mode = dev->npc_flow.switch_header_type;
+	req->dir = PKIND_RX;
+	rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
+	if (rc)
+		return rc;
+	req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
+	req->mode = dev->npc_flow.switch_header_type;
+	req->dir = PKIND_TX;
+	return otx2_mbox_process_msg(mbox, (void *)&rsp);
+}
+
 static int
 nix_lf_free(struct otx2_eth_dev *dev)
 {
@@ -1612,6 +1636,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
 		goto fail_offloads;
 	}
 
+	rc = nix_lf_switch_header_type_enable(dev);
+	if (rc) {
+		otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
+		goto free_nix_lf;
+	}
+
 	rc = nix_setup_lso_formats(dev);
 	if (rc) {
 		otx2_err("failed to setup nix lso format fields, rc=%d", rc);
diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c
index 7dc6e92be..ca9a5ffb8 100644
--- a/drivers/net/octeontx2/otx2_ethdev_devargs.c
+++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c
@@ -104,12 +104,27 @@ parse_sqb_count(const char *key, const char *value, void *extra_args)
 	return 0;
 }
 
+static int
+parse_switch_header_type(const char *key, const char *value, void *extra_args)
+{
+	RTE_SET_USED(key);
+
+	if (strcmp(value, "higig2") == 0)
+		*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_HIGIG;
+
+	if (strcmp(value, "dsa") == 0)
+		*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA;
+
+	return 0;
+}
+
 #define OTX2_RSS_RETA_SIZE "reta_size"
 #define OTX2_PTYPE_DISABLE "ptype_disable"
 #define OTX2_SCL_ENABLE "scalar_enable"
 #define OTX2_MAX_SQB_COUNT "max_sqb_count"
 #define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size"
 #define OTX2_FLOW_MAX_PRIORITY "flow_max_priority"
+#define OTX2_SWITCH_HEADER_TYPE "switch_header"
 
 int
 otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
@@ -118,6 +133,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
 	uint16_t rss_size = NIX_RSS_RETA_SIZE;
 	uint16_t sqb_count = NIX_MAX_SQB;
 	uint16_t flow_prealloc_size = 8;
+	uint16_t switch_header_type = 0;
 	uint16_t flow_max_priority = 3;
 	uint16_t scalar_enable = 0;
 	struct rte_kvargs *kvlist;
@@ -141,6 +157,8 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
 			   &parse_flow_prealloc_size, &flow_prealloc_size);
 	rte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,
 			   &parse_flow_max_priority, &flow_max_priority);
+	rte_kvargs_process(kvlist, OTX2_SWITCH_HEADER_TYPE,
+			   &parse_switch_header_type, &switch_header_type);
 	rte_kvargs_free(kvlist);
 
 null_devargs:
@@ -150,6 +168,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
 	dev->rss_info.rss_size = rss_size;
 	dev->npc_flow.flow_prealloc_size = flow_prealloc_size;
 	dev->npc_flow.flow_max_priority = flow_max_priority;
+	dev->npc_flow.switch_header_type = switch_header_type;
 	return 0;
 
 exit:
@@ -162,4 +181,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,
 			      OTX2_SCL_ENABLE "=1"
 			      OTX2_MAX_SQB_COUNT "=<8-512>"
 			      OTX2_FLOW_PREALLOC_SIZE "=<1-32>"
-			      OTX2_FLOW_MAX_PRIORITY "=<1-32>");
+			      OTX2_FLOW_MAX_PRIORITY "=<1-32>"
+			      OTX2_SWITCH_HEADER_TYPE "=<higig2|dsa>");
diff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h
index ab068b088..6bfd5afde 100644
--- a/drivers/net/octeontx2/otx2_flow.h
+++ b/drivers/net/octeontx2/otx2_flow.h
@@ -190,6 +190,7 @@ struct otx2_npc_flow_info {
 	uint16_t channel; /*rx channel */
 	uint16_t flow_prealloc_size;
 	uint16_t flow_max_priority;
+	uint16_t switch_header_type;
 };
 
 struct otx2_parse_state {
-- 
2.17.1

[dpdk-dev] [PATCH 2/2] net/octeontx2: add support to parse higig2 hdr

[kirankumark]

From: Kiran Kumar K <kirankumark@marvell.com>

Adding support to parse higig2 header in RTE flow for octeontx2.
And added devargs to configure port for higig2.

Change-Id: I6931c2905f90a841c2638251bdfa1e63c7d676e6
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
 doc/guides/nics/octeontx2.rst           |  2 ++
 drivers/common/octeontx2/hw/otx2_npc.h  |  2 ++
 drivers/net/octeontx2/otx2_flow.c       |  1 +
 drivers/net/octeontx2/otx2_flow.h       |  3 ++
 drivers/net/octeontx2/otx2_flow_parse.c | 47 +++++++++++++++++++++++++
 5 files changed, 55 insertions(+)

diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst
index adf7c7131..eb7aaa468 100644
--- a/doc/guides/nics/octeontx2.rst
+++ b/doc/guides/nics/octeontx2.rst
@@ -288,6 +288,8 @@ Patterns:
    +----+--------------------------------+
    | 23 | RTE_FLOW_ITEM_TYPE_GRE_KEY     |
    +----+--------------------------------+
+   | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2      |
+   +----+--------------------------------+
 
 .. note::
 
diff --git a/drivers/common/octeontx2/hw/otx2_npc.h b/drivers/common/octeontx2/hw/otx2_npc.h
index 5b8d3ed8c..a0536e0ae 100644
--- a/drivers/common/octeontx2/hw/otx2_npc.h
+++ b/drivers/common/octeontx2/hw/otx2_npc.h
@@ -182,6 +182,8 @@ enum npc_kpu_la_ltype {
 	NPC_LT_LA_IH_8_ETHER,
 	NPC_LT_LA_IH_4_ETHER,
 	NPC_LT_LA_IH_2_ETHER,
+	NPC_LT_LA_HIGIG2_ETHER,
+	NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
 };
 
 enum npc_kpu_lb_ltype {
diff --git a/drivers/net/octeontx2/otx2_flow.c b/drivers/net/octeontx2/otx2_flow.c
index bdbf123a9..f1fb9f988 100644
--- a/drivers/net/octeontx2/otx2_flow.c
+++ b/drivers/net/octeontx2/otx2_flow.c
@@ -325,6 +325,7 @@ flow_parse_pattern(struct rte_eth_dev *dev,
 {
 	flow_parse_stage_func_t parse_stage_funcs[] = {
 		flow_parse_meta_items,
+		otx2_flow_parse_higig2_hdr,
 		otx2_flow_parse_la,
 		otx2_flow_parse_lb,
 		otx2_flow_parse_lc,
diff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h
index 6bfd5afde..df78f41d3 100644
--- a/drivers/net/octeontx2/otx2_flow.h
+++ b/drivers/net/octeontx2/otx2_flow.h
@@ -29,6 +29,7 @@ enum {
 
 #define NPC_IH_LENGTH			8
 #define NPC_TPID_LENGTH			2
+#define NPC_HIGIG2_LENGTH		16
 #define NPC_COUNTER_NONE		(-1)
 /* 32 bytes from LDATA_CFG & 32 bytes from FLAGS_CFG */
 #define NPC_MAX_EXTRACT_DATA_LEN	(64)
@@ -382,6 +383,8 @@ int otx2_flow_parse_lb(struct otx2_parse_state *pst);
 
 int otx2_flow_parse_la(struct otx2_parse_state *pst);
 
+int otx2_flow_parse_higig2_hdr(struct otx2_parse_state *pst);
+
 int otx2_flow_parse_actions(struct rte_eth_dev *dev,
 			    const struct rte_flow_attr *attr,
 			    const struct rte_flow_action actions[],
diff --git a/drivers/net/octeontx2/otx2_flow_parse.c b/drivers/net/octeontx2/otx2_flow_parse.c
index 2cba0a447..b7b7b6127 100644
--- a/drivers/net/octeontx2/otx2_flow_parse.c
+++ b/drivers/net/octeontx2/otx2_flow_parse.c
@@ -675,6 +675,15 @@ otx2_flow_parse_la(struct otx2_parse_state *pst)
 	if (pst->flow->nix_intf == NIX_INTF_TX) {
 		lt = NPC_LT_LA_IH_NIX_ETHER;
 		info.hw_hdr_len = NPC_IH_LENGTH;
+		if (pst->npc->switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+			lt = NPC_LT_LA_IH_NIX_HIGIG2_ETHER;
+			info.hw_hdr_len += NPC_HIGIG2_LENGTH;
+		}
+	} else {
+		if (pst->npc->switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+			lt = NPC_LT_LA_HIGIG2_ETHER;
+			info.hw_hdr_len = NPC_HIGIG2_LENGTH;
+		}
 	}
 
 	/* Prepare for parsing the item */
@@ -694,6 +703,44 @@ otx2_flow_parse_la(struct otx2_parse_state *pst)
 	return otx2_flow_update_parse_state(pst, &info, lid, lt, 0);
 }
 
+int
+otx2_flow_parse_higig2_hdr(struct otx2_parse_state *pst)
+{
+	struct rte_flow_item_higig2_hdr hw_mask;
+	struct otx2_flow_item_info info;
+	int lid, lt;
+	int rc;
+
+	/* Identify the pattern type into lid, lt */
+	if (pst->pattern->type != RTE_FLOW_ITEM_TYPE_HIGIG2)
+		return 0;
+
+	lid = NPC_LID_LA;
+	lt = NPC_LT_LA_HIGIG2_ETHER;
+	info.hw_hdr_len = 0;
+
+	if (pst->flow->nix_intf == NIX_INTF_TX) {
+		lt = NPC_LT_LA_IH_NIX_HIGIG2_ETHER;
+		info.hw_hdr_len = NPC_IH_LENGTH;
+	}
+
+	/* Prepare for parsing the item */
+	info.def_mask = &rte_flow_item_higig2_hdr_mask;
+	info.hw_mask = &hw_mask;
+	info.len = sizeof(struct rte_flow_item_higig2_hdr);
+	otx2_flow_get_hw_supp_mask(pst, &info, lid, lt);
+	info.spec = NULL;
+	info.mask = NULL;
+
+	/* Basic validation of item parameters */
+	rc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);
+	if (rc)
+		return rc;
+
+	/* Update pst if not validate only? clash check? */
+	return otx2_flow_update_parse_state(pst, &info, lid, lt, 0);
+}
+
 static int
 parse_rss_action(struct rte_eth_dev *dev,
 		 const struct rte_flow_attr *attr,
-- 
2.17.1

[dpdk-dev] [PATCH v2 1/2] net/octeontx2: add support to enable switch type

[kirankumark]

From: Kiran Kumar K <kirankumark@marvell.com>

Adding support to configure specific switch types like high2 and dsa
on a port. When this switch type is configured, it is expected that
all the traffic on that port should be of specific type only.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
V2 Changes:
* Fixed checkpatch issue

 doc/guides/nics/octeontx2.rst               | 12 +++++++++
 drivers/common/octeontx2/otx2_mbox.h        | 19 ++++++++++++-
 drivers/net/octeontx2/otx2_ethdev.c         | 30 +++++++++++++++++++++
 drivers/net/octeontx2/otx2_ethdev_devargs.c | 22 ++++++++++++++-
 drivers/net/octeontx2/otx2_flow.h           |  1 +
 5 files changed, 82 insertions(+), 2 deletions(-)

diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst
index fc8a130fb..adf7c7131 100644
--- a/doc/guides/nics/octeontx2.rst
+++ b/doc/guides/nics/octeontx2.rst
@@ -170,6 +170,18 @@ Runtime Config Options
    With the above configuration, each send queue's decscriptor buffer count is
    limited to a maximum of 64 buffers.

+- ``switch header enable`` (default ``none``)
+
+   A port can be configured to a specific switch header type by using
+   ``switch_header`` ``devargs`` parameter.
+
+   For example::
+
+      -w 0002:02:00.0,switch_header="higig2"
+
+   With the above configuration, higig2 will be enabled on that port and the
+   traffic on this port should be higig2 traffic only. Supported switch header
+   types are "higig2" and "dsa".

 .. note::

diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h
index 445b03e26..c2a9e9fe6 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -89,7 +89,7 @@ struct mbox_msghdr {
 #define OTX2_MBOX_RSP_SIG (0xbeef)
 	/* Signature, for validating corrupted msgs */
 	uint16_t __otx2_io sig;
-#define OTX2_MBOX_VERSION (0x0002)
+#define OTX2_MBOX_VERSION (0x0003)
 	/* Version of msg's structure for this ID */
 	uint16_t __otx2_io ver;
 	/* Offset of next msg within mailbox region */
@@ -236,6 +236,9 @@ M(NPC_DELETE_FLOW,	  0x600e, npc_delete_flow,			\
 M(NPC_MCAM_READ_ENTRY,	  0x600f, npc_mcam_read_entry,			\
 				  npc_mcam_read_entry_req,		\
 				  npc_mcam_read_entry_rsp)		\
+M(NPC_SET_PKIND,          0x6010, npc_set_pkind,                        \
+				  npc_set_pkind,                        \
+				  msg_rsp)                              \
 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */				\
 M(NIX_LF_ALLOC,		0x8000, nix_lf_alloc, nix_lf_alloc_req,		\
 				nix_lf_alloc_rsp)			\
@@ -329,6 +332,20 @@ struct ready_msg_rsp {
 	uint16_t __otx2_io rclk_freq; /* RCLK frequency */
 };

+/* Struct to set pkind */
+struct npc_set_pkind {
+	struct mbox_msghdr hdr;
+#define OTX2_PRIV_FLAGS_DEFAULT  BIT_ULL(0)
+#define OTX2_PRIV_FLAGS_EDSA     BIT_ULL(1)
+#define OTX2_PRIV_FLAGS_HIGIG    BIT_ULL(2)
+#define OTX2_PRIV_FLAGS_CUSTOM   BIT_ULL(63)
+	uint64_t __otx2_io mode;
+#define PKIND_TX		BIT_ULL(0)
+#define PKIND_RX		BIT_ULL(1)
+	uint8_t __otx2_io dir;
+	uint8_t __otx2_io pkind; /* valid only in case custom flag */
+};
+
 /* Structure for requesting resource provisioning.
  * 'modify' flag to be used when either requesting more
  * or detach partial of a certain resource type.
diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index 62291c698..dfa8cd205 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -90,6 +90,30 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
 	return 0;
 }

+static int
+nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev)
+{
+	struct otx2_mbox *mbox = dev->mbox;
+	struct npc_set_pkind *req;
+	struct msg_resp *rsp;
+	int rc;
+
+	if (dev->npc_flow.switch_header_type == 0)
+		return 0;
+
+	/* Notify AF about higig2 config */
+	req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
+	req->mode = dev->npc_flow.switch_header_type;
+	req->dir = PKIND_RX;
+	rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
+	if (rc)
+		return rc;
+	req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
+	req->mode = dev->npc_flow.switch_header_type;
+	req->dir = PKIND_TX;
+	return otx2_mbox_process_msg(mbox, (void *)&rsp);
+}
+
 static int
 nix_lf_free(struct otx2_eth_dev *dev)
 {
@@ -1612,6 +1636,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
 		goto fail_offloads;
 	}

+	rc = nix_lf_switch_header_type_enable(dev);
+	if (rc) {
+		otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
+		goto free_nix_lf;
+	}
+
 	rc = nix_setup_lso_formats(dev);
 	if (rc) {
 		otx2_err("failed to setup nix lso format fields, rc=%d", rc);
diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c
index 7dc6e92be..ca9a5ffb8 100644
--- a/drivers/net/octeontx2/otx2_ethdev_devargs.c
+++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c
@@ -104,12 +104,27 @@ parse_sqb_count(const char *key, const char *value, void *extra_args)
 	return 0;
 }

+static int
+parse_switch_header_type(const char *key, const char *value, void *extra_args)
+{
+	RTE_SET_USED(key);
+
+	if (strcmp(value, "higig2") == 0)
+		*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_HIGIG;
+
+	if (strcmp(value, "dsa") == 0)
+		*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA;
+
+	return 0;
+}
+
 #define OTX2_RSS_RETA_SIZE "reta_size"
 #define OTX2_PTYPE_DISABLE "ptype_disable"
 #define OTX2_SCL_ENABLE "scalar_enable"
 #define OTX2_MAX_SQB_COUNT "max_sqb_count"
 #define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size"
 #define OTX2_FLOW_MAX_PRIORITY "flow_max_priority"
+#define OTX2_SWITCH_HEADER_TYPE "switch_header"

 int
 otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
@@ -118,6 +133,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
 	uint16_t rss_size = NIX_RSS_RETA_SIZE;
 	uint16_t sqb_count = NIX_MAX_SQB;
 	uint16_t flow_prealloc_size = 8;
+	uint16_t switch_header_type = 0;
 	uint16_t flow_max_priority = 3;
 	uint16_t scalar_enable = 0;
 	struct rte_kvargs *kvlist;
@@ -141,6 +157,8 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
 			   &parse_flow_prealloc_size, &flow_prealloc_size);
 	rte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,
 			   &parse_flow_max_priority, &flow_max_priority);
+	rte_kvargs_process(kvlist, OTX2_SWITCH_HEADER_TYPE,
+			   &parse_switch_header_type, &switch_header_type);
 	rte_kvargs_free(kvlist);

 null_devargs:
@@ -150,6 +168,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
 	dev->rss_info.rss_size = rss_size;
 	dev->npc_flow.flow_prealloc_size = flow_prealloc_size;
 	dev->npc_flow.flow_max_priority = flow_max_priority;
+	dev->npc_flow.switch_header_type = switch_header_type;
 	return 0;

 exit:
@@ -162,4 +181,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,
 			      OTX2_SCL_ENABLE "=1"
 			      OTX2_MAX_SQB_COUNT "=<8-512>"
 			      OTX2_FLOW_PREALLOC_SIZE "=<1-32>"
-			      OTX2_FLOW_MAX_PRIORITY "=<1-32>");
+			      OTX2_FLOW_MAX_PRIORITY "=<1-32>"
+			      OTX2_SWITCH_HEADER_TYPE "=<higig2|dsa>");
diff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h
index ab068b088..6bfd5afde 100644
--- a/drivers/net/octeontx2/otx2_flow.h
+++ b/drivers/net/octeontx2/otx2_flow.h
@@ -190,6 +190,7 @@ struct otx2_npc_flow_info {
 	uint16_t channel; /*rx channel */
 	uint16_t flow_prealloc_size;
 	uint16_t flow_max_priority;
+	uint16_t switch_header_type;
 };

 struct otx2_parse_state {
--
2.17.1

[dpdk-dev] [PATCH v2 2/2] net/octeontx2: add support to parse higig2 hdr

[kirankumark]

From: Kiran Kumar K <kirankumark@marvell.com>

Adding support to parse higig2 header in RTE flow for octeontx2.
And added devargs to configure port for higig2.

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
V2 Changes:
* Fixed checkpatch issue

 doc/guides/nics/octeontx2.rst           |  2 ++
 drivers/common/octeontx2/hw/otx2_npc.h  |  2 ++
 drivers/net/octeontx2/otx2_flow.c       |  1 +
 drivers/net/octeontx2/otx2_flow.h       |  3 ++
 drivers/net/octeontx2/otx2_flow_parse.c | 47 +++++++++++++++++++++++++
 5 files changed, 55 insertions(+)

diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst
index adf7c7131..eb7aaa468 100644
--- a/doc/guides/nics/octeontx2.rst
+++ b/doc/guides/nics/octeontx2.rst
@@ -288,6 +288,8 @@ Patterns:
    +----+--------------------------------+
    | 23 | RTE_FLOW_ITEM_TYPE_GRE_KEY     |
    +----+--------------------------------+
+   | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2      |
+   +----+--------------------------------+

 .. note::

diff --git a/drivers/common/octeontx2/hw/otx2_npc.h b/drivers/common/octeontx2/hw/otx2_npc.h
index 5b8d3ed8c..a0536e0ae 100644
--- a/drivers/common/octeontx2/hw/otx2_npc.h
+++ b/drivers/common/octeontx2/hw/otx2_npc.h
@@ -182,6 +182,8 @@ enum npc_kpu_la_ltype {
 	NPC_LT_LA_IH_8_ETHER,
 	NPC_LT_LA_IH_4_ETHER,
 	NPC_LT_LA_IH_2_ETHER,
+	NPC_LT_LA_HIGIG2_ETHER,
+	NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
 };

 enum npc_kpu_lb_ltype {
diff --git a/drivers/net/octeontx2/otx2_flow.c b/drivers/net/octeontx2/otx2_flow.c
index bdbf123a9..f1fb9f988 100644
--- a/drivers/net/octeontx2/otx2_flow.c
+++ b/drivers/net/octeontx2/otx2_flow.c
@@ -325,6 +325,7 @@ flow_parse_pattern(struct rte_eth_dev *dev,
 {
 	flow_parse_stage_func_t parse_stage_funcs[] = {
 		flow_parse_meta_items,
+		otx2_flow_parse_higig2_hdr,
 		otx2_flow_parse_la,
 		otx2_flow_parse_lb,
 		otx2_flow_parse_lc,
diff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h
index 6bfd5afde..df78f41d3 100644
--- a/drivers/net/octeontx2/otx2_flow.h
+++ b/drivers/net/octeontx2/otx2_flow.h
@@ -29,6 +29,7 @@ enum {

 #define NPC_IH_LENGTH			8
 #define NPC_TPID_LENGTH			2
+#define NPC_HIGIG2_LENGTH		16
 #define NPC_COUNTER_NONE		(-1)
 /* 32 bytes from LDATA_CFG & 32 bytes from FLAGS_CFG */
 #define NPC_MAX_EXTRACT_DATA_LEN	(64)
@@ -382,6 +383,8 @@ int otx2_flow_parse_lb(struct otx2_parse_state *pst);

 int otx2_flow_parse_la(struct otx2_parse_state *pst);

+int otx2_flow_parse_higig2_hdr(struct otx2_parse_state *pst);
+
 int otx2_flow_parse_actions(struct rte_eth_dev *dev,
 			    const struct rte_flow_attr *attr,
 			    const struct rte_flow_action actions[],
diff --git a/drivers/net/octeontx2/otx2_flow_parse.c b/drivers/net/octeontx2/otx2_flow_parse.c
index 2cba0a447..b7b7b6127 100644
--- a/drivers/net/octeontx2/otx2_flow_parse.c
+++ b/drivers/net/octeontx2/otx2_flow_parse.c
@@ -675,6 +675,15 @@ otx2_flow_parse_la(struct otx2_parse_state *pst)
 	if (pst->flow->nix_intf == NIX_INTF_TX) {
 		lt = NPC_LT_LA_IH_NIX_ETHER;
 		info.hw_hdr_len = NPC_IH_LENGTH;
+		if (pst->npc->switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+			lt = NPC_LT_LA_IH_NIX_HIGIG2_ETHER;
+			info.hw_hdr_len += NPC_HIGIG2_LENGTH;
+		}
+	} else {
+		if (pst->npc->switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+			lt = NPC_LT_LA_HIGIG2_ETHER;
+			info.hw_hdr_len = NPC_HIGIG2_LENGTH;
+		}
 	}

 	/* Prepare for parsing the item */
@@ -694,6 +703,44 @@ otx2_flow_parse_la(struct otx2_parse_state *pst)
 	return otx2_flow_update_parse_state(pst, &info, lid, lt, 0);
 }

+int
+otx2_flow_parse_higig2_hdr(struct otx2_parse_state *pst)
+{
+	struct rte_flow_item_higig2_hdr hw_mask;
+	struct otx2_flow_item_info info;
+	int lid, lt;
+	int rc;
+
+	/* Identify the pattern type into lid, lt */
+	if (pst->pattern->type != RTE_FLOW_ITEM_TYPE_HIGIG2)
+		return 0;
+
+	lid = NPC_LID_LA;
+	lt = NPC_LT_LA_HIGIG2_ETHER;
+	info.hw_hdr_len = 0;
+
+	if (pst->flow->nix_intf == NIX_INTF_TX) {
+		lt = NPC_LT_LA_IH_NIX_HIGIG2_ETHER;
+		info.hw_hdr_len = NPC_IH_LENGTH;
+	}
+
+	/* Prepare for parsing the item */
+	info.def_mask = &rte_flow_item_higig2_hdr_mask;
+	info.hw_mask = &hw_mask;
+	info.len = sizeof(struct rte_flow_item_higig2_hdr);
+	otx2_flow_get_hw_supp_mask(pst, &info, lid, lt);
+	info.spec = NULL;
+	info.mask = NULL;
+
+	/* Basic validation of item parameters */
+	rc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);
+	if (rc)
+		return rc;
+
+	/* Update pst if not validate only? clash check? */
+	return otx2_flow_update_parse_state(pst, &info, lid, lt, 0);
+}
+
 static int
 parse_rss_action(struct rte_eth_dev *dev,
 		 const struct rte_flow_attr *attr,
--
2.17.1

Re: [dpdk-dev] [PATCH v2 1/2] net/octeontx2: add support to enable switch type

[Jerin Jacob]

On Wed, Oct 23, 2019 at 8:56 PM <kirankumark@marvell.com> wrote:
>
> From: Kiran Kumar K <kirankumark@marvell.com>
>
> Adding support to configure specific switch types like high2 and dsa
> on a port. When this switch type is configured, it is expected that
> all the traffic on that port should be of specific type only.
>
> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
> ---
> V2 Changes:
> * Fixed checkpatch issue

Series Acked-by: Jerin Jacob <jerinj@marvell.com>

Series applied to dpdk-next-net-mrvl/master. Thanks.


>
>  doc/guides/nics/octeontx2.rst               | 12 +++++++++
>  drivers/common/octeontx2/otx2_mbox.h        | 19 ++++++++++++-
>  drivers/net/octeontx2/otx2_ethdev.c         | 30 +++++++++++++++++++++
>  drivers/net/octeontx2/otx2_ethdev_devargs.c | 22 ++++++++++++++-
>  drivers/net/octeontx2/otx2_flow.h           |  1 +
>  5 files changed, 82 insertions(+), 2 deletions(-)
>
> diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst
> index fc8a130fb..adf7c7131 100644
> --- a/doc/guides/nics/octeontx2.rst
> +++ b/doc/guides/nics/octeontx2.rst
> @@ -170,6 +170,18 @@ Runtime Config Options
>     With the above configuration, each send queue's decscriptor buffer count is
>     limited to a maximum of 64 buffers.
>
> +- ``switch header enable`` (default ``none``)
> +
> +   A port can be configured to a specific switch header type by using
> +   ``switch_header`` ``devargs`` parameter.
> +
> +   For example::
> +
> +      -w 0002:02:00.0,switch_header="higig2"
> +
> +   With the above configuration, higig2 will be enabled on that port and the
> +   traffic on this port should be higig2 traffic only. Supported switch header
> +   types are "higig2" and "dsa".
>
>  .. note::
>
> diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h
> index 445b03e26..c2a9e9fe6 100644
> --- a/drivers/common/octeontx2/otx2_mbox.h
> +++ b/drivers/common/octeontx2/otx2_mbox.h
> @@ -89,7 +89,7 @@ struct mbox_msghdr {
>  #define OTX2_MBOX_RSP_SIG (0xbeef)
>         /* Signature, for validating corrupted msgs */
>         uint16_t __otx2_io sig;
> -#define OTX2_MBOX_VERSION (0x0002)
> +#define OTX2_MBOX_VERSION (0x0003)
>         /* Version of msg's structure for this ID */
>         uint16_t __otx2_io ver;
>         /* Offset of next msg within mailbox region */
> @@ -236,6 +236,9 @@ M(NPC_DELETE_FLOW,    0x600e, npc_delete_flow,                      \
>  M(NPC_MCAM_READ_ENTRY,   0x600f, npc_mcam_read_entry,                  \
>                                   npc_mcam_read_entry_req,              \
>                                   npc_mcam_read_entry_rsp)              \
> +M(NPC_SET_PKIND,          0x6010, npc_set_pkind,                        \
> +                                 npc_set_pkind,                        \
> +                                 msg_rsp)                              \
>  /* NIX mbox IDs (range 0x8000 - 0xFFFF) */                             \
>  M(NIX_LF_ALLOC,                0x8000, nix_lf_alloc, nix_lf_alloc_req,         \
>                                 nix_lf_alloc_rsp)                       \
> @@ -329,6 +332,20 @@ struct ready_msg_rsp {
>         uint16_t __otx2_io rclk_freq; /* RCLK frequency */
>  };
>
> +/* Struct to set pkind */
> +struct npc_set_pkind {
> +       struct mbox_msghdr hdr;
> +#define OTX2_PRIV_FLAGS_DEFAULT  BIT_ULL(0)
> +#define OTX2_PRIV_FLAGS_EDSA     BIT_ULL(1)
> +#define OTX2_PRIV_FLAGS_HIGIG    BIT_ULL(2)
> +#define OTX2_PRIV_FLAGS_CUSTOM   BIT_ULL(63)
> +       uint64_t __otx2_io mode;
> +#define PKIND_TX               BIT_ULL(0)
> +#define PKIND_RX               BIT_ULL(1)
> +       uint8_t __otx2_io dir;
> +       uint8_t __otx2_io pkind; /* valid only in case custom flag */
> +};
> +
>  /* Structure for requesting resource provisioning.
>   * 'modify' flag to be used when either requesting more
>   * or detach partial of a certain resource type.
> diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
> index 62291c698..dfa8cd205 100644
> --- a/drivers/net/octeontx2/otx2_ethdev.c
> +++ b/drivers/net/octeontx2/otx2_ethdev.c
> @@ -90,6 +90,30 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
>         return 0;
>  }
>
> +static int
> +nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev)
> +{
> +       struct otx2_mbox *mbox = dev->mbox;
> +       struct npc_set_pkind *req;
> +       struct msg_resp *rsp;
> +       int rc;
> +
> +       if (dev->npc_flow.switch_header_type == 0)
> +               return 0;
> +
> +       /* Notify AF about higig2 config */
> +       req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
> +       req->mode = dev->npc_flow.switch_header_type;
> +       req->dir = PKIND_RX;
> +       rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
> +       if (rc)
> +               return rc;
> +       req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
> +       req->mode = dev->npc_flow.switch_header_type;
> +       req->dir = PKIND_TX;
> +       return otx2_mbox_process_msg(mbox, (void *)&rsp);
> +}
> +
>  static int
>  nix_lf_free(struct otx2_eth_dev *dev)
>  {
> @@ -1612,6 +1636,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
>                 goto fail_offloads;
>         }
>
> +       rc = nix_lf_switch_header_type_enable(dev);
> +       if (rc) {
> +               otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
> +               goto free_nix_lf;
> +       }
> +
>         rc = nix_setup_lso_formats(dev);
>         if (rc) {
>                 otx2_err("failed to setup nix lso format fields, rc=%d", rc);
> diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c
> index 7dc6e92be..ca9a5ffb8 100644
> --- a/drivers/net/octeontx2/otx2_ethdev_devargs.c
> +++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c
> @@ -104,12 +104,27 @@ parse_sqb_count(const char *key, const char *value, void *extra_args)
>         return 0;
>  }
>
> +static int
> +parse_switch_header_type(const char *key, const char *value, void *extra_args)
> +{
> +       RTE_SET_USED(key);
> +
> +       if (strcmp(value, "higig2") == 0)
> +               *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_HIGIG;
> +
> +       if (strcmp(value, "dsa") == 0)
> +               *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA;
> +
> +       return 0;
> +}
> +
>  #define OTX2_RSS_RETA_SIZE "reta_size"
>  #define OTX2_PTYPE_DISABLE "ptype_disable"
>  #define OTX2_SCL_ENABLE "scalar_enable"
>  #define OTX2_MAX_SQB_COUNT "max_sqb_count"
>  #define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size"
>  #define OTX2_FLOW_MAX_PRIORITY "flow_max_priority"
> +#define OTX2_SWITCH_HEADER_TYPE "switch_header"
>
>  int
>  otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
> @@ -118,6 +133,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
>         uint16_t rss_size = NIX_RSS_RETA_SIZE;
>         uint16_t sqb_count = NIX_MAX_SQB;
>         uint16_t flow_prealloc_size = 8;
> +       uint16_t switch_header_type = 0;
>         uint16_t flow_max_priority = 3;
>         uint16_t scalar_enable = 0;
>         struct rte_kvargs *kvlist;
> @@ -141,6 +157,8 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
>                            &parse_flow_prealloc_size, &flow_prealloc_size);
>         rte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,
>                            &parse_flow_max_priority, &flow_max_priority);
> +       rte_kvargs_process(kvlist, OTX2_SWITCH_HEADER_TYPE,
> +                          &parse_switch_header_type, &switch_header_type);
>         rte_kvargs_free(kvlist);
>
>  null_devargs:
> @@ -150,6 +168,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)
>         dev->rss_info.rss_size = rss_size;
>         dev->npc_flow.flow_prealloc_size = flow_prealloc_size;
>         dev->npc_flow.flow_max_priority = flow_max_priority;
> +       dev->npc_flow.switch_header_type = switch_header_type;
>         return 0;
>
>  exit:
> @@ -162,4 +181,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,
>                               OTX2_SCL_ENABLE "=1"
>                               OTX2_MAX_SQB_COUNT "=<8-512>"
>                               OTX2_FLOW_PREALLOC_SIZE "=<1-32>"
> -                             OTX2_FLOW_MAX_PRIORITY "=<1-32>");
> +                             OTX2_FLOW_MAX_PRIORITY "=<1-32>"
> +                             OTX2_SWITCH_HEADER_TYPE "=<higig2|dsa>");
> diff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h
> index ab068b088..6bfd5afde 100644
> --- a/drivers/net/octeontx2/otx2_flow.h
> +++ b/drivers/net/octeontx2/otx2_flow.h
> @@ -190,6 +190,7 @@ struct otx2_npc_flow_info {
>         uint16_t channel; /*rx channel */
>         uint16_t flow_prealloc_size;
>         uint16_t flow_max_priority;
> +       uint16_t switch_header_type;
>  };
>
>  struct otx2_parse_state {
> --
> 2.17.1
>