From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D286CA00BE; Wed, 30 Oct 2019 18:25:08 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 383541C0BC; Wed, 30 Oct 2019 18:25:07 +0100 (CET) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by dpdk.org (Postfix) with ESMTP id C69211C0B9 for ; Wed, 30 Oct 2019 18:25:05 +0100 (CET) Received: by mail-io1-f65.google.com with SMTP id r144so3449948iod.8 for ; Wed, 30 Oct 2019 10:25:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=k0A4gPlYNPFyz6XNXOsLjNEXiU71ddXN5zNwzKcZOoY=; b=ZLa7I39+ljoptEhNuN/LR/Un5R5VgDT4K6wENo/brNfumZ9gI+sgrGY2RTFvrHKBDW h4Vd+63ieSioeBM3XK677TfvsviKmGyHgh1nIv8IKn4KWq0a2+EZI00Q0fau9YTE2Up4 R6yp+ztufIJJe01iCZKbTs/n9FRTOD8J6BfO8uXt+UU89TIzPnmynzmOxh/7loA/uYEg hnr9e2SRWVvAtd6iXzvRoEbbyIs5WOEUVOKyuxwx3ssmE7HZByo9MLReOLGQbjB/jWbe NNqg8x91Kj6AqbulnnXMUDWVLZA9qve9nDWC+3DsybOST+7ROFc32eLjkuabMgZV7s/1 lgtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=k0A4gPlYNPFyz6XNXOsLjNEXiU71ddXN5zNwzKcZOoY=; b=cA0hKhWpG02gDvcvPBDMDTq1nhcNZrNLX6Dg17tQiCbl9nZhS0IJo9ndQOQyTsXwcQ +syE7qO2DiBQlV2E3nwf5B0foabiwVMi/JMs1JfO7RKQZ8iciqkqWxaldiQwi95bWF9J 3OPPKdqzxehP1XEyCUh6c3m4L0Mta9N+Zul5JZwwWutyC+hcmRgAd+XRJQJ8Urs+nIOE gMXVvApF9UxVry90pzT1PDpKN+F5qy110BJdIpTtNN2Y75UYILCK3R/X7Tn99BIaewwR EenijJcLjHVEbbcMVDqZcrtnsHRNeLv9/gpcA/iLl8LyYNXEsay61mZgz/b6BrWGhfNM MJzg== X-Gm-Message-State: APjAAAWzarh9M+t5ist1+PrjYc2VIgqU46xn542CWxtAbN5+TNcfosxI rRnlB7b2Z87CboWI4tvW4Wv3e/P4QoiZuc0unOQH7/QrTCM= X-Google-Smtp-Source: APXvYqzl2hE4s92XRBi0Pf4IoT5JbJD6lIndcmjFngh937w6Xl0TuKC9Pe4JCtrp6L2djmv/bYIzjayEkDS8XpZfwm8= X-Received: by 2002:a02:cea7:: with SMTP id z7mr755295jaq.104.1572456304648; Wed, 30 Oct 2019 10:25:04 -0700 (PDT) MIME-Version: 1.0 References: <20191023152043.17887-1-kirankumark@marvell.com> <20191023152549.18658-1-kirankumark@marvell.com> In-Reply-To: <20191023152549.18658-1-kirankumark@marvell.com> From: Jerin Jacob Date: Wed, 30 Oct 2019 22:54:48 +0530 Message-ID: To: Kiran Kumar K , Ferruh Yigit Cc: Jerin Jacob , Nithin Dabilpuram , John McNamara , Marko Kovacevic , Vamsi Attunuru , dpdk-dev Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v2 1/2] net/octeontx2: add support to enable switch type X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Wed, Oct 23, 2019 at 8:56 PM wrote: > > From: Kiran Kumar K > > Adding support to configure specific switch types like high2 and dsa > on a port. When this switch type is configured, it is expected that > all the traffic on that port should be of specific type only. > > Signed-off-by: Kiran Kumar K > --- > V2 Changes: > * Fixed checkpatch issue Series Acked-by: Jerin Jacob Series applied to dpdk-next-net-mrvl/master. Thanks. > > doc/guides/nics/octeontx2.rst | 12 +++++++++ > drivers/common/octeontx2/otx2_mbox.h | 19 ++++++++++++- > drivers/net/octeontx2/otx2_ethdev.c | 30 +++++++++++++++++++++ > drivers/net/octeontx2/otx2_ethdev_devargs.c | 22 ++++++++++++++- > drivers/net/octeontx2/otx2_flow.h | 1 + > 5 files changed, 82 insertions(+), 2 deletions(-) > > diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst > index fc8a130fb..adf7c7131 100644 > --- a/doc/guides/nics/octeontx2.rst > +++ b/doc/guides/nics/octeontx2.rst > @@ -170,6 +170,18 @@ Runtime Config Options > With the above configuration, each send queue's decscriptor buffer count is > limited to a maximum of 64 buffers. > > +- ``switch header enable`` (default ``none``) > + > + A port can be configured to a specific switch header type by using > + ``switch_header`` ``devargs`` parameter. > + > + For example:: > + > + -w 0002:02:00.0,switch_header="higig2" > + > + With the above configuration, higig2 will be enabled on that port and the > + traffic on this port should be higig2 traffic only. Supported switch header > + types are "higig2" and "dsa". > > .. note:: > > diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h > index 445b03e26..c2a9e9fe6 100644 > --- a/drivers/common/octeontx2/otx2_mbox.h > +++ b/drivers/common/octeontx2/otx2_mbox.h > @@ -89,7 +89,7 @@ struct mbox_msghdr { > #define OTX2_MBOX_RSP_SIG (0xbeef) > /* Signature, for validating corrupted msgs */ > uint16_t __otx2_io sig; > -#define OTX2_MBOX_VERSION (0x0002) > +#define OTX2_MBOX_VERSION (0x0003) > /* Version of msg's structure for this ID */ > uint16_t __otx2_io ver; > /* Offset of next msg within mailbox region */ > @@ -236,6 +236,9 @@ M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \ > M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \ > npc_mcam_read_entry_req, \ > npc_mcam_read_entry_rsp) \ > +M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \ > + npc_set_pkind, \ > + msg_rsp) \ > /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \ > M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \ > nix_lf_alloc_rsp) \ > @@ -329,6 +332,20 @@ struct ready_msg_rsp { > uint16_t __otx2_io rclk_freq; /* RCLK frequency */ > }; > > +/* Struct to set pkind */ > +struct npc_set_pkind { > + struct mbox_msghdr hdr; > +#define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0) > +#define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1) > +#define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2) > +#define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63) > + uint64_t __otx2_io mode; > +#define PKIND_TX BIT_ULL(0) > +#define PKIND_RX BIT_ULL(1) > + uint8_t __otx2_io dir; > + uint8_t __otx2_io pkind; /* valid only in case custom flag */ > +}; > + > /* Structure for requesting resource provisioning. > * 'modify' flag to be used when either requesting more > * or detach partial of a certain resource type. > diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c > index 62291c698..dfa8cd205 100644 > --- a/drivers/net/octeontx2/otx2_ethdev.c > +++ b/drivers/net/octeontx2/otx2_ethdev.c > @@ -90,6 +90,30 @@ nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq) > return 0; > } > > +static int > +nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev) > +{ > + struct otx2_mbox *mbox = dev->mbox; > + struct npc_set_pkind *req; > + struct msg_resp *rsp; > + int rc; > + > + if (dev->npc_flow.switch_header_type == 0) > + return 0; > + > + /* Notify AF about higig2 config */ > + req = otx2_mbox_alloc_msg_npc_set_pkind(mbox); > + req->mode = dev->npc_flow.switch_header_type; > + req->dir = PKIND_RX; > + rc = otx2_mbox_process_msg(mbox, (void *)&rsp); > + if (rc) > + return rc; > + req = otx2_mbox_alloc_msg_npc_set_pkind(mbox); > + req->mode = dev->npc_flow.switch_header_type; > + req->dir = PKIND_TX; > + return otx2_mbox_process_msg(mbox, (void *)&rsp); > +} > + > static int > nix_lf_free(struct otx2_eth_dev *dev) > { > @@ -1612,6 +1636,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev) > goto fail_offloads; > } > > + rc = nix_lf_switch_header_type_enable(dev); > + if (rc) { > + otx2_err("Failed to enable switch type nix_lf rc=%d", rc); > + goto free_nix_lf; > + } > + > rc = nix_setup_lso_formats(dev); > if (rc) { > otx2_err("failed to setup nix lso format fields, rc=%d", rc); > diff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c > index 7dc6e92be..ca9a5ffb8 100644 > --- a/drivers/net/octeontx2/otx2_ethdev_devargs.c > +++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c > @@ -104,12 +104,27 @@ parse_sqb_count(const char *key, const char *value, void *extra_args) > return 0; > } > > +static int > +parse_switch_header_type(const char *key, const char *value, void *extra_args) > +{ > + RTE_SET_USED(key); > + > + if (strcmp(value, "higig2") == 0) > + *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_HIGIG; > + > + if (strcmp(value, "dsa") == 0) > + *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA; > + > + return 0; > +} > + > #define OTX2_RSS_RETA_SIZE "reta_size" > #define OTX2_PTYPE_DISABLE "ptype_disable" > #define OTX2_SCL_ENABLE "scalar_enable" > #define OTX2_MAX_SQB_COUNT "max_sqb_count" > #define OTX2_FLOW_PREALLOC_SIZE "flow_prealloc_size" > #define OTX2_FLOW_MAX_PRIORITY "flow_max_priority" > +#define OTX2_SWITCH_HEADER_TYPE "switch_header" > > int > otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) > @@ -118,6 +133,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) > uint16_t rss_size = NIX_RSS_RETA_SIZE; > uint16_t sqb_count = NIX_MAX_SQB; > uint16_t flow_prealloc_size = 8; > + uint16_t switch_header_type = 0; > uint16_t flow_max_priority = 3; > uint16_t scalar_enable = 0; > struct rte_kvargs *kvlist; > @@ -141,6 +157,8 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) > &parse_flow_prealloc_size, &flow_prealloc_size); > rte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY, > &parse_flow_max_priority, &flow_max_priority); > + rte_kvargs_process(kvlist, OTX2_SWITCH_HEADER_TYPE, > + &parse_switch_header_type, &switch_header_type); > rte_kvargs_free(kvlist); > > null_devargs: > @@ -150,6 +168,7 @@ otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev) > dev->rss_info.rss_size = rss_size; > dev->npc_flow.flow_prealloc_size = flow_prealloc_size; > dev->npc_flow.flow_max_priority = flow_max_priority; > + dev->npc_flow.switch_header_type = switch_header_type; > return 0; > > exit: > @@ -162,4 +181,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2, > OTX2_SCL_ENABLE "=1" > OTX2_MAX_SQB_COUNT "=<8-512>" > OTX2_FLOW_PREALLOC_SIZE "=<1-32>" > - OTX2_FLOW_MAX_PRIORITY "=<1-32>"); > + OTX2_FLOW_MAX_PRIORITY "=<1-32>" > + OTX2_SWITCH_HEADER_TYPE "="); > diff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h > index ab068b088..6bfd5afde 100644 > --- a/drivers/net/octeontx2/otx2_flow.h > +++ b/drivers/net/octeontx2/otx2_flow.h > @@ -190,6 +190,7 @@ struct otx2_npc_flow_info { > uint16_t channel; /*rx channel */ > uint16_t flow_prealloc_size; > uint16_t flow_max_priority; > + uint16_t switch_header_type; > }; > > struct otx2_parse_state { > -- > 2.17.1 >