From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 94504A04B5; Tue, 12 Jan 2021 05:39:50 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7C84B140D01; Tue, 12 Jan 2021 05:39:50 +0100 (CET) Received: from mail-io1-f42.google.com (mail-io1-f42.google.com [209.85.166.42]) by mails.dpdk.org (Postfix) with ESMTP id 8A267140CFE; Tue, 12 Jan 2021 05:39:48 +0100 (CET) Received: by mail-io1-f42.google.com with SMTP id z5so1366564iob.11; Mon, 11 Jan 2021 20:39:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=yjes3EMeTjukf3/0aoHi3vJGsGZInHrkt1C9U854aqI=; b=r8KUdVvCMthi9EIjwmJLi4aCd8ULUJIY9gA591tGujE7i1WsjK7HsRbsZSZdf+5CoQ bYYNv246AJIvarxO/9zXuxn+TEzMLKHamCT9QOVropfkZrdQSkmwwHRwhtI1PEnM5Pgv cOH4zJkfTos5LLZNoHVB+kSR0zmM+tzG0nTcf469eGWeYQmxyuvdKBlq2VHWvOscZkOj JY/6OpeKXp+c/6YvnTTv1hFwGx6+XRdLBMBx2aO9qruZFP0WWwzddlRadn3Vs+7KrE6P ywKkn+IDamCBEPA6v6vMBAZExCn/JOqjtB0THy2iXbYNEuUSoB9y6xN6eDHoplxBzmVW EvYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yjes3EMeTjukf3/0aoHi3vJGsGZInHrkt1C9U854aqI=; b=cuTGlJzXFfNHY143asKIIni3rvFTTSRdJ/b09bLzw8bPUGBj/v1FAEnkcmq1QS76sN Tl5Cm1eF0jGr5og+CJr2xZm8y/0XaK/W6EFf+WXxNvUpNHTb52VGZmjMkDiw/ZaqpWq1 i300OAwRTrMc/Y+BD6tr03Vb4+Dr8zFQifm1WTaQOcXjYpTaCHHER+QyZaoAqolu6s3B Ts3GNKJZY6Y8lgXsAq6zaLnCeXmoc2Sxavo6MpiYe5TDW8o6V2EZHEo81hddBcwddrfJ lC4svpcvoj97GZk5FkuGxrqLlaH53D77Xt7rCZF9h6N7VOC1CSqJQYbKPIl3UWBwywDF GyXQ== X-Gm-Message-State: AOAM533AhKokT1aNqvZwokGDy0KRqP4l2227P6dUAIxaoNMKGL2jwWDd 6ftFM2P2Npqzm6/8ByJczW482rHvxLbE2SmHegw= X-Google-Smtp-Source: ABdhPJy3fYhOKnmnzhaxk25pe5A1BAHjmRKfIObrmO9GPFstIdiEOi8sVjcRI6kkRKQ6sI04hyBHMnsn4ytq3FBZk98= X-Received: by 2002:a02:cba7:: with SMTP id v7mr2509814jap.133.1610426387908; Mon, 11 Jan 2021 20:39:47 -0800 (PST) MIME-Version: 1.0 References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210112025709.1121523-1-ruifeng.wang@arm.com> <20210112025709.1121523-4-ruifeng.wang@arm.com> In-Reply-To: <20210112025709.1121523-4-ruifeng.wang@arm.com> From: Jerin Jacob Date: Tue, 12 Jan 2021 10:09:31 +0530 Message-ID: To: Ruifeng Wang Cc: Harman Kalra , Santosh Shukla , Jerin Jacob , dpdk-dev , Vladimir Medvedkin , Pavan Nikhilesh , Jerin Jacob , Hemant Agrawal , Honnappa Nagarahalli , nd , dpdk stable Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v3 3/5] net/octeontx: fix build with sve enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Tue, Jan 12, 2021 at 8:28 AM Ruifeng Wang wrote: > > Building with gcc 10.2 with SVE extension enabled got error: > > {standard input}: Assembler messages: > {standard input}:91: Error: selected processor does not support `addvl x4,x8,#-1' > {standard input}:95: Error: selected processor does not support `ptrue p1.d,all' > {standard input}:135: Error: selected processor does not support `whilelo p2.d,xzr,x5' > {standard input}:137: Error: selected processor does not support `decb x1' > > This is because inline assembly code explicitly resets cpu model to > not have SVE support. Thus SVE instructions generated by compiler > auto vectorization got rejected by assembler. > > Added SVE to the cpu model specified by inline assembly for SVE support. > Not replacing the inline assembly with C atomics because the driver relies > on specific LSE instruction to interface to co-processor [1]. > > Fixes: f0c7bb1bf778 ("net/octeontx/base: add octeontx IO operations") > Cc: jerinj@marvell.com > Cc: stable@dpdk.org > > [1] https://mails.dpdk.org/archives/dev/2021-January/196092.html > > Signed-off-by: Ruifeng Wang Reviewed-by: Jerin Jacob > --- > v3: > Keep inline assembly and add sve extension to fix issue. (Pavan) > > drivers/net/octeontx/base/octeontx_io.h | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/octeontx/base/octeontx_io.h b/drivers/net/octeontx/base/octeontx_io.h > index 04b9ce191..d0b9cfbc6 100644 > --- a/drivers/net/octeontx/base/octeontx_io.h > +++ b/drivers/net/octeontx/base/octeontx_io.h > @@ -52,6 +52,11 @@ do { \ > #endif > > #if defined(RTE_ARCH_ARM64) > +#if defined(__ARM_FEATURE_SVE) > +#define __LSE_PREAMBLE " .cpu generic+lse+sve\n" > +#else > +#define __LSE_PREAMBLE " .cpu generic+lse\n" > +#endif > /** > * Perform an atomic fetch-and-add operation. > */ > @@ -61,7 +66,7 @@ octeontx_reg_ldadd_u64(void *addr, int64_t off) > uint64_t old_val; > > __asm__ volatile( > - " .cpu generic+lse\n" > + __LSE_PREAMBLE > " ldadd %1, %0, [%2]\n" > : "=r" (old_val) : "r" (off), "r" (addr) : "memory"); > > @@ -98,12 +103,13 @@ octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[], > > /* LDEOR initiates atomic transfer to I/O device */ > __asm__ volatile( > - " .cpu generic+lse\n" > + __LSE_PREAMBLE > " ldeor xzr, %0, [%1]\n" > : "=r" (result) : "r" (ioreg_va) : "memory"); > } while (!result); > } > > +#undef __LSE_PREAMBLE > #else > > static inline uint64_t > -- > 2.25.1 >